OV - exec - Loop 476

	Loop Id: 476	Module: exec	Source: advec_mom_kernel.f90-pp.f90:214-242 [...]	Coverage: 3.86%

  (475) 0x41e760 ADD	X13, X8, #1

  (475) 0x41e764 ORR	X8, XZR, X13

  (475) 0x41e768 SUBS	W9, W9, #1

  (475) 0x41e76c B.LE	41e8a8

  (475) 0x41e770 CMP	W11, #0

  (475) 0x41e774 B.LE	41e760

0x41e778 LDR	X13, [X20, #64]

0x41e77c LDR	X2, [X20, #224]

0x41e780 LDR	X15, [X20, #256]

0x41e784 SUB	W16, W8, #1

0x41e788 ADD	W17, W8, #2

0x41e78c LDR	X14, [X13]

0x41e790 LDR	X13, [X20, #104]

0x41e794 MADD	X18, X8, X14, XZR

0x41e798 LDR	X1, [X13]

0x41e79c ADD	X13, X8, #1

0x41e7a0 UBFM	X3, X18, #61, #60

0x41e7a4 LDP	X18, X0, [X20, #288]

0x41e7a8 ADD	X2, X2, X3

0x41e7ac SUB	X1, X10, X1

0x41e7b0 ADD	X0, X0, X3

0x41e7b4 ORR	W3, WZR, W12

0x41e7b8 B	41e7e0

0x41e7c0 FSUB	D4, D0, S4

0x41e7c4 SUB	W3, W3, #1

0x41e7c8 CMP	W3, #1

0x41e7cc FMADD	D4, D4, D16, D5

0x41e7d0 FMUL	D3, D3, D4

0x41e7d4 STR	D3, [X0, X1,LSL #3]

0x41e7d8 ADD	X1, X1, #1

0x41e7dc B.LE	41e764

0x41e7e0 LDR	D3, [X2, X1,LSL #3]

0x41e7e4 MOVI	D16, #0

0x41e7e8 FCMP	D3, #0

0x41e7ec FABS	D4, D3

0x41e7f0 CSINC	W5, W8, W8, #5

0x41e7f4 CSEL	W4, W16, W17, #5

0x41e7f8 CSINC	X6, X8, X8, #4

0x41e7fc SBFM	X5, X5, #0, #31

0x41e800 SBFM	X4, X4, #0, #31

0x41e804 MADD	X5, X14, X5, X1

0x41e808 MADD	X4, X14, X4, X1

0x41e80c LDR	D5, [X15, X5,LSL #3]

0x41e810 LDR	D6, [X18, X4,LSL #3]

0x41e814 MADD	X4, X14, X6, X1

0x41e818 FDIV	D4, D4, D5

0x41e81c LDR	D5, [X18, X5,LSL #3]

0x41e820 FSUB	D7, D5, S6

0x41e824 LDR	D6, [X18, X4,LSL #3]

0x41e828 FSUB	D6, D6, S5

0x41e82c FMUL	D17, D7, D6

0x41e830 FCMP	D17, #0

0x41e834 B.LE	41e7c0

0x41e838 LDP	X5, X6, [X20, #312]

0x41e83c FCMP	D3, #0

0x41e840 FABS	D7, D7

0x41e844 FADD	D18, D4, D0

0x41e848 CSEL	W4, W16, W13, #5

0x41e84c FMUL	D18, D18, D7

0x41e850 FABS	D17, D6

0x41e854 SBFM	X4, X4, #0, #31

0x41e858 LDR	X6, [X6]

0x41e85c SUB	X4, X4, X6

0x41e860 SUB	X7, X8, X6

0x41e864 LDR	D19, [X5, X4,LSL #3]

0x41e868 LDR	D16, [X5, X7,LSL #3]

0x41e86c FDIV	D18, D18, D19

0x41e870 FSUB	D19, D1, S4

0x41e874 FMUL	D19, D19, D17

0x41e878 FDIV	D19, D19, D16

0x41e87c FADD	D18, D19, D18

0x41e880 FMUL	D16, D16, D18

0x41e884 FDIV	D16, D16, D2

0x41e888 FCMP	D16, D7

0x41e88c FCSEL	D7, D7, D16, #10

0x41e890 FCMP	D7, D17

0x41e894 FCSEL	D7, D17, D7, #10

0x41e898 FCMP	D6, #0

0x41e89c FNEG	D16, D7

0x41e8a0 FCSEL	D16, D7, D16, #8

0x41e8a4 B	41e7c0

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 214 - 242

--------------------------------------------------------------------------------

214:       DO k=y_min-1,y_max+1

215:         DO j=x_min,x_max+1

[...]

227: # 227 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90"

228:           sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor))

229:           width=celldy(k)

230:           vdiffuw=vel1(j,donor)-vel1(j,upwind)

231:           vdiffdw=vel1(j,downwind)-vel1(j,donor)

232:           limiter=0.0

233:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

234:             auw=ABS(vdiffuw)

235:             adw=ABS(vdiffdw)

236:             wind=1.0_8

237:             IF(vdiffdw.LE.0.0) wind=-1.0_8

238:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw)

239:           ENDIF

240:           advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter

241:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

242:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	3.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.69 - 7.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:214-215,advec_mom_kernel.f90-pp.f90:227-234,advec_mom_kernel.f90-pp.f90:237-241
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.38
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	9.38
CQA cycles if fully vectorized	2.00 - 1.30
Front-end cycles	9.38
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	7.75
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	5.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.81
Nb FLOP add-sub	6.00
Nb FLOP mul	5.00
Nb FLOP fma	1.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.21
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.54
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	3.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.69 - 7.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:214-215,advec_mom_kernel.f90-pp.f90:227-234,advec_mom_kernel.f90-pp.f90:237-241
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.38
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	9.38
CQA cycles if fully vectorized	2.00 - 1.30
Front-end cycles	9.38
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	7.75
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	5.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.81
Nb FLOP add-sub	6.00
Nb FLOP mul	5.00
Nb FLOP fma	1.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.21
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.54
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:214-242
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:214-215,227-242.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:214-215,227-234,237-241.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.38 to 2.83 cycles (3.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.38 to 1.30 cycles (7.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (1 inside FMA instructions)
6: multiply (1 inside FMA instructions)
4: divide

The binary loop is loading 144 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.00	6.00	6.00	6.00	7.75	7.75	7.75	7.75	5.83	5.50	5.67	0.00	0.00
cycles	2.00	2.00	6.00	6.00	6.00	6.00	7.75	7.75	7.75	7.75	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

4.00-2.00

Cycles summary

Front-end	9.38
Overall L1	9.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.38 cycles. At this rate:

16% of peak load performance is reached (15.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.85 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X13, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X20, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X20, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W16, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W17, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X18, X8, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X1, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X13, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X3, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X18, X0, [X20, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD X2, X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X1, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W3, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 41e7e0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x16b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FSUB D4, D0, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMADD D4, D4, D16, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D3, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D3, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 41e764 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1634>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CSINC W5, W8, W8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSEL W4, W16, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC X6, X8, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X5, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X4, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X14, X5, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X4, X14, X4, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D5, [X15, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X4, X14, X6, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FDIV D4, D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D5, [X18, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D7, D5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D6, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D6, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D17, D7, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LE 41e7c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X6, [X20, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D18, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CSEL W4, W16, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D18, D18, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D17, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SBFM X4, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X4, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X7, X8, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D19, [X5, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X5, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D18, D18, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D19, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D19, D19, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D19, D19, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FADD D18, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D16, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D16, D16, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FCMP D16, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D7, D7, D16, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D7, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D7, D17, D7, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D16, D7, D16, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
B 41e7c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:214-242
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.38 to 2.83 cycles (3.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (1 inside FMA instructions)
6: multiply (1 inside FMA instructions)
4: divide

The binary loop is loading 144 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.00	6.00	6.00	6.00	7.75	7.75	7.75	7.75	5.83	5.50	5.67	0.00	0.00
cycles	2.00	2.00	6.00	6.00	6.00	6.00	7.75	7.75	7.75	7.75	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

4.00-2.00

Cycles summary

Front-end	9.38
Overall L1	9.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.38 cycles. At this rate:

16% of peak load performance is reached (15.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.85 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X13, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X20, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X20, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W16, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W17, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X18, X8, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X1, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X13, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X3, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X18, X0, [X20, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD X2, X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X1, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W3, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 41e7e0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x16b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FSUB D4, D0, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMADD D4, D4, D16, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D3, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D3, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 41e764 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1634>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CSINC W5, W8, W8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSEL W4, W16, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC X6, X8, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X5, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X4, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X14, X5, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X4, X14, X4, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D5, [X15, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X4, X14, X6, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FDIV D4, D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D5, [X18, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D7, D5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D6, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D6, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D17, D7, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LE 41e7c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X6, [X20, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D18, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CSEL W4, W16, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D18, D18, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D17, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SBFM X4, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X4, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X7, X8, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D19, [X5, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X5, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D18, D18, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D19, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D19, D19, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D19, D19, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FADD D18, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D16, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D16, D16, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FCMP D16, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D7, D7, D16, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D7, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D7, D17, D7, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D16, D7, D16, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
B 41e7c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code