OV - exec - Loop 472

	Loop Id: 472	Module: exec	Source: advec_mom_kernel.f90-pp.f90:247-250	Coverage: 0.01%

0x41e94c ADD	X8, X8, #1

0x41e950 SUBS	W9, W9, #1

0x41e954 ADD	X13, X13, #1

0x41e958 B.LE	41eac0

0x41e95c CMP	W11, #1

0x41e960 B.LT	41e94c

0x41e964 LDR	X15, [X20, #64]

0x41e968 LDP	X16, X17, [X20, #288]

0x41e96c LDR	X1, [X20, #240]

0x41e970 ORR	X4, XZR, X10

0x41e974 ORR	W2, WZR, W11

0x41e978 CMP	X12, X14

0x41e97c LDR	X18, [X15]

0x41e980 LDR	X15, [X20, #104]

0x41e984 LDR	X0, [X15]

0x41e988 LDR	X15, [X20, #256]

0x41e98c B.CC	41ea58

0x41e990 UDIV	X2, X12, X14

0x41e994 MADD	X4, X18, X13, X10

0x41e998 MADD	X5, X18, X8, X10

0x41e99c ORR	X3, XZR, XZR

0x41e9a0 SUB	X4, X4, X0

0x41e9a4 SUB	X19, X5, X0

0x41e9a8 UBFM	X4, X4, #61, #60

0x41e9ac UBFM	X27, X19, #61, #60

0x41e9b0 ADD	X6, X17, X4

0x41e9b4 ADDVL	X4, X4, #1

0x41e9b8 ADDVL	X28, X27, #1

0x41e9bc ADD	X22, X1, X27

0x41e9c0 ADD	X24, X17, X27

0x41e9c4 ADD	X26, X16, X27

0x41e9c8 ADD	X27, X15, X27

0x41e9cc ADD	X7, X17, X4

0x41e9d0 ADD	X23, X1, X28

0x41e9d4 ADD	X25, X17, X28

0x41e9d8 ADD	X19, X16, X28

0x41e9dc ADD	X28, X15, X28

0x41e9e0 MADD	X21, X2, X14, XZR

0x41e9e4 SUB	X5, X12, X21

0x41e9e8 ADD	X4, X21, X10

0x41e9ec SUB	W2, W11, W21

0x41e9f0 HINT	#0

0x41e9f4 HINT	#0

0x41e9f8 HINT	#0

0x41e9fc HINT	#0

  (474) 0x41ea00 LD1D	{Z0.D}, P0/Z, [X6, X3,LSL #3]

  (474) 0x41ea04 LD1D	{Z1.D}, P0/Z, [X7, X3,LSL #3]

  (474) 0x41ea08 LD1D	{Z2.D}, P0/Z, [X27, X3,LSL #3]

  (474) 0x41ea0c LD1D	{Z3.D}, P0/Z, [X28, X3,LSL #3]

  (474) 0x41ea10 LD1D	{Z4.D}, P0/Z, [X26, X3,LSL #3]

  (474) 0x41ea14 FMLA	Z0.D, P0/M, Z2.D, Z4.D

  (474) 0x41ea18 LD1D	{Z5.D}, P0/Z, [X19, X3,LSL #3]

  (474) 0x41ea1c FMLA	Z1.D, P0/M, Z3.D, Z5.D

  (474) 0x41ea20 LD1D	{Z2.D}, P0/Z, [X24, X3,LSL #3]

  (474) 0x41ea24 LD1D	{Z3.D}, P0/Z, [X25, X3,LSL #3]

  (474) 0x41ea28 FSUB	Z0.D, Z0.D, Z2.D

  (474) 0x41ea2c FSUB	Z1.D, Z1.D, Z3.D

  (474) 0x41ea30 LD1D	{Z2.D}, P0/Z, [X22, X3,LSL #3]

  (474) 0x41ea34 LD1D	{Z3.D}, P0/Z, [X23, X3,LSL #3]

  (474) 0x41ea38 FDIV	Z0.D, P0/M, Z0.D, Z2.D

  (474) 0x41ea3c FDIV	Z1.D, P0/M, Z1.D, Z3.D

  (474) 0x41ea40 ST1D	{Z0.D}, P0, [X26, X3,LSL #3]

  (474) 0x41ea44 ST1D	{Z1.D}, P0, [X19, X3,LSL #3]

  (474) 0x41ea48 ADD	X3, X3, X14

  (474) 0x41ea4c CMP	X21, X3

  (474) 0x41ea50 B.NE	41ea00

0x41ea54 CBZ	X5, 41e94c

0x41ea58 MADD	X5, X18, X13, X4

0x41ea5c MADD	X18, X18, X8, X4

0x41ea60 ORR	X3, XZR, XZR

0x41ea64 SUB	X18, X18, X0

0x41ea68 SUB	X5, X5, X0

0x41ea6c UBFM	X0, X18, #61, #60

0x41ea70 ADD	X5, X17, X5,LSL #3

0x41ea74 ADD	X18, X1, X0

0x41ea78 ADD	X17, X17, X0

0x41ea7c ADD	X16, X16, X0

0x41ea80 ADD	X15, X15, X0

0x41ea84 ADD	W0, W2, #1

  (473) 0x41ea88 LDR	D0, [X5, X3]

  (473) 0x41ea8c LDR	D1, [X15, X3]

  (473) 0x41ea90 LDR	D2, [X16, X3]

  (473) 0x41ea94 SUB	W0, W0, #1

  (473) 0x41ea98 CMP	W0, #1

  (473) 0x41ea9c FMADD	D0, D1, D2, D0

  (473) 0x41eaa0 LDR	D1, [X17, X3]

  (473) 0x41eaa4 FSUB	D0, D0, S1

  (473) 0x41eaa8 LDR	D1, [X18, X3]

  (473) 0x41eaac FDIV	D0, D0, D1

  (473) 0x41eab0 STR	D0, [X16, X3]

  (473) 0x41eab4 ADD	X3, X3, #8

  (473) 0x41eab8 B.HI	41ea88

0x41eabc B	41e94c

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 247 - 250

--------------------------------------------------------------------------------

247:       !$OMP SIMD

248:         DO j=x_min,x_max+1

249:           vel1 (j,k)=(vel1(j,k)*node_mass_pre(j,k)+mom_flux(j,k-1)-mom_flux(j,k))/node_mass_post(j,k)

250:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:247-250
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.50
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	0.96
Front-end cycles	3.25
DIV/SQRT cycles	1.67
P0 cycles	1.67
P1 cycles	4.50
P2 cycles	4.50
P3 cycles	4.50
P4 cycles	4.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.56
P10 cycles	1.56
P11 cycles	1.56
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.33 - 0.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.33
Nb uops	26.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.24
Bytes prefetched	0.00
Bytes loaded	42.67
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.72
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.93
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.88

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P0, P1, P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:247-250
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.19
Front-end cycles	0.75
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	6.00
Nb uops	6.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.59
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:247-250
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.75
CQA cycles if no scalar integer	7.75
CQA cycles if FP arith vectorized	7.75
CQA cycles if fully vectorized	1.69
Front-end cycles	5.25
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	7.75
P2 cycles	7.75
P3 cycles	7.75
P4 cycles	7.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.26
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.34
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.88

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:247-250
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	4.75
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	1.00
Front-end cycles	3.75
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.47
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.33
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.88

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:247-250
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:247-250.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.50 to 0.96 cycles (4.70x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 42 bytes.

General properties

nb instructions	27.33
loop length	109.33
nb stack references	0

Front-end

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.67	1.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	1.56	1.56	1.56	0.00	0.00
cycles	1.67	1.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	1.56	1.56	1.56	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.33-0.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.25
Data deps.	1.00
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

7% of peak load performance is reached (7.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:247-250
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.19 cycles (5.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	6
loop length	24
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	0.75
Data deps.	1.00
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 41e95c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
B.LE 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990>	1	0.50	0.50	0	0	0	0	1	0.50
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.LT 41e94c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x181c>	1	0.50	0.50	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:247-250
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.75 to 1.69 cycles (4.59x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	2.00	2.00	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	7.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.75 cycles. At this rate:

8% of peak load performance is reached (8.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e95c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 41e94c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x181c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X16, X17, [X20, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X20, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X4, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 41ea58 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X2, X12, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X4, X18, X13, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X5, X18, X8, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X4, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X4, X4, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X28, X27, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X22, X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X17, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X15, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X1, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X17, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X16, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X15, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X21, X2, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X5, X12, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W11, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X5, 41e94c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x181c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:247-250
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	2.00	2.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.75
Data deps.	1.00
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles. At this rate:

14% of peak load performance is reached (13.47 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e95c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B.LE 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 41e94c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x181c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X16, X17, [X20, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X1, [X20, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X4, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W2, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
LDR X18, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X20, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X20, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B.CC 41ea58 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1928>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD X5, X18, X13, X4	1	0	0	0	0	1	0	0	0	0	2	1
MADD X18, X18, X8, X4	1	0	0	0	0	1	0	0	0	0	2	1
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X18, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X5, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X0, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X17, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W0, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 41e94c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x181c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code