OV - exec - Loop 444

	Loop Id: 444	Module: exec	Source: accelerate_kernel.f90-pp.f90:62-78 [...]	Coverage: 0.01%

0x4198e0 ADD	X8, X8, #1

0x4198e4 SUBS	W9, W9, #1

0x4198e8 ADD	X13, X13, #1

0x4198ec B.LE	419cac

0x4198f0 CMP	W27, #1

0x4198f4 B.LT	4198e0

0x4198f8 LDP	X10, X7, [X20, #112]

0x4198fc LDR	X30, [X20, #32]

0x419900 LDR	X21, [X20, #184]

0x419904 ORR	X24, XZR, X19

0x419908 ORR	W11, WZR, W27

0x41990c CMP	X28, X14

0x419910 LDP	X16, X4, [X20, #216]

0x419914 LDR	X2, [X20, #240]

0x419918 LDP	X29, X0, [X20, #200]

0x41991c LDR	D2, [X10]

0x419920 LDR	X10, [X20, #56]

0x419924 LDR	X18, [X10]

0x419928 LDP	X10, X17, [X20, #96]

0x41992c LDR	X1, [X10]

0x419930 LDR	X10, [X20, #136]

0x419934 LDR	X22, [X10]

0x419938 LDP	X10, X3, [X20, #168]

0x41993c LDR	X23, [X10]

0x419940 B.CC	419b50

0x419944 ORR	X6, XZR, X16

0x419948 UDIV	X16, X28, X14

0x41994c MADD	X10, X18, X8, X19

0x419950 MADD	X11, X18, X13, X19

0x419954 ORR	X24, XZR, X2

0x419958 STR	X1, [SP, #136]

0x41995c ORR	X2, XZR, X3

0x419960 STR	X18, [SP, #152]

0x419964 ORR	W18, WZR, W27

0x419968 ORR	X26, XZR, X0

0x41996c MADD	X0, X22, X8, X19

0x419970 ORR	X5, XZR, X17

0x419974 STR	X7, [SP, #112]

0x419978 ORR	X25, XZR, XZR

0x41997c DUP	Z3.D, Z2.D[0]

0x419980 SUB	X10, X10, X1

0x419984 SUB	X11, X11, X1

0x419988 ORR	X1, XZR, X28

0x41998c STP	X4, X24, [SP, #72]

0x419990 STP	X26, X6, [SP, #96]

0x419994 STR	X2, [SP, #88]

0x419998 UBFM	X10, X10, #61, #60

0x41999c UBFM	X3, X11, #61, #60

0x4199a0 ORR	X11, XZR, X29

0x4199a4 ADD	X28, X4, X10

0x4199a8 ORR	X4, XZR, X30

0x4199ac ADD	X27, X24, X10

0x4199b0 ADD	X29, X29, X10

0x4199b4 ADD	X30, X30, X10

0x4199b8 ADD	X12, X17, X10

0x4199bc ORR	X17, XZR, X19

0x4199c0 STP	X11, X5, [SP, #120]

0x4199c4 ADD	X19, X24, X3

0x4199c8 STR	X4, [SP, #144]

0x4199cc ADD	X10, X4, X3

0x4199d0 ADD	X11, X11, X3

0x4199d4 ADD	X3, X5, X3

0x4199d8 MADD	X4, X16, X14, XZR

0x4199dc SUB	X16, X1, X4

0x4199e0 STR	X16, [SP, #56]

0x4199e4 SUB	W16, W18, W4

0x4199e8 ADD	X24, X4, X17

0x4199ec STR	W16, [SP, #68]

0x4199f0 SUB	X16, X0, X23

0x4199f4 UBFM	X16, X16, #61, #60

0x4199f8 ADD	X5, X26, X16

0x4199fc ADD	X6, X6, X16

0x419a00 ADD	X7, X7, X16

0x419a04 ADD	X0, X21, X16

0x419a08 ADD	X26, X2, X16

0x419a0c MADD	X16, X22, X13, X17

0x419a10 SUB	X16, X16, X23

0x419a14 ADD	X16, X21, X16,LSL #3

0x419a18 HINT	#0

0x419a1c HINT	#0

  (446) 0x419a20 UBFM	X17, X25, #61, #60

  (446) 0x419a24 ADD	X18, X12, X17

  (446) 0x419a28 ADD	X1, X30, X17

  (446) 0x419a2c LD1D	{Z4.D}, P0/Z, [X18, X15,LSL #3]

  (446) 0x419a30 LD1D	{Z5.D}, P0/Z, [X1, X15,LSL #3]

  (446) 0x419a34 LD1D	{Z6.D}, P0/Z, [X18, MUL VL]

  (446) 0x419a38 LD1D	{Z7.D}, P0/Z, [X1, MUL VL]

  (446) 0x419a3c ADD	X18, X3, X17

  (446) 0x419a40 ADD	X1, X10, X17

  (446) 0x419a44 FMUL	Z6.D, Z6.D, Z7.D

  (446) 0x419a48 FMAD	Z4.D, P0/M, Z5.D, Z6.D

  (446) 0x419a4c LD1D	{Z5.D}, P0/Z, [X18, MUL VL]

  (446) 0x419a50 LD1D	{Z6.D}, P0/Z, [X1, MUL VL]

  (446) 0x419a54 LD1D	{Z7.D}, P0/Z, [X18, X15,LSL #3]

  (446) 0x419a58 LD1D	{Z16.D}, P0/Z, [X1, X15,LSL #3]

  (446) 0x419a5c ADD	X18, X11, X17

  (446) 0x419a60 FMUL	Z7.D, Z7.D, Z16.D

  (446) 0x419a64 FMAD	Z5.D, P0/M, Z6.D, Z7.D

  (446) 0x419a68 FADD	Z4.D, Z4.D, Z5.D

  (446) 0x419a6c LD1D	{Z5.D}, P0/Z, [X26, X25,LSL #3]

  (446) 0x419a70 LD1D	{Z6.D}, P0/Z, [X18, MUL VL]

  (446) 0x419a74 LD1D	{Z7.D}, P0/Z, [X18, X15,LSL #3]

  (446) 0x419a78 ADD	X18, X29, X17

  (446) 0x419a7c LD1D	{Z17.D}, P0/Z, [X16, X25,LSL #3]

  (446) 0x419a80 FMUL	Z4.D, Z4.D, Z1.D

  (446) 0x419a84 LD1D	{Z18.D}, P0/Z, [X18, MUL VL]

  (446) 0x419a88 LD1D	{Z19.D}, P0/Z, [X18, X15,LSL #3]

  (446) 0x419a8c LD1D	{Z21.D}, P0/Z, [X0, X25,LSL #3]

  (446) 0x419a90 ADD	X18, X28, X17

  (446) 0x419a94 FDIVR	Z4.D, P0/M, Z4.D, Z3.D

  (446) 0x419a98 FSUB	Z16.D, Z6.D, Z7.D

  (446) 0x419a9c FSUB	Z6.D, Z18.D, Z6.D

  (446) 0x419aa0 FSUB	Z20.D, Z18.D, Z19.D

  (446) 0x419aa4 FSUB	Z7.D, Z19.D, Z7.D

  (446) 0x419aa8 LD1D	{Z19.D}, P0/Z, [X18, X15,LSL #3]

  (446) 0x419aac FMUL	Z20.D, Z20.D, Z21.D

  (446) 0x419ab0 FMAD	Z16.D, P0/M, Z17.D, Z20.D

  (446) 0x419ab4 FMLS	Z5.D, P0/M, Z4.D, Z16.D

  (446) 0x419ab8 LD1D	{Z16.D}, P0/Z, [X6, X25,LSL #3]

  (446) 0x419abc LD1D	{Z18.D}, P0/Z, [X18, MUL VL]

  (446) 0x419ac0 ADD	X18, X19, X17

  (446) 0x419ac4 ADD	X17, X27, X17

  (446) 0x419ac8 FMUL	Z6.D, Z6.D, Z18.D

  (446) 0x419acc FMLA	Z6.D, P0/M, Z7.D, Z19.D

  (446) 0x419ad0 LD1D	{Z7.D}, P0/Z, [X18, MUL VL]

  (446) 0x419ad4 LD1D	{Z20.D}, P0/Z, [X18, X15,LSL #3]

  (446) 0x419ad8 LD1D	{Z22.D}, P0/Z, [X17, MUL VL]

  (446) 0x419adc LD1D	{Z23.D}, P0/Z, [X17, X15,LSL #3]

  (446) 0x419ae0 FSUB	Z24.D, Z22.D, Z23.D

  (446) 0x419ae4 FMUL	Z21.D, Z21.D, Z24.D

  (446) 0x419ae8 FSUB	Z24.D, Z7.D, Z20.D

  (446) 0x419aec FSUB	Z7.D, Z22.D, Z7.D

  (446) 0x419af0 FMUL	Z7.D, Z18.D, Z7.D

  (446) 0x419af4 FMAD	Z17.D, P0/M, Z24.D, Z21.D

  (446) 0x419af8 FMLS	Z5.D, P0/M, Z4.D, Z17.D

  (446) 0x419afc ST1D	{Z5.D}, P0, [X7, X25,LSL #3]

  (446) 0x419b00 MOVPRFX	Z5, Z16

  (446) 0x419b04 FMLS	Z5.D, P0/M, Z4.D, Z6.D

  (446) 0x419b08 FSUB	Z6.D, Z23.D, Z20.D

  (446) 0x419b0c FMAD	Z6.D, P0/M, Z19.D, Z7.D

  (446) 0x419b10 FMSB	Z4.D, P0/M, Z6.D, Z5.D

  (446) 0x419b14 ST1D	{Z4.D}, P0, [X5, X25,LSL #3]

  (446) 0x419b18 ADD	X25, X25, X14

  (446) 0x419b1c CMP	X4, X25

  (446) 0x419b20 B.NE	419a20

0x419b24 LDP	X19, X10, [SP, #48]

0x419b28 LDR	W27, [SP, #44]

0x419b2c LDR	X28, [SP, #32]

0x419b30 LDP	X30, X18, [SP, #144]

0x419b34 LDP	X17, X1, [SP, #128]

0x419b38 LDP	X7, X29, [SP, #112]

0x419b3c LDP	X0, X16, [SP, #96]

0x419b40 LDP	X2, X3, [SP, #80]

0x419b44 LDR	X4, [SP, #72]

0x419b48 LDR	W11, [SP, #68]

0x419b4c CBZ	X10, 4198e0

0x419b50 MADD	X10, X18, X8, X24

0x419b54 ADD	W26, W11, #1

0x419b58 MADD	X11, X22, X13, X24

0x419b5c SUB	X17, X17, #8

0x419b60 MADD	X12, X22, X8, X24

0x419b64 ORR	X25, XZR, XZR

0x419b68 SUB	X11, X11, X23

0x419b6c SUB	X12, X12, X23

0x419b70 SUB	X10, X10, X1

0x419b74 UBFM	X10, X10, #61, #60

0x419b78 ADD	X22, X21, X11,LSL #3

0x419b7c UBFM	X11, X12, #61, #60

0x419b80 ADD	X12, X4, X10

0x419b84 ADD	X4, X16, X11

0x419b88 MADD	X16, X18, X13, X24

0x419b8c ADD	X6, X3, X11

0x419b90 SUB	X12, X12, #8

0x419b94 SUB	X16, X16, X1

0x419b98 ADD	X21, X21, X11

0x419b9c ADD	X3, X7, X11

0x419ba0 ADD	X5, X0, X11

0x419ba4 UBFM	X0, X16, #61, #60

0x419ba8 ADD	X11, X30, X10

0x419bac ADD	X23, X2, X10

0x419bb0 ADD	X7, X29, X10

0x419bb4 ADD	X10, X17, X10

0x419bb8 SUB	X11, X11, #8

0x419bbc ADD	X16, X30, X0

0x419bc0 ADD	X17, X17, X0

0x419bc4 ADD	X18, X2, X0

0x419bc8 ADD	X0, X29, X0

  (445) 0x419bcc ADD	X1, X10, X25

  (445) 0x419bd0 ADD	X2, X11, X25

  (445) 0x419bd4 SUB	W26, W26, #1

  (445) 0x419bd8 CMP	W26, #1

  (445) 0x419bdc LDP	D3, D4, [X1]

  (445) 0x419be0 ADD	X1, X17, X25

  (445) 0x419be4 LDP	D5, D6, [X2]

  (445) 0x419be8 ADD	X2, X16, X25

  (445) 0x419bec LDP	D16, D7, [X1]

  (445) 0x419bf0 LDP	D17, D18, [X2, #1016]

  (445) 0x419bf4 ADD	X1, X0, X25

  (445) 0x419bf8 ADD	X2, X7, X25

  (445) 0x419bfc FMUL	D4, D4, D6

  (445) 0x419c00 FMADD	D3, D3, D5, D4

  (445) 0x419c04 FMUL	D6, D16, D17

  (445) 0x419c08 LDR	D16, [X21, X25]

  (445) 0x419c0c FMADD	D4, D7, D18, D6

  (445) 0x419c10 LDP	D6, D5, [X2, #1016]

  (445) 0x419c14 LDR	D7, [X22, X25]

  (445) 0x419c18 ADD	X2, X12, X25

  (445) 0x419c1c FADD	D3, D3, D4

  (445) 0x419c20 LDP	D17, D4, [X1, #1016]

  (445) 0x419c24 ADD	X1, X18, X25

  (445) 0x419c28 FMUL	D3, D3, D0

  (445) 0x419c2c LDP	D19, D18, [X1, #1016]

  (445) 0x419c30 ADD	X1, X23, X25

  (445) 0x419c34 FSUB	D22, D5, S6

  (445) 0x419c38 LDP	D21, D20, [X1, #1016]

  (445) 0x419c3c FMUL	D22, D22, D16

  (445) 0x419c40 FDIV	D3, D2, D3

  (445) 0x419c44 FSUB	D6, D6, S17

  (445) 0x419c48 FSUB	D23, D20, S21

  (445) 0x419c4c FMUL	D16, D16, D23

  (445) 0x419c50 FSUB	D23, D4, S17

  (445) 0x419c54 FSUB	D4, D5, S4

  (445) 0x419c58 LDR	D5, [X6, X25]

  (445) 0x419c5c LDR	D17, [X4, X25]

  (445) 0x419c60 FMADD	D22, D23, D7, D22

  (445) 0x419c64 FSUB	D23, D18, S19

  (445) 0x419c68 FMADD	D7, D7, D23, D16

  (445) 0x419c6c LDP	D16, D23, [X2]

  (445) 0x419c70 FMADD	D5, D3, D22, D5

  (445) 0x419c74 FMUL	D4, D4, D23

  (445) 0x419c78 FMADD	D4, D6, D16, D4

  (445) 0x419c7c FSUB	D6, D20, S18

  (445) 0x419c80 FMADD	D5, D3, D7, D5

  (445) 0x419c84 FMUL	D6, D23, D6

  (445) 0x419c88 FMADD	D4, D3, D4, D17

  (445) 0x419c8c STR	D5, [X3, X25]

  (445) 0x419c90 FSUB	D5, D21, S19

  (445) 0x419c94 FMADD	D5, D16, D5, D6

  (445) 0x419c98 FMADD	D3, D3, D5, D4

  (445) 0x419c9c STR	D3, [X5, X25]

  (445) 0x419ca0 ADD	X25, X25, #8

  (445) 0x419ca4 B.HI	419bcc

0x419ca8 B	4198e0

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/accelerate_kernel.f90-pp.f90: 62 - 78

--------------------------------------------------------------------------------

62:     !$OMP SIMD

63:       DO j=x_min,x_max+1

[...]

69: # 69 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90"

70:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

71:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

72:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

73:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

74:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

75:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

76:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

77:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

78:       ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	5.69
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks
Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source	accelerate_kernel.f90-pp.f90:62-62,accelerate_kernel.f90-pp.f90:75-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.58
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	7.58
CQA cycles if fully vectorized	4.55
Front-end cycles	6.33
DIV/SQRT cycles	1.67
P0 cycles	1.67
P1 cycles	7.58
P2 cycles	7.58
P3 cycles	7.58
P4 cycles	7.58
P5 cycles	0.17
P6 cycles	0.17
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.56
P10 cycles	5.56
P11 cycles	5.56
P12 cycles	1.67
P13 cycles	1.67
P14 cycles	0.33 - 0.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.33
Nb uops	50.67
Nb loads	NA
Nb stores	3.33
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.95
Bytes prefetched	0.00
Bytes loaded	146.67
Bytes stored	33.33
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.88
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	3.13
Vector-efficiency ratio all	23.31
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.02
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P0, P1, P2, P3, P4, P5,
Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source	accelerate_kernel.f90-pp.f90:62-62,accelerate_kernel.f90-pp.f90:75-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.19
Front-end cycles	0.75
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	6.00
Nb uops	6.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	6.13
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P2, P3, P4, P5,
Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source	accelerate_kernel.f90-pp.f90:62-62,accelerate_kernel.f90-pp.f90:75-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	11.42
Front-end cycles	11.13
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	12.25
P2 cycles	12.25
P3 cycles	12.25
P4 cycles	12.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	11.67
P10 cycles	11.67
P11 cycles	11.67
P12 cycles	5.00
P13 cycles	5.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	91.00
Nb uops	89.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.02
Bytes prefetched	0.00
Bytes loaded	280.00
Bytes stored	100.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	2.63
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	6.25
Vector-efficiency ratio all	25.66
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.31
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	27.34

Metric	Value
CQA speedup if no scalar integer	9.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.68
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P2, P3, P4, P5,
Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source	accelerate_kernel.f90-pp.f90:62-62,accelerate_kernel.f90-pp.f90:75-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	2.03
Front-end cycles	7.13
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	57.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.84
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.91
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source file and lines	accelerate_kernel.f90-pp.f90:62-78
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/accelerate_kernel.f90-pp.f90:62-63,69-78.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/accelerate_kernel.f90-pp.f90:62,75-78.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.58 to 4.55 cycles (1.67x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 146 bytes. The binary loop is storing 33 bytes.

General properties

nb instructions	51.33
loop length	205.33
nb stack references	0

Front-end

front end

6.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.67	1.67	7.58	7.58	7.58	7.58	0.17	0.17	0.00	0.00	5.56	5.56	5.56	1.67	1.67
cycles	1.67	1.67	7.58	7.58	7.58	7.58	0.17	0.17	0.00	0.00	5.56	5.56	5.56	1.67	1.67

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.33-0.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.33
Data deps.	1.00
Overall L1	7.58

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.58 cycles. At this rate:

13% of peak load performance is reached (13.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source file and lines	accelerate_kernel.f90-pp.f90:62-78
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.19 cycles (5.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	6
loop length	24
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	0.75
Data deps.	1.00
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 4198f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
B.LE 419cac <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x49c>	1	0.50	0.50	0	0	0	0	1	0.50
CMP W27, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.LT 4198e0 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0xd0>	1	0.50	0.50	0	0	0	0	1	0.50

Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source file and lines	accelerate_kernel.f90-pp.f90:62-78
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 2.00 cycles (6.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.25 to 11.42 cycles (1.07x speedup).

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 280 bytes. The binary loop is storing 100 bytes.

General properties

nb instructions	91
loop length	364
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	12.25	12.25	12.25	12.25	0.50	0.50	0.00	0.00	11.67	11.67	11.67	5.00	5.00
cycles	2.00	2.00	12.25	12.25	12.25	12.25	0.50	0.50	0.00	0.00	11.67	11.67	11.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.13
Data deps.	1.00
Overall L1	12.25

Vectorization ratios

all	2%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

23% of peak load performance is reached (22.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4198f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 419cac <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4198e0 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X7, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X30, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W11, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X28, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDP X16, X4, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X20, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X0, [X20, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D2, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X10, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X17, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X20, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X3, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 419b50 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X16, X28, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X10, X18, X8, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X11, X18, X13, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X24, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W18, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X0, X22, X8, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X5, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X25, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z3.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
SUB X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X4, X24, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X3, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, X29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X4, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X24, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X29, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X17, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X11, X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X19, X24, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X5, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X4, X16, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X16, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X16, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W16, W18, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W16, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X16, X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X16, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X26, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X16, X22, X13, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X16, X16, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X21, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDP X19, X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W27, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X18, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X29, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X0, X16, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X3, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 4198e0 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source file and lines	accelerate_kernel.f90-pp.f90:62-78
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.00 cycles (9.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 2.03 cycles (4.68x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	5.00	5.00	5.00	0.00	0.00
cycles	2.00	2.00	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	5.00	5.00	5.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.13
Data deps.	1.00
Overall L1	9.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

17% of peak load performance is reached (16.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4198f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B.LE 419cac <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 4198e0 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X10, X7, [X20, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X30, [X20, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X21, [X20, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X24, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W11, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X28, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
LDP X16, X4, [X20, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X2, [X20, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X29, X0, [X20, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR D2, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X10, [X20, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X18, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X10, X17, [X20, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X1, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X20, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X22, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X10, X3, [X20, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X23, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B.CC 419b50 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD X10, X18, X8, X24	1	0	0	0	0	1	0	0	0	0	2	1
ADD W26, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X11, X22, X13, X24	1	0	0	0	0	1	0	0	0	0	2	1
SUB X17, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X12, X22, X8, X24	1	0	0	0	0	1	0	0	0	0	2	1
ORR X25, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X11, X11, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X12, X12, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X22, X21, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X11, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X12, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X16, X18, X13, X24	1	0	0	0	0	1	0	0	0	0	2	1
ADD X6, X3, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X16, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X21, X21, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X7, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X0, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X11, X30, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X2, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X29, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X10, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X29, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 4198e0 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code