OV - exec - Loop 1022

	Loop Id: 1022	Module: exec	Source: viscosity_kernel.f90-pp.f90:56-89	Coverage: 2.48%

0x44a1c0 UBFM	X6, X25, #61, #60

0x44a1c4 ADD	X7, X16, X6

0x44a1c8 ADD	X23, X11, X6

0x44a1cc LD1D	{Z20.D}, P0/Z, [X7, X1,LSL #3]    [15]

0x44a1d0 LD1D	{Z21.D}, P0/Z, [X23, X1,LSL #3]    [2]

0x44a1d4 LD1D	{Z23.D}, P0/Z, [X7, MUL VL]    [5]

0x44a1d8 ADD	X7, X19, X6

0x44a1dc LD1D	{Z24.D}, P0/Z, [X23, MUL VL]    [1]

0x44a1e0 LD1D	{Z26.D}, P0/Z, [X7, X1,LSL #3]    [6]

0x44a1e4 LD1D	{Z27.D}, P0/Z, [X7, MUL VL]    [12]

0x44a1e8 ADD	X7, X12, X6

0x44a1ec ADD	X6, X29, X6

0x44a1f0 LD1D	{Z28.D}, P0/Z, [X7, X1,LSL #3]    [7]

0x44a1f4 FADD	Z25.D, Z23.D, Z24.D

0x44a1f8 LD1D	{Z29.D}, P0/Z, [X7, MUL VL]    [4]

0x44a1fc LD1D	{Z31.D}, P0/Z, [X6, MUL VL]    [14]

0x44a200 FADD	Z22.D, Z20.D, Z21.D

0x44a204 FADD	Z20.D, Z20.D, Z23.D

0x44a208 FSUB	Z22.D, Z22.D, Z25.D

0x44a20c FADD	Z25.D, Z26.D, Z27.D

0x44a210 FSUB	Z20.D, Z20.D, Z24.D

0x44a214 FADD	Z26.D, Z26.D, Z28.D

0x44a218 FSUB	Z20.D, Z20.D, Z21.D

0x44a21c FADD	Z30.D, Z28.D, Z29.D

0x44a220 FSUB	Z26.D, Z26.D, Z29.D

0x44a224 FMUL	Z20.D, P0/M, Z20.D, #0

0x44a228 MOVPRFX	Z21, Z20

0x44a22c FDIV	Z21.D, P0/M, Z21.D, Z16.D

0x44a230 ADD	Z20.D, Z7.D, Z18.D

0x44a234 FSUB	Z25.D, Z25.D, Z30.D

0x44a238 MOVPRFX	Z29, Z25

0x44a23c FMUL	Z29.D, P0/M, Z29.D, #0

0x44a240 FDIV	Z29.D, P0/M, Z29.D, Z16.D

0x44a244 ADD	Z18.D, Z18.D, Z19.D

0x44a248 FSUB	Z26.D, Z26.D, Z27.D

0x44a24c FMOV	X7, D20

0x44a250 FMUL	Z27.D, Z22.D, Z31.D

0x44a254 FMUL	Z22.D, P0/M, Z22.D, #0

0x44a258 FMUL	Z26.D, P0/M, Z26.D, #0

0x44a25c LD1D	{Z23.D}, P0/Z, [X26, X7,LSL #3]    [8]

0x44a260 LD1D	{Z24.D}, P0/Z, [X27, X7,LSL #3]    [13]

0x44a264 FDIV	Z22.D, P0/M, Z22.D, Z31.D

0x44a268 FMAD	Z25.D, P0/M, Z16.D, Z27.D

0x44a26c FDIV	Z26.D, P0/M, Z26.D, Z31.D

0x44a270 FCMGE	P2.D, P0/Z, Z25.D, #0

0x44a274 FSUB	Z23.D, Z23.D, Z24.D

0x44a278 LD1D	{Z24.D}, P0/Z, [X6, X1,LSL #3]    [3]

0x44a27c FADD	Z24.D, Z31.D, Z24.D

0x44a280 FDIV	Z23.D, P0/M, Z23.D, Z24.D

0x44a284 LD1D	{Z24.D}, P0/Z, [X10, X25,LSL #3]    [16]

0x44a288 FADD	Z21.D, Z21.D, Z26.D

0x44a28c LD1D	{Z26.D}, P0/Z, [X5, X25,LSL #3]    [18]

0x44a290 ADD	X25, X25, X0

0x44a294 CMP	X14, X25

0x44a298 FSUB	Z24.D, Z24.D, Z26.D

0x44a29c FDIV	Z24.D, P0/M, Z24.D, Z17.D

0x44a2a0 FMUL	Z26.D, Z23.D, Z23.D

0x44a2a4 FMUL	Z21.D, Z21.D, Z23.D

0x44a2a8 FMUL	Z22.D, Z22.D, Z26.D

0x44a2ac FMUL	Z28.D, Z24.D, Z24.D

0x44a2b0 FMLA	Z22.D, P0/M, Z28.D, Z29.D

0x44a2b4 FMAD	Z21.D, P0/M, Z24.D, Z22.D

0x44a2b8 FADD	Z22.D, Z26.D, Z28.D

0x44a2bc FCMGE	P1.D, P0/Z, Z22.D, Z3.D

0x44a2c0 SEL	Z22.D, P1, Z22.D, Z3.D

0x44a2c4 FDIV	Z21.D, P0/M, Z21.D, Z22.D

0x44a2c8 MOVPRFX	Z22, Z23

0x44a2cc FABS	Z22.D, P0/M, Z23.D

0x44a2d0 FCMGE	P3.D, P0/Z, Z22.D, Z3.D

0x44a2d4 SEL	Z22.D, P3, Z22.D, Z3.D

0x44a2d8 FCMLT	P3.D, P0/Z, Z23.D, #0

0x44a2dc MOVPRFX	Z23, Z22

0x44a2e0 FNEG	Z23.D, P0/M, Z22.D

0x44a2e4 EOR	P3.B, P0/Z, P3.B, P0.B

0x44a2e8 SEL	Z22.D, P3, Z22.D, Z23.D

0x44a2ec MOVPRFX	Z23, Z24

0x44a2f0 FABS	Z23.D, P0/M, Z24.D

0x44a2f4 FCMLT	P3.D, P0/Z, Z22.D, #0

0x44a2f8 EOR	P3.B, P0/Z, P3.B, P0.B

0x44a2fc FCMGT	P1.D, P0/Z, Z21.D, #0

0x44a300 EOR	P1.B, P0/Z, P1.B, P0.B

0x44a304 BIC	P1.B, P1/Z, P1.B, P2.B

0x44a308 FCMGE	P2.D, P0/Z, Z23.D, Z3.D

0x44a30c SEL	Z23.D, P2, Z23.D, Z3.D

0x44a310 MOVPRFX	Z24, Z23

0x44a314 FNEG	Z24.D, P0/M, Z23.D

0x44a318 SEL	Z23.D, P3, Z23.D, Z24.D

0x44a31c FMUL	Z24.D, Z23.D, Z23.D

0x44a320 FMLA	Z24.D, P0/M, Z22.D, Z22.D

0x44a324 FSQRT	Z24.D, P0/M, Z24.D

0x44a328 FMUL	Z25.D, Z31.D, Z24.D

0x44a32c FMUL	Z24.D, Z16.D, Z24.D

0x44a330 FDIVR	Z22.D, P0/M, Z22.D, Z25.D

0x44a334 FDIVR	Z23.D, P0/M, Z23.D, Z24.D

0x44a338 FABS	Z22.D, P0/M, Z22.D

0x44a33c FABS	Z23.D, P0/M, Z23.D

0x44a340 FCMGE	P2.D, P0/Z, Z22.D, Z23.D

0x44a344 SEL	Z22.D, P2, Z23.D, Z22.D

0x44a348 LD1D	{Z23.D}, P1/Z, [X13, Z4.D,LSL #3]    [11]

0x44a34c FMUL	Z22.D, Z22.D, Z22.D

0x44a350 ADR	Z23.D, [Z23, Z20.D,LSL #3]    [17]

0x44a354 LD1D	{Z23.D}, P1/Z, [V23.D]    [9]

0x44a358 FADD	Z23.D, Z23.D, Z23.D

0x44a35c FMUL	Z22.D, Z22.D, Z23.D

0x44a360 FMUL	Z22.D, Z21.D, Z22.D

0x44a364 FMUL	Z21.D, Z21.D, Z22.D

0x44a368 SEL	Z21.D, P1, Z21.D, Z4.D

0x44a36c ST1D	{Z21.D}, P0, [X30, Z20.D,LSL #3]    [10]

0x44a370 B.NE	44a1c0

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/viscosity_kernel.f90-pp.f90: 56 - 89

--------------------------------------------------------------------------------

56:       DO j=x_min,x_max

57:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

58: # 58 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90"

59:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

60: # 60 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90"

61:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

62: # 62 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90"

63:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

64:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

65: # 65 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90"

66:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

67:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

68: # 68 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90"

69:         pgradx2 = pgradx*pgradx

70:         pgrady2 = pgrady*pgrady

71: # 71 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90"

72:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

73:           /MAX(pgradx2+pgrady2,1.0e-16_8)

74: # 74 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90"

75:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

76:           viscosity(j,k) = 0.0

77:         ELSE

78:           dirx=1.0_8

79:           IF(pgradx.LT.0.0) dirx=-1.0_8

80:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

81:           diry=1.0_8

82:           IF(pgradx.LT.0.0) diry=-1.0_8

83:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

84:           pgrad = SQRT(pgradx**2+pgrady**2)

85:           xgrad = ABS(celldx(j)*pgrad/pgradx)

86:           ygrad = ABS(celldy(k)*pgrad/pgrady)

87:           grad  = MIN(xgrad,ygrad)

88:           grad2 = grad*grad

89: # 89 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90"

Path /

Metric	Value
CQA speedup if no scalar integer	1.01
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.08
Bottlenecks	P6, P7,
Function	__nv_viscosity_kernel_module_viscosity_kernel__F1L50_1_
Source	viscosity_kernel.f90-pp.f90:56-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	39.50
CQA cycles if no scalar integer	39.00
CQA cycles if FP arith vectorized	39.50
CQA cycles if fully vectorized	39.13
Front-end cycles	13.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	4.00
P4 cycles	2.50
P5 cycles	39.50
P6 cycles	39.50
P7 cycles	19.00
P8 cycles	19.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.00 - 5.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	109.00
Nb uops	109.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	5.27
Nb FLOP add-sub	72.00
Nb FLOP mul	64.00
Nb FLOP fma	16.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.77
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	92.00
Vectorization ratio load	94.12
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	95.24
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	78.13
Vector-efficiency ratio all	95.00
Vector-efficiency ratio load	95.59
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	96.43
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	86.72

Metric	Value
CQA speedup if no scalar integer	1.01
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.08
Bottlenecks	P6, P7,
Function	__nv_viscosity_kernel_module_viscosity_kernel__F1L50_1_
Source	viscosity_kernel.f90-pp.f90:56-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	39.50
CQA cycles if no scalar integer	39.00
CQA cycles if FP arith vectorized	39.50
CQA cycles if fully vectorized	39.13
Front-end cycles	13.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	4.00
P4 cycles	2.50
P5 cycles	39.50
P6 cycles	39.50
P7 cycles	19.00
P8 cycles	19.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.00 - 5.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	109.00
Nb uops	109.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	5.27
Nb FLOP add-sub	72.00
Nb FLOP mul	64.00
Nb FLOP fma	16.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.77
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	92.00
Vectorization ratio load	94.12
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	95.24
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	78.13
Vector-efficiency ratio all	95.00
Vector-efficiency ratio load	95.59
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	96.43
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	86.72

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_viscosity_kernel_module_viscosity_kernel__F1L50_1_
Source file and lines	viscosity_kernel.f90-pp.f90:56-89
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/viscosity_kernel.f90-pp.f90:56-89.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 39.50 to 39.12 cycles (1.01x speedup).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU loads are used in vector version.
95% of VPU addition or subtraction instructions are used in vector version.
78% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

88: addition or subtraction (16 inside FMA instructions)
80: multiply (16 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 512 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.38 FP operations per loaded or stored byte.

General properties

nb instructions	109
loop length	436
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.75	2.75	4.00	2.50	39.50	39.50	1.00	1.00	8.00	8.00	1.00	0.00	0.00
cycles	0.50	0.50	2.75	2.75	4.00	2.50	39.50	39.50	19.00	19.00	8.00	8.00	1.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-5.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	13.63
Data deps.	2.00
Overall L1	39.50

Vectorization ratios

INT

all	78%
load	94%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	61%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	92%
load	94%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	78%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 39.50 cycles. At this rate:

13% of peak load performance is reached (12.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44a1c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
UBFM X6, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X16, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X23, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1D {Z20.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z21.D}, P0/Z, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z23.D}, P0/Z, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X7, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1D {Z24.D}, P0/Z, [X23, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z26.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z27.D}, P0/Z, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X7, X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X6, X29, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1D {Z28.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z25.D, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z29.D}, P0/Z, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z31.D}, P0/Z, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z22.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z20.D, Z20.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z22.D, Z22.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z25.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z20.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z26.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z30.D, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z26.D, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z20.D, P0/M, Z20.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z21.D, P0/M, Z21.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
ADD Z20.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z25.D, Z25.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z29, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z29.D, P0/M, Z29.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FDIV Z29.D, P0/M, Z29.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
ADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMOV X7, D20	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z27.D, Z22.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z22.D, P0/M, Z22.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z26.D, P0/M, Z26.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
LD1D {Z23.D}, P0/Z, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z24.D}, P0/Z, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FDIV Z22.D, P0/M, Z22.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FMAD Z25.D, P0/M, Z16.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FDIV Z26.D, P0/M, Z26.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FCMGE P2.D, P0/Z, Z25.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FSUB Z23.D, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z24.D}, P0/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z24.D, Z31.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z23.D, P0/M, Z23.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
LD1D {Z24.D}, P0/Z, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z21.D, Z21.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X5, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X25, X25, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X14, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FSUB Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z24.D, P0/M, Z24.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FMUL Z26.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z22.D, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z28.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMLA Z22.D, P0/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMAD Z21.D, P0/M, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FADD Z22.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMGE P1.D, P0/Z, Z22.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
SEL Z22.D, P1, Z22.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z21.D, P0/M, Z21.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z22, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FABS Z22.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMGE P3.D, P0/Z, Z22.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
SEL Z22.D, P3, Z22.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMLT P3.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
MOVPRFX Z23, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FNEG Z23.D, P0/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
EOR P3.B, P0/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
SEL Z22.D, P3, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z23, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FABS Z23.D, P0/M, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMLT P3.D, P0/Z, Z22.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
EOR P3.B, P0/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
FCMGT P1.D, P0/Z, Z21.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
BIC P1.B, P1/Z, P1.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
FCMGE P2.D, P0/Z, Z23.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
SEL Z23.D, P2, Z23.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FNEG Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SEL Z23.D, P3, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z24.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMLA Z24.D, P0/M, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FSQRT Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	1-0.50
FMUL Z25.D, Z31.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z24.D, Z16.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FDIVR Z22.D, P0/M, Z22.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FDIVR Z23.D, P0/M, Z23.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FABS Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FABS Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMGE P2.D, P0/Z, Z22.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
SEL Z22.D, P2, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z23.D}, P1/Z, [X13, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMUL Z22.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
ADR Z23.D, [Z23, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z23.D}, P1/Z, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
FADD Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z22.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z22.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
SEL Z21.D, P1, Z21.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ST1D {Z21.D}, P0, [X30, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 44a1c0 <__nv_viscosity_kernel_module_viscosity_kernel__F1L50_1_+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_viscosity_kernel_module_viscosity_kernel__F1L50_1_
Source file and lines	viscosity_kernel.f90-pp.f90:56-89
Module	exec

gain
potential
hint
expert

Vectorization

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU loads are used in vector version.
95% of VPU addition or subtraction instructions are used in vector version.
78% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

88: addition or subtraction (16 inside FMA instructions)
80: multiply (16 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 512 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.38 FP operations per loaded or stored byte.

General properties

nb instructions	109
loop length	436
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.75	2.75	4.00	2.50	39.50	39.50	1.00	1.00	8.00	8.00	1.00	0.00	0.00
cycles	0.50	0.50	2.75	2.75	4.00	2.50	39.50	39.50	19.00	19.00	8.00	8.00	1.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-5.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	13.63
Data deps.	2.00
Overall L1	39.50

Vectorization ratios

INT

all	78%
load	94%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	61%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	92%
load	94%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	78%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 39.50 cycles. At this rate:

13% of peak load performance is reached (12.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44a1c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
UBFM X6, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X16, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X23, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1D {Z20.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z21.D}, P0/Z, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z23.D}, P0/Z, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X7, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1D {Z24.D}, P0/Z, [X23, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z26.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z27.D}, P0/Z, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X7, X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X6, X29, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1D {Z28.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z25.D, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z29.D}, P0/Z, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z31.D}, P0/Z, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z22.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z20.D, Z20.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z22.D, Z22.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z25.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z20.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z26.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z30.D, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z26.D, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z20.D, P0/M, Z20.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z21.D, P0/M, Z21.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
ADD Z20.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z25.D, Z25.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z29, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z29.D, P0/M, Z29.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FDIV Z29.D, P0/M, Z29.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
ADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FSUB Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMOV X7, D20	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z27.D, Z22.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z22.D, P0/M, Z22.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z26.D, P0/M, Z26.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
LD1D {Z23.D}, P0/Z, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z24.D}, P0/Z, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FDIV Z22.D, P0/M, Z22.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FMAD Z25.D, P0/M, Z16.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FDIV Z26.D, P0/M, Z26.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FCMGE P2.D, P0/Z, Z25.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FSUB Z23.D, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z24.D}, P0/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z24.D, Z31.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z23.D, P0/M, Z23.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
LD1D {Z24.D}, P0/Z, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z21.D, Z21.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X5, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X25, X25, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X14, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FSUB Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z24.D, P0/M, Z24.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FMUL Z26.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z22.D, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z28.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMLA Z22.D, P0/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMAD Z21.D, P0/M, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FADD Z22.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMGE P1.D, P0/Z, Z22.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
SEL Z22.D, P1, Z22.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z21.D, P0/M, Z21.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z22, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FABS Z22.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMGE P3.D, P0/Z, Z22.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
SEL Z22.D, P3, Z22.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMLT P3.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
MOVPRFX Z23, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FNEG Z23.D, P0/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
EOR P3.B, P0/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
SEL Z22.D, P3, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z23, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FABS Z23.D, P0/M, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMLT P3.D, P0/Z, Z22.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
EOR P3.B, P0/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
FCMGT P1.D, P0/Z, Z21.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
BIC P1.B, P1/Z, P1.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
FCMGE P2.D, P0/Z, Z23.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
SEL Z23.D, P2, Z23.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FNEG Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SEL Z23.D, P3, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z24.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMLA Z24.D, P0/M, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FSQRT Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	1-0.50
FMUL Z25.D, Z31.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z24.D, Z16.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FDIVR Z22.D, P0/M, Z22.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FDIVR Z23.D, P0/M, Z23.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FABS Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FABS Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMGE P2.D, P0/Z, Z22.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
SEL Z22.D, P2, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z23.D}, P1/Z, [X13, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMUL Z22.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
ADR Z23.D, [Z23, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z23.D}, P1/Z, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
FADD Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z22.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z22.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
SEL Z21.D, P1, Z21.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ST1D {Z21.D}, P0, [X30, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 44a1c0 <__nv_viscosity_kernel_module_viscosity_kernel__F1L50_1_+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code