OV - exec - Function __nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1

	Function: __nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_	Module: exec	Source: generate_chunk_kernel.f90-pp.f90:85-172 [...]	Coverage: 0.03%

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/generate_chunk_kernel.f90-pp.f90: 85 - 172

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85: # 85 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

86:     !$OMP PARALLEL SHARED(x_cent,y_cent)

87:     !$OMP DO

88:     DO k=y_min-2,y_max+2

89:     !$OMP SIMD

90:       DO j=x_min-2,x_max+2

91:         energy0(j,k)=state_energy(1)

92:       ENDDO

93:     ENDDO

94:     !$OMP END DO

95:     !$OMP DO

96:     DO k=y_min-2,y_max+2

97:     !$OMP SIMD

98:       DO j=x_min-2,x_max+2

99:         density0(j,k)=state_density(1)

100:       ENDDO

101:     ENDDO

102:     !$OMP END DO

103:     !$OMP DO

104:     DO k=y_min-2,y_max+2

105:     !$OMP SIMD

106:       DO j=x_min-2,x_max+2

107:         xvel0(j,k)=state_xvel(1)

108:       ENDDO

109:     ENDDO

110:     !$OMP END DO

111:     !$OMP DO

112:     DO k=y_min-2,y_max+2

113:     !$OMP SIMD

114:       DO j=x_min-2,x_max+2

115:         yvel0(j,k)=state_yvel(1)

116:       ENDDO

117:     ENDDO

118:     !$OMP END DO

119: # 119 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

120:     DO state=2,number_of_states

121: # 121 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

122:       ! Could the velocity setting be thread unsafe?

123:       x_cent=state_xmin(state)

124:       y_cent=state_ymin(state)

125: # 125 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

126:       !$OMP DO PRIVATE(radius,jt,kt)

127:       DO k=y_min-2,y_max+2

128:       !$OMP SIMD

129:         DO j=x_min-2,x_max+2

130:           IF(state_geometry(state).EQ.g_rect ) THEN

131:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

[...]

142:             ENDIF

143:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

144:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

[...]

154:             ENDIF

155:           ELSEIF(state_geometry(state).EQ.g_point) THEN

[...]

166:           ENDIF

167:         ENDDO

168:       ENDDO

169:     !$OMP END DO

170: # 170 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

171:     ENDDO

172: # 172 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

0x423b60 SUB	SP, SP, #160

0x423b64 STP	X30, X25, [SP, #96]

0x423b68 STP	X24, X23, [SP, #112]

0x423b6c STP	X22, X21, [SP, #128]

0x423b70 STP	X20, X19, [SP, #144]

0x423b74 LDP	X8, X9, [X2]

0x423b78 LDR	W20, [X0]

0x423b7c ORR	X0, XZR, XZR

0x423b80 ORR	X19, XZR, X2

0x423b84 MOVZ	W21, #1

0x423b88 ADD	X3, SP, #92

0x423b8c ADD	X4, SP, #88

0x423b90 STR	WZR, [SP, #92]

0x423b94 ADD	X5, SP, #84

0x423b98 ADD	X6, SP, #80

0x423b9c MOVZ	W2, #34

0x423ba0 STR	W21, [SP, #80]

0x423ba4 LDR	W8, [X8]

0x423ba8 LDR	W9, [X9]

0x423bac ORR	W1, WZR, W20

0x423bb0 MOVZ	W7, #1

0x423bb4 ADD	W22, W9, #2

0x423bb8 SUB	W8, W8, #2

0x423bbc STR	W21, [SP]

0x423bc0 STP	W22, W8, [SP, #84]

0x423bc4 BL	404c10

0x423bc8 LDRSW	X8, [SP, #88]

0x423bcc CMP	W8, W22

0x423bd0 B.GT	423cd4

0x423bd4 LDR	W9, [SP, #84]

0x423bd8 SUBS	W9, W9, W8

0x423bdc B.MI	423cd4

0x423be0 LDP	X11, X10, [X19, #16]

0x423be4 PTRUE	P0.D, ALL

0x423be8 ADD	W9, W9, #1

0x423bec LDR	W10, [X10]

0x423bf0 LDR	W11, [X11]

0x423bf4 SUB	W13, W10, W11

0x423bf8 SUB	W12, W11, #2

0x423bfc SBFM	X11, X12, #0, #31

0x423c00 ADD	W10, W13, #5

0x423c04 ADD	W12, W13, #4

0x423c08 CNTW	X13, ALL

0x423c0c ADD	X12, X12, #1

0x423c10 B	423c2c

0x423c14 HINT	#0

0x423c18 HINT	#0

0x423c1c HINT	#0

(535) 0x423c20 ADD	X8, X8, #1

(535) 0x423c24 SUBS	W9, W9, #1

(535) 0x423c28 B.LE	423cd4

(535) 0x423c2c CMP	W10, #1

(535) 0x423c30 B.LT	423c20

(535) 0x423c34 LDP	X15, X14, [X19, #96]

(535) 0x423c38 ORR	X17, XZR, X11

(535) 0x423c3c ORR	W18, WZR, W10

(535) 0x423c40 LDR	D0, [X14]

(535) 0x423c44 LDR	X14, [X19, #56]

(535) 0x423c48 LDR	X15, [X15]

(535) 0x423c4c CMP	X12, X13

(535) 0x423c50 LDR	X16, [X14]

(535) 0x423c54 LDR	X14, [X19, #32]

(535) 0x423c58 B.CC	423ca0

(535) 0x423c5c UDIV	X17, X12, X13

(535) 0x423c60 MADD	X3, X16, X8, X11

(535) 0x423c64 ORR	X1, XZR, XZR

(535) 0x423c68 DUP	Z1.D, Z0.D[0]

(535) 0x423c6c SUB	X3, X3, X15

(535) 0x423c70 ADD	X3, X14, X3,LSL #3

(535) 0x423c74 ADDVL	X4, X3, #1

(535) 0x423c78 MADD	X2, X17, X13, XZR

(535) 0x423c7c SUB	X0, X12, X2

(535) 0x423c80 ADD	X17, X2, X11

(535) 0x423c84 SUB	W18, W10, W2

  (537) 0x423c88 ST1D	{Z1.D}, P0, [X3, X1,LSL #3]

  (537) 0x423c8c ST1D	{Z1.D}, P0, [X4, X1,LSL #3]

  (537) 0x423c90 ADD	X1, X1, X13

  (537) 0x423c94 CMP	X2, X1

  (537) 0x423c98 B.NE	423c88

(535) 0x423c9c CBZ	X0, 423c20

(535) 0x423ca0 MADD	X16, X16, X8, X17

(535) 0x423ca4 SUB	X15, X16, X15

(535) 0x423ca8 ADD	X14, X14, X15,LSL #3

(535) 0x423cac ADD	W15, W18, #1

(535) 0x423cb0 HINT	#0

(535) 0x423cb4 HINT	#0

(535) 0x423cb8 HINT	#0

(535) 0x423cbc HINT	#0

  (536) 0x423cc0 SUB	W15, W15, #1

  (536) 0x423cc4 STR	D0, [X14], #8

  (536) 0x423cc8 CMP	W15, #1

  (536) 0x423ccc B.HI	423cc0

(535) 0x423cd0 B	423c20

0x423cd4 ORR	X0, XZR, XZR

0x423cd8 ORR	W1, WZR, W20

0x423cdc BL	404d30

0x423ce0 ORR	X0, XZR, XZR

0x423ce4 ORR	W1, WZR, W20

0x423ce8 BL	404900

0x423cec LDP	X8, X9, [X19]

0x423cf0 ORR	X0, XZR, XZR

0x423cf4 ORR	W1, WZR, W20

0x423cf8 ADD	X3, SP, #76

0x423cfc ADD	X4, SP, #72

0x423d00 ADD	X5, SP, #68

0x423d04 STR	WZR, [SP, #76]

0x423d08 LDR	W8, [X8]

0x423d0c LDR	W9, [X9]

0x423d10 ADD	X6, SP, #64

0x423d14 MOVZ	W2, #34

0x423d18 MOVZ	W7, #1

0x423d1c STR	W21, [SP, #64]

0x423d20 STR	W21, [SP]

0x423d24 SUB	W8, W8, #2

0x423d28 ADD	W22, W9, #2

0x423d2c STP	W22, W8, [SP, #68]

0x423d30 BL	404c10

0x423d34 LDRSW	X8, [SP, #72]

0x423d38 CMP	W8, W22

0x423d3c B.GT	423e34

0x423d40 LDR	W9, [SP, #68]

0x423d44 SUBS	W9, W9, W8

0x423d48 B.MI	423e34

0x423d4c LDP	X11, X10, [X19, #16]

0x423d50 PTRUE	P0.D, ALL

0x423d54 ADD	W9, W9, #1

0x423d58 LDR	W10, [X10]

0x423d5c LDR	W11, [X11]

0x423d60 SUB	W13, W10, W11

0x423d64 SUB	W12, W11, #2

0x423d68 SBFM	X11, X12, #0, #31

0x423d6c ADD	W10, W13, #5

0x423d70 ADD	W12, W13, #4

0x423d74 CNTW	X13, ALL

0x423d78 ADD	X12, X12, #1

0x423d7c B	423d8c

(532) 0x423d80 ADD	X8, X8, #1

(532) 0x423d84 SUBS	W9, W9, #1

(532) 0x423d88 B.LE	423e34

(532) 0x423d8c CMP	W10, #1

(532) 0x423d90 B.LT	423d80

(532) 0x423d94 LDP	X14, X15, [X19, #120]

(532) 0x423d98 LDR	X16, [X19, #96]

(532) 0x423d9c ORR	X18, XZR, X11

(532) 0x423da0 ORR	W17, WZR, W10

(532) 0x423da4 LDR	D0, [X15]

(532) 0x423da8 LDR	X15, [X19, #56]

(532) 0x423dac LDR	X16, [X16]

(532) 0x423db0 CMP	X12, X13

(532) 0x423db4 LDR	X15, [X15]

(532) 0x423db8 B.CC	423e00

(532) 0x423dbc UDIV	X17, X12, X13

(532) 0x423dc0 MADD	X3, X15, X8, X11

(532) 0x423dc4 ORR	X1, XZR, XZR

(532) 0x423dc8 DUP	Z1.D, Z0.D[0]

(532) 0x423dcc SUB	X3, X3, X16

(532) 0x423dd0 ADD	X3, X14, X3,LSL #3

(532) 0x423dd4 ADDVL	X4, X3, #1

(532) 0x423dd8 MADD	X2, X17, X13, XZR

(532) 0x423ddc SUB	X0, X12, X2

(532) 0x423de0 ADD	X18, X2, X11

(532) 0x423de4 SUB	W17, W10, W2

  (534) 0x423de8 ST1D	{Z1.D}, P0, [X3, X1,LSL #3]

  (534) 0x423dec ST1D	{Z1.D}, P0, [X4, X1,LSL #3]

  (534) 0x423df0 ADD	X1, X1, X13

  (534) 0x423df4 CMP	X2, X1

  (534) 0x423df8 B.NE	423de8

(532) 0x423dfc CBZ	X0, 423d80

(532) 0x423e00 MADD	X15, X15, X8, X18

(532) 0x423e04 SUB	X15, X15, X16

(532) 0x423e08 ADD	X14, X14, X15,LSL #3

(532) 0x423e0c ADD	W15, W17, #1

(532) 0x423e10 HINT	#0

(532) 0x423e14 HINT	#0

(532) 0x423e18 HINT	#0

(532) 0x423e1c HINT	#0

  (533) 0x423e20 SUB	W15, W15, #1

  (533) 0x423e24 STR	D0, [X14], #8

  (533) 0x423e28 CMP	W15, #1

  (533) 0x423e2c B.HI	423e20

(532) 0x423e30 B	423d80

0x423e34 ORR	X0, XZR, XZR

0x423e38 ORR	W1, WZR, W20

0x423e3c BL	404d30

0x423e40 ORR	X0, XZR, XZR

0x423e44 ORR	W1, WZR, W20

0x423e48 BL	404900

0x423e4c LDP	X8, X9, [X19]

0x423e50 ORR	X0, XZR, XZR

0x423e54 ORR	W1, WZR, W20

0x423e58 MOVZ	W21, #1

0x423e5c ADD	X3, SP, #60

0x423e60 ADD	X4, SP, #56

0x423e64 STR	WZR, [SP, #60]

0x423e68 LDR	W8, [X8]

0x423e6c LDR	W9, [X9]

0x423e70 ADD	X5, SP, #52

0x423e74 ADD	X6, SP, #48

0x423e78 MOVZ	W2, #34

0x423e7c MOVZ	W7, #1

0x423e80 STR	W21, [SP, #48]

0x423e84 STR	W21, [SP]

0x423e88 ADD	W22, W9, #2

0x423e8c SUB	W8, W8, #2

0x423e90 STP	W22, W8, [SP, #52]

0x423e94 BL	404c10

0x423e98 LDRSW	X8, [SP, #56]

0x423e9c CMP	W8, W22

0x423ea0 B.GT	423f94

0x423ea4 LDR	W9, [SP, #52]

0x423ea8 SUBS	W9, W9, W8

0x423eac B.MI	423f94

0x423eb0 LDP	X11, X10, [X19, #16]

0x423eb4 PTRUE	P0.D, ALL

0x423eb8 ADD	W9, W9, #1

0x423ebc LDR	W10, [X10]

0x423ec0 LDR	W11, [X11]

0x423ec4 SUB	W13, W10, W11

0x423ec8 SUB	W12, W11, #2

0x423ecc SBFM	X11, X12, #0, #31

0x423ed0 ADD	W10, W13, #5

0x423ed4 ADD	W12, W13, #4

0x423ed8 CNTW	X13, ALL

0x423edc ADD	X12, X12, #1

0x423ee0 B	423ef0

(529) 0x423ee4 ADD	X8, X8, #1

(529) 0x423ee8 SUBS	W9, W9, #1

(529) 0x423eec B.LE	423f94

(529) 0x423ef0 CMP	W10, #1

(529) 0x423ef4 B.LT	423ee4

(529) 0x423ef8 LDP	X15, X14, [X19, #184]

(529) 0x423efc ORR	X17, XZR, X11

(529) 0x423f00 ORR	W18, WZR, W10

(529) 0x423f04 LDR	D0, [X14]

(529) 0x423f08 LDR	X14, [X19, #152]

(529) 0x423f0c LDR	X15, [X15]

(529) 0x423f10 CMP	X12, X13

(529) 0x423f14 LDR	X16, [X14]

(529) 0x423f18 LDR	X14, [X19, #136]

(529) 0x423f1c B.CC	423f64

(529) 0x423f20 UDIV	X17, X12, X13

(529) 0x423f24 MADD	X3, X16, X8, X11

(529) 0x423f28 ORR	X1, XZR, XZR

(529) 0x423f2c DUP	Z1.D, Z0.D[0]

(529) 0x423f30 SUB	X3, X3, X15

(529) 0x423f34 ADD	X3, X14, X3,LSL #3

(529) 0x423f38 ADDVL	X4, X3, #1

(529) 0x423f3c MADD	X2, X17, X13, XZR

(529) 0x423f40 SUB	X0, X12, X2

(529) 0x423f44 ADD	X17, X2, X11

(529) 0x423f48 SUB	W18, W10, W2

  (531) 0x423f4c ST1D	{Z1.D}, P0, [X3, X1,LSL #3]

  (531) 0x423f50 ST1D	{Z1.D}, P0, [X4, X1,LSL #3]

  (531) 0x423f54 ADD	X1, X1, X13

  (531) 0x423f58 CMP	X2, X1

  (531) 0x423f5c B.NE	423f4c

(529) 0x423f60 CBZ	X0, 423ee4

(529) 0x423f64 MADD	X16, X16, X8, X17

(529) 0x423f68 SUB	X15, X16, X15

(529) 0x423f6c ADD	X14, X14, X15,LSL #3

(529) 0x423f70 ADD	W15, W18, #1

(529) 0x423f74 HINT	#0

(529) 0x423f78 HINT	#0

(529) 0x423f7c HINT	#0

  (530) 0x423f80 SUB	W15, W15, #1

  (530) 0x423f84 STR	D0, [X14], #8

  (530) 0x423f88 CMP	W15, #1

  (530) 0x423f8c B.HI	423f80

(529) 0x423f90 B	423ee4

0x423f94 ORR	X0, XZR, XZR

0x423f98 ORR	W1, WZR, W20

0x423f9c BL	404d30

0x423fa0 ORR	X0, XZR, XZR

0x423fa4 ORR	W1, WZR, W20

0x423fa8 BL	404900

0x423fac LDP	X8, X9, [X19]

0x423fb0 ORR	X0, XZR, XZR

0x423fb4 ORR	W1, WZR, W20

0x423fb8 ADD	X3, SP, #44

0x423fbc ADD	X4, SP, #40

0x423fc0 ADD	X5, SP, #36

0x423fc4 STR	WZR, [SP, #44]

0x423fc8 LDR	W8, [X8]

0x423fcc LDR	W9, [X9]

0x423fd0 ADD	X6, SP, #32

0x423fd4 MOVZ	W2, #34

0x423fd8 MOVZ	W7, #1

0x423fdc STR	W21, [SP, #32]

0x423fe0 STR	W21, [SP]

0x423fe4 SUB	W8, W8, #2

0x423fe8 ADD	W22, W9, #2

0x423fec STP	W22, W8, [SP, #36]

0x423ff0 BL	404c10

0x423ff4 LDRSW	X8, [SP, #40]

0x423ff8 CMP	W8, W22

0x423ffc B.GT	4240f4

0x424000 LDR	W9, [SP, #36]

0x424004 SUBS	W9, W9, W8

0x424008 B.MI	4240f4

0x42400c LDP	X11, X10, [X19, #16]

0x424010 PTRUE	P0.D, ALL

0x424014 ADD	W9, W9, #1

0x424018 LDR	W10, [X10]

0x42401c LDR	W11, [X11]

0x424020 SUB	W13, W10, W11

0x424024 SUB	W12, W11, #2

0x424028 SBFM	X11, X12, #0, #31

0x42402c ADD	W10, W13, #5

0x424030 ADD	W12, W13, #4

0x424034 CNTW	X13, ALL

0x424038 ADD	X12, X12, #1

0x42403c B	42404c

(526) 0x424040 ADD	X8, X8, #1

(526) 0x424044 SUBS	W9, W9, #1

(526) 0x424048 B.LE	4240f4

(526) 0x42404c CMP	W10, #1

(526) 0x424050 B.LT	424040

(526) 0x424054 LDP	X14, X15, [X19, #200]

(526) 0x424058 LDR	X16, [X19, #184]

(526) 0x42405c ORR	X18, XZR, X11

(526) 0x424060 ORR	W17, WZR, W10

(526) 0x424064 LDR	D0, [X15]

(526) 0x424068 LDR	X15, [X19, #152]

(526) 0x42406c LDR	X16, [X16]

(526) 0x424070 CMP	X12, X13

(526) 0x424074 LDR	X15, [X15]

(526) 0x424078 B.CC	4240c0

(526) 0x42407c UDIV	X17, X12, X13

(526) 0x424080 MADD	X3, X15, X8, X11

(526) 0x424084 ORR	X1, XZR, XZR

(526) 0x424088 DUP	Z1.D, Z0.D[0]

(526) 0x42408c SUB	X3, X3, X16

(526) 0x424090 ADD	X3, X14, X3,LSL #3

(526) 0x424094 ADDVL	X4, X3, #1

(526) 0x424098 MADD	X2, X17, X13, XZR

(526) 0x42409c SUB	X0, X12, X2

(526) 0x4240a0 ADD	X18, X2, X11

(526) 0x4240a4 SUB	W17, W10, W2

  (528) 0x4240a8 ST1D	{Z1.D}, P0, [X3, X1,LSL #3]

  (528) 0x4240ac ST1D	{Z1.D}, P0, [X4, X1,LSL #3]

  (528) 0x4240b0 ADD	X1, X1, X13

  (528) 0x4240b4 CMP	X2, X1

  (528) 0x4240b8 B.NE	4240a8

(526) 0x4240bc CBZ	X0, 424040

(526) 0x4240c0 MADD	X15, X15, X8, X18

(526) 0x4240c4 SUB	X15, X15, X16

(526) 0x4240c8 ADD	X14, X14, X15,LSL #3

(526) 0x4240cc ADD	W15, W17, #1

(526) 0x4240d0 HINT	#0

(526) 0x4240d4 HINT	#0

(526) 0x4240d8 HINT	#0

(526) 0x4240dc HINT	#0

  (527) 0x4240e0 SUB	W15, W15, #1

  (527) 0x4240e4 STR	D0, [X14], #8

  (527) 0x4240e8 CMP	W15, #1

  (527) 0x4240ec B.HI	4240e0

(526) 0x4240f0 B	424040

0x4240f4 ORR	X0, XZR, XZR

0x4240f8 ORR	W1, WZR, W20

0x4240fc BL	404d30

0x424100 ORR	X0, XZR, XZR

0x424104 ORR	W1, WZR, W20

0x424108 BL	404900

0x42410c LDR	X8, [X19, #216]

0x424110 LDR	W8, [X8]

0x424114 CMP	W8, #2

0x424118 B.GE	424134

      (522) 0x42411c LDP	X20, X19, [SP, #144]

      (522) 0x424120 LDP	X22, X21, [SP, #128]

      (522) 0x424124 LDP	X24, X23, [SP, #112]

      (522) 0x424128 LDP	X30, X25, [SP, #96]

      (522) 0x42412c ADD	SP, SP, #160

      (522) 0x424130 RET

      (522) 0x424134 ADD	X21, X8, #1

      (522) 0x424138 MOVZ	W22, #2

      (522) 0x42413c MOVZ	W23, #1

      (522) 0x424140 B	424168

      (522) 0x424144 ORR	X0, XZR, XZR

      (522) 0x424148 ORR	W1, WZR, W20

      (522) 0x42414c BL	404d30

      (522) 0x424150 ORR	X0, XZR, XZR

      (522) 0x424154 ORR	W1, WZR, W20

      (522) 0x424158 BL	404900

      (522) 0x42415c ADD	X22, X22, #1

      (522) 0x424160 CMP	X22, X21

      (522) 0x424164 B.EQ	42411c

      (522) 0x424168 LDP	X8, X9, [X19, #232]

      (522) 0x42416c UBFM	X24, X22, #61, #60

      (522) 0x424170 ORR	X0, XZR, XZR

      (522) 0x424174 ORR	W1, WZR, W20

      (522) 0x424178 ADD	X3, SP, #28

      (522) 0x42417c ADD	X4, SP, #24

      (522) 0x424180 STR	WZR, [SP, #28]

      (522) 0x424184 ADD	X5, SP, #20

      (522) 0x424188 ADD	X6, SP, #16

      (522) 0x42418c MOVZ	W2, #34

      (522) 0x424190 STR	W23, [SP, #16]

      (522) 0x424194 MOVZ	W7, #1

      (522) 0x424198 ADD	X8, X8, X24

      (522) 0x42419c LDUR	D0, [X8, #504]

      (522) 0x4241a0 STR	D0, [X9]

      (522) 0x4241a4 LDP	X8, X9, [X19, #248]

      (522) 0x4241a8 ADD	X8, X8, X24

      (522) 0x4241ac LDUR	D0, [X8, #504]

      (522) 0x4241b0 STR	D0, [X9]

      (522) 0x4241b4 LDP	X8, X9, [X19]

      (522) 0x4241b8 LDR	W8, [X8]

      (522) 0x4241bc LDR	W9, [X9]

      (522) 0x4241c0 STR	W23, [SP]

      (522) 0x4241c4 SUB	W8, W8, #2

      (522) 0x4241c8 ADD	W25, W9, #2

      (522) 0x4241cc STP	W25, W8, [SP, #20]

      (522) 0x4241d0 BL	404c10

      (522) 0x4241d4 LDRSW	X8, [SP, #24]

      (522) 0x4241d8 CMP	W8, W25

      (522) 0x4241dc B.GT	424144

      (522) 0x4241e0 LDR	W9, [SP, #20]

      (522) 0x4241e4 SUBS	W9, W9, W8

      (522) 0x4241e8 B.MI	424144

    (523) 0x4241ec LDP	X11, X10, [X19, #16]

    (523) 0x4241f0 ADD	W9, W9, #1

    (523) 0x4241f4 LDR	W10, [X10]

    (523) 0x4241f8 LDR	W11, [X11]

    (523) 0x4241fc SUB	W13, W11, #2

    (523) 0x424200 SUB	W12, W10, W11

    (523) 0x424204 SBFM	X11, X13, #0, #31

    (523) 0x424208 SBFM	X13, X13, #61, #31

    (523) 0x42420c ADD	W10, W12, #5

    (523) 0x424210 ADD	W12, W12, #6

    (523) 0x424214 ADD	X13, X13, #8

    (523) 0x424218 B	424230

0x42421c HINT	#0

    (523) 0x424220 ADD	X14, X8, #1

    (523) 0x424224 ORR	X8, XZR, X14

    (523) 0x424228 SUBS	W9, W9, #1

    (523) 0x42422c B.LE	424144

    (523) 0x424230 CMP	W10, #0

    (523) 0x424234 B.LE	424220

  (525) 0x424238 LDP	X14, X16, [X19, #264]

  (525) 0x42423c ORR	X17, XZR, X13

  (525) 0x424240 ORR	W18, WZR, W12

  (525) 0x424244 LDR	W16, [X16]

  (525) 0x424248 ADD	X14, X14, X22,LSL #2

  (525) 0x42424c ORR	X0, XZR, X11

  (525) 0x424250 LDUR	W15, [X14, #508]

  (525) 0x424254 ADD	X14, X8, #1

  (525) 0x424258 B	424314

  (525) 0x42425c LDP	X3, X2, [X19, #96]

  (525) 0x424260 LDR	X1, [X19, #56]

  (525) 0x424264 LDP	X6, X5, [X19, #120]

  (525) 0x424268 ADD	X2, X2, X24

  (525) 0x42426c LDR	X3, [X3]

  (525) 0x424270 LDR	X1, [X1]

  (525) 0x424274 LDR	X4, [X19, #32]

  (525) 0x424278 ADD	X5, X5, X24

  (525) 0x42427c LDR	X7, [X19, #152]

  (525) 0x424280 LDUR	D0, [X2, #504]

  (525) 0x424284 LDUR	D1, [X5, #504]

  (525) 0x424288 LDP	X5, X2, [X19, #184]

  (525) 0x42428c SUB	X3, XZR, X3

  (525) 0x424290 MADD	X1, X1, X8, X3

  (525) 0x424294 ADD	X2, X2, X24

  (525) 0x424298 LDR	X5, [X5]

  (525) 0x42429c ADD	X1, X0, X1

  (525) 0x4242a0 SUB	X2, X2, #8

  (525) 0x4242a4 STR	D0, [X4, X1,LSL #3]

  (525) 0x4242a8 LD1R	{V0.2D}, [X2]

  (525) 0x4242ac SUB	X2, XZR, X5

  (525) 0x4242b0 LDP	X4, X3, [X19, #200]

  (525) 0x4242b4 STR	D1, [X6, X1,LSL #3]

  (525) 0x4242b8 LDR	X1, [X7]

  (525) 0x4242bc ADD	X3, X3, X24

  (525) 0x4242c0 MADD	X5, X1, X8, X2

  (525) 0x4242c4 MADD	X1, X1, X14, X2

  (525) 0x4242c8 SUB	X3, X3, #8

  (525) 0x4242cc ADD	X5, X0, X5

  (525) 0x4242d0 ADD	X1, X0, X1

  (525) 0x4242d4 LD1R	{V1.2D}, [X3]

  (525) 0x4242d8 LDR	X3, [X19, #136]

  (525) 0x4242dc UBFM	X5, X5, #61, #60

  (525) 0x4242e0 UBFM	X1, X1, #61, #60

  (525) 0x4242e4 STR	Q0, [X3, X5]

  (525) 0x4242e8 STR	Q0, [X3, X1]

  (525) 0x4242ec STR	Q1, [X4, X5]

  (525) 0x4242f0 STR	Q1, [X4, X1]

  (525) 0x4242f4 HINT	#0

  (525) 0x4242f8 HINT	#0

  (525) 0x4242fc HINT	#0

  (525) 0x424300 SUB	W18, W18, #1

  (525) 0x424304 ADD	X0, X0, #1

  (525) 0x424308 ADD	X17, X17, #8

  (525) 0x42430c CMP	W18, #1

  (525) 0x424310 B.LE	424224

  (525) 0x424314 CMP	W15, W16

  (525) 0x424318 B.NE	4243a0

  (525) 0x42431c LDP	X2, X1, [X19, #280]

  (525) 0x424320 LDR	X1, [X1]

  (525) 0x424324 SUB	X1, X2, X1,LSL #3

  (525) 0x424328 LDR	X2, [X19, #232]

  (525) 0x42432c LDR	D0, [X1, X17]

  (525) 0x424330 ADD	X2, X2, X22,LSL #3

  (525) 0x424334 LDUR	D1, [X2, #504]

  (525) 0x424338 FCMP	D0, D1

  (525) 0x42433c B.LT	424300

  (525) 0x424340 ADD	X1, X1, X17

  (525) 0x424344 LDUR	D0, [X1, #504]

  (525) 0x424348 LDR	X1, [X19, #296]

  (525) 0x42434c ADD	X1, X1, X22,LSL #3

  (525) 0x424350 LDUR	D1, [X1, #504]

  (525) 0x424354 FCMP	D0, D1

  (525) 0x424358 B.PL	424300

  (525) 0x42435c LDP	X1, X2, [X19, #304]

  (525) 0x424360 LDR	X2, [X2]

  (525) 0x424364 SUB	X2, X8, X2

  (525) 0x424368 ADD	X3, X1, X2,LSL #3

  (525) 0x42436c LDR	D0, [X3, #8]

  (525) 0x424370 LDR	X3, [X19, #248]

  (525) 0x424374 ADD	X3, X3, X22,LSL #3

  (525) 0x424378 LDUR	D1, [X3, #504]

  (525) 0x42437c FCMP	D0, D1

  (525) 0x424380 B.LT	424300

  (525) 0x424384 LDR	D0, [X1, X2,LSL #3]

  (525) 0x424388 LDR	X1, [X19, #320]

  (525) 0x42438c ADD	X1, X1, X22,LSL #3

  (525) 0x424390 LDUR	D1, [X1, #504]

  (525) 0x424394 FCMP	D0, D1

  (525) 0x424398 B.MI	42425c

  (525) 0x42439c B	424300

  (525) 0x4243a0 LDR	X1, [X19, #328]

  (525) 0x4243a4 LDR	W1, [X1]

  (525) 0x4243a8 CMP	W15, W1

  (525) 0x4243ac B.NE	424420

  (525) 0x4243b0 LDR	X1, [X19, #312]

  (525) 0x4243b4 LDP	X3, X2, [X19, #336]

  (525) 0x4243b8 LDR	X1, [X1]

  (525) 0x4243bc SUB	X1, X8, X1

  (525) 0x4243c0 LDR	D0, [X2, X1,LSL #3]

  (525) 0x4243c4 LDR	X1, [X19, #256]

  (525) 0x4243c8 LDR	D1, [X1]

  (525) 0x4243cc LDR	X1, [X19, #288]

  (525) 0x4243d0 LDR	X1, [X1]

  (525) 0x4243d4 FSUB	D0, D0, S1

  (525) 0x4243d8 SUB	X1, X3, X1,LSL #3

  (525) 0x4243dc LDR	D1, [X1, X0,LSL #3]

  (525) 0x4243e0 LDR	X1, [X19, #240]

  (525) 0x4243e4 LDR	D2, [X1]

  (525) 0x4243e8 LDR	X1, [X19, #352]

  (525) 0x4243ec ADD	X1, X1, X22,LSL #3

  (525) 0x4243f0 FSUB	D1, D1, S2

  (525) 0x4243f4 FMUL	D1, D1, D1

  (525) 0x4243f8 FMADD	D0, D0, D0, D1

  (525) 0x4243fc LDUR	D1, [X1, #504]

  (525) 0x424400 FSQRT	D0, D0

  (525) 0x424404 FCMP	D0, D1

  (525) 0x424408 B.LS	42425c

  (525) 0x42440c B	424300

0x424410 HINT	#0

0x424414 HINT	#0

0x424418 HINT	#0

0x42441c HINT	#0

(524) 0x424420 LDR	X1, [X19, #360]

(524) 0x424424 LDR	W1, [X1]

(524) 0x424428 CMP	W15, W1

(524) 0x42442c B.NE	424300

(524) 0x424430 LDP	X2, X1, [X19, #280]

(524) 0x424434 LDR	X1, [X1]

(524) 0x424438 SUB	X1, X2, X1,LSL #3

(524) 0x42443c LDR	D0, [X1, X0,LSL #3]

(524) 0x424440 LDR	X1, [X19, #240]

(524) 0x424444 LDR	D1, [X1]

(524) 0x424448 FCMP	D0, D1

(524) 0x42444c B.NE	424300

(524) 0x424450 LDP	X2, X1, [X19, #304]

(524) 0x424454 LDR	X1, [X1]

(524) 0x424458 SUB	X1, X8, X1

(524) 0x42445c LDR	D0, [X2, X1,LSL #3]

(524) 0x424460 LDR	X1, [X19, #256]

(524) 0x424464 LDR	D1, [X1]

(524) 0x424468 FCMP	D0, D1

(524) 0x42446c B.NE	424300

(524) 0x424470 B	42425c

0x424474 HINT	#0

0x424478 HINT	#0

0x42447c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	generate_chunk_kernel.f90-pp.f90:85-172
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/generate_chunk_kernel.f90-pp.f90:85-131,142-144,154-155,166-172.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.25 to 4.00 cycles (7.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 29.25 to 18.33 cycles (1.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.25 to 6.00 cycles (4.87x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 240 bytes. The binary function is storing 144 bytes.

General properties

nb instructions	196
loop length	784
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.50	12.50	29.25	29.25	29.25	29.25	0.00	0.00	0.00	0.00	18.33	18.33	18.33	10.00	10.00
cycles	12.50	12.50	29.25	29.25	29.25	29.25	0.00	0.00	0.00	0.00	18.33	18.33	18.33	10.00	10.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.13
Overall L1	29.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.25 cycles. At this rate:

8% of peak load performance is reached (8.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.92 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 423b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X30, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W22, W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 423cd4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 423cd4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423c2c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #76	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #68	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 423e34 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 423e34 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423d8c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 423f94 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 423f94 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423ef0 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4240f4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x594>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4240f4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x594>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42404c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 424134 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	generate_chunk_kernel.f90-pp.f90:85-172
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.25 to 4.00 cycles (7.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.25 to 6.00 cycles (4.87x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 240 bytes. The binary function is storing 144 bytes.

General properties

nb instructions	196
loop length	784
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.50	12.50	29.25	29.25	29.25	29.25	0.00	0.00	0.00	0.00	18.33	18.33	18.33	10.00	10.00
cycles	12.50	12.50	29.25	29.25	29.25	29.25	0.00	0.00	0.00	0.00	18.33	18.33	18.33	10.00	10.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.13
Overall L1	29.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.25 cycles. At this rate:

8% of peak load performance is reached (8.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.92 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 423b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X30, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W22, W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 423cd4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 423cd4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423c2c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #76	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #68	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 423e34 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 423e34 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423d8c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 423f94 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 423f94 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423ef0 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4240f4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x594>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4240f4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x594>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42404c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 424134 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_–	0.03	0.04
▼Loop 524 - generate_chunk_kernel.f90-pp.f90:119-172 - exec–	0	0
▼Loop 525 - generate_chunk_kernel.f90-pp.f90:119-172 - exec–	0.01	0.01
▼Loop 523 - generate_chunk_kernel.f90-pp.f90:119-172 - exec–	0	0
○Loop 522 - generate_chunk_kernel.f90-pp.f90:119-172 - exec	0	0
▼Loop 529 - generate_chunk_kernel.f90-pp.f90:105-108 - exec–	0	0
○Loop 531 - generate_chunk_kernel.f90-pp.f90:106-106 - exec	0.01	0.01
○Loop 530 - generate_chunk_kernel.f90-pp.f90:106-107 - exec	0	0
▼Loop 532 - generate_chunk_kernel.f90-pp.f90:97-100 - exec–	0	0
○Loop 534 - generate_chunk_kernel.f90-pp.f90:98-98 - exec	0.01	0.01
○Loop 533 - generate_chunk_kernel.f90-pp.f90:98-99 - exec	0	0
▼Loop 526 - generate_chunk_kernel.f90-pp.f90:113-116 - exec–	0	0
○Loop 527 - generate_chunk_kernel.f90-pp.f90:114-115 - exec	0	0
○Loop 528 - generate_chunk_kernel.f90-pp.f90:114-114 - exec	0	0.01
▼Loop 535 - generate_chunk_kernel.f90-pp.f90:89-92 - exec–	0	0
○Loop 537 - generate_chunk_kernel.f90-pp.f90:90-90 - exec	0	0.01
○Loop 536 - generate_chunk_kernel.f90-pp.f90:90-91 - exec	0	0

Report Configuration

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Expensive FP math instructions/calls

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Back-end

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Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code