OV - exec - Function __nv_flux_calc_kernel_module_flux_calc_kernel__F1L49_1

	Function: __nv_flux_calc_kernel_module_flux_calc_kernel__F1L49_1_	Module: exec	Source: flux_calc_kernel.f90-pp.f90:49-65	Coverage: 4.61%

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/flux_calc_kernel.f90-pp.f90: 49 - 65

--------------------------------------------------------------------------------

49: # 49 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90"

50:     !$OMP PARALLEL

51: # 51 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90"

52:     ! Note that the loops calculate one extra flux than required, but this

53:     ! allows loop fusion that improves performance

54:     !$OMP DO

55:     DO k=y_min,y_max+1

56:     !$OMP SIMD

57:       DO j=x_min,x_max+1

58:         vol_flux_x(j,k)=0.25_8*dt*xarea(j,k)                  &

59:           *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1))

60:         vol_flux_y(j,k)=0.25_8*dt*yarea(j,k)                  &

61:           *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k))

62:       ENDDO

63:     ENDDO

64:   !$OMP END DO

65: # 65 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90"

0x423040 SUB	SP, SP, #192

0x423044 STP	X29, X30, [SP, #96]

0x423048 STP	X28, X27, [SP, #112]

0x42304c STP	X26, X25, [SP, #128]

0x423050 STP	X24, X23, [SP, #144]

0x423054 STP	X22, X21, [SP, #160]

0x423058 STP	X20, X19, [SP, #176]

0x42305c LDP	X8, X9, [X2]

0x423060 LDR	W21, [X0]

0x423064 ORR	X0, XZR, XZR

0x423068 ORR	X20, XZR, X2

0x42306c ADD	X3, SP, #92

0x423070 ADD	X4, SP, #88

0x423074 ADD	X5, SP, #84

0x423078 STR	WZR, [SP, #92]

0x42307c ADD	X6, SP, #80

0x423080 MOVZ	W2, #34

0x423084 MOVZ	W7, #1

0x423088 LDR	W9, [X9]

0x42308c LDR	W8, [X8]

0x423090 ORR	W1, WZR, W21

0x423094 ADD	W19, W9, #1

0x423098 STP	W19, W8, [SP, #84]

0x42309c MOVZ	W8, #1

0x4230a0 STR	W8, [SP, #80]

0x4230a4 STR	W8, [SP]

0x4230a8 BL	404c10

0x4230ac LDRSW	X8, [SP, #88]

0x4230b0 CMP	W8, W19

0x4230b4 B.GT	42333c

0x4230b8 LDR	W9, [SP, #84]

0x4230bc SUBS	W9, W9, W8

0x4230c0 B.MI	42333c

0x4230c4 LDP	X11, X10, [X20, #16]

0x4230c8 FMOV	D0, #0.2500000

0x4230cc CNTD	X14, ALL

0x4230d0 PTRUE	P0.D, ALL

0x4230d4 ADD	W9, W9, #1

0x4230d8 ADD	X13, X8, #1

0x4230dc MOVZ	X15, #1

0x4230e0 STR	W21, [SP, #12]

0x4230e4 LDR	W10, [X10]

0x4230e8 LDRSW	X1, [X11]

0x4230ec SUB	W10, W10, W1

0x4230f0 STR	X1, [SP, #32]

0x4230f4 ADD	W19, W10, #2

0x4230f8 ADD	W10, W10, #1

0x4230fc ADD	X25, X10, #1

0x423100 STR	W19, [SP, #28]

0x423104 STR	X25, [SP, #16]

0x423108 B	42311c

(519) 0x42310c ADD	X8, X8, #1

(519) 0x423110 SUBS	W9, W9, #1

(519) 0x423114 ADD	X13, X13, #1

(519) 0x423118 B.LE	423338

(519) 0x42311c CMP	W19, #1

(519) 0x423120 B.LT	42310c

(519) 0x423124 LDR	X10, [X20, #56]

(519) 0x423128 LDP	X17, X16, [X20, #112]

(519) 0x42312c LDR	X0, [X20, #32]

(519) 0x423130 ORR	X22, XZR, X1

(519) 0x423134 ORR	W23, WZR, W19

(519) 0x423138 CMP	X25, X14

(519) 0x42313c LDP	X28, X30, [X20, #208]

(519) 0x423140 LDR	X18, [X10]

(519) 0x423144 LDP	X10, X11, [X20, #96]

(519) 0x423148 LDP	X2, X5, [X20, #152]

(519) 0x42314c LDR	X3, [X10]

(519) 0x423150 LDR	X10, [X20, #176]

(519) 0x423154 LDR	D1, [X11]

(519) 0x423158 LDR	X7, [X10]

(519) 0x42315c LDP	X10, X6, [X20, #192]

(519) 0x423160 FMUL	D1, D1, D0

(519) 0x423164 LDR	X21, [X10]

(519) 0x423168 B.CC	423270

(519) 0x42316c UDIV	X10, X25, X14

(519) 0x423170 MADD	X11, X18, X13, X1

(519) 0x423174 MADD	X12, X18, X8, X1

(519) 0x423178 ORR	X4, XZR, X0

(519) 0x42317c ORR	X0, XZR, X17

(519) 0x423180 STP	X30, X28, [SP, #48]

(519) 0x423184 ORR	X24, XZR, XZR

(519) 0x423188 DUP	Z2.D, Z1.D[0]

(519) 0x42318c SUB	X11, X11, X3

(519) 0x423190 SUB	X12, X12, X3

(519) 0x423194 STP	X4, X0, [SP, #64]

(519) 0x423198 UBFM	X11, X11, #61, #60

(519) 0x42319c UBFM	X17, X12, #61, #60

(519) 0x4231a0 ADD	X26, X16, X11

(519) 0x4231a4 ADD	X27, X2, X11

(519) 0x4231a8 MADD	X11, X7, X8, X1

(519) 0x4231ac ADD	X28, X28, X17

(519) 0x4231b0 ADD	X30, X30, X17

(519) 0x4231b4 ADD	X12, X0, X17

(519) 0x4231b8 SUB	X11, X11, X21

(519) 0x4231bc MADD	X29, X10, X14, XZR

(519) 0x4231c0 SUB	X10, X25, X29

(519) 0x4231c4 SUB	W23, W19, W29

(519) 0x4231c8 ADD	X19, X4, X17

(519) 0x4231cc ADD	X25, X16, X17

(519) 0x4231d0 ADD	X22, X29, X1

(519) 0x4231d4 STR	X10, [SP, #40]

(519) 0x4231d8 ADD	X10, X2, X17

(519) 0x4231dc UBFM	X17, X11, #61, #60

(519) 0x4231e0 ADD	X11, X5, X17

(519) 0x4231e4 ADD	X17, X6, X17

  (521) 0x4231e8 LD1D	{Z3.D}, P0/Z, [X27, X24,LSL #3]

  (521) 0x4231ec LD1D	{Z4.D}, P0/Z, [X10, X24,LSL #3]

  (521) 0x4231f0 UBFM	X0, X24, #61, #60

  (521) 0x4231f4 ADD	X1, X30, X0

  (521) 0x4231f8 LD1D	{Z5.D}, P0/Z, [X25, X24,LSL #3]

  (521) 0x4231fc ADD	X0, X28, X0

  (521) 0x423200 FADD	Z3.D, Z3.D, Z4.D

  (521) 0x423204 LD1D	{Z4.D}, P0/Z, [X26, X24,LSL #3]

  (521) 0x423208 FADD	Z4.D, Z4.D, Z5.D

  (521) 0x42320c FADD	Z3.D, Z3.D, Z4.D

  (521) 0x423210 LD1D	{Z4.D}, P0/Z, [X12, X24,LSL #3]

  (521) 0x423214 FMUL	Z4.D, Z4.D, Z2.D

  (521) 0x423218 FMUL	Z3.D, Z3.D, Z4.D

  (521) 0x42321c ST1D	{Z3.D}, P0, [X19, X24,LSL #3]

  (521) 0x423220 LD1D	{Z3.D}, P0/Z, [X1, X15,LSL #3]

  (521) 0x423224 LD1D	{Z4.D}, P0/Z, [X1, MUL VL]

  (521) 0x423228 FADD	Z3.D, Z3.D, Z4.D

  (521) 0x42322c LD1D	{Z4.D}, P0/Z, [X0, X15,LSL #3]

  (521) 0x423230 LD1D	{Z5.D}, P0/Z, [X0, MUL VL]

  (521) 0x423234 FADD	Z4.D, Z4.D, Z5.D

  (521) 0x423238 FADD	Z3.D, Z3.D, Z4.D

  (521) 0x42323c LD1D	{Z4.D}, P0/Z, [X17, X24,LSL #3]

  (521) 0x423240 FMUL	Z4.D, Z2.D, Z4.D

  (521) 0x423244 FMUL	Z3.D, Z3.D, Z4.D

  (521) 0x423248 ST1D	{Z3.D}, P0, [X11, X24,LSL #3]

  (521) 0x42324c ADD	X24, X24, X14

  (521) 0x423250 CMP	X29, X24

  (521) 0x423254 B.NE	4231e8

(519) 0x423258 LDP	X1, X10, [SP, #32]

(519) 0x42325c LDR	W19, [SP, #28]

(519) 0x423260 LDR	X25, [SP, #16]

(519) 0x423264 LDP	X0, X17, [SP, #64]

(519) 0x423268 LDP	X30, X28, [SP, #48]

(519) 0x42326c CBZ	X10, 42310c

(519) 0x423270 MADD	X10, X18, X13, X22

(519) 0x423274 MADD	X11, X7, X8, X22

(519) 0x423278 ADD	W23, W23, #1

(519) 0x42327c ORR	X24, XZR, XZR

(519) 0x423280 SUB	X10, X10, X3

(519) 0x423284 SUB	X11, X11, X21

(519) 0x423288 UBFM	X10, X10, #61, #60

(519) 0x42328c UBFM	X11, X11, #61, #60

(519) 0x423290 ADD	X7, X16, X10

(519) 0x423294 ADD	X21, X2, X10

(519) 0x423298 MADD	X10, X18, X8, X22

(519) 0x42329c ADD	X6, X6, X11

(519) 0x4232a0 SUB	X10, X10, X3

(519) 0x4232a4 UBFM	X10, X10, #61, #60

(519) 0x4232a8 ADD	X12, X30, X10

(519) 0x4232ac ADD	X0, X0, X10

(519) 0x4232b0 ADD	X16, X16, X10

(519) 0x4232b4 ADD	X18, X12, #8

(519) 0x4232b8 ADD	X12, X28, X10

(519) 0x4232bc ADD	X3, X12, #8

(519) 0x4232c0 ADD	X12, X17, X10

(519) 0x4232c4 ADD	X10, X2, X10

(519) 0x4232c8 ADD	X17, X5, X11

  (520) 0x4232cc LDR	D2, [X21, X24]

  (520) 0x4232d0 LDR	D3, [X10, X24]

  (520) 0x4232d4 LDR	D4, [X16, X24]

  (520) 0x4232d8 ADD	X11, X18, X24

  (520) 0x4232dc SUB	W23, W23, #1

  (520) 0x4232e0 CMP	W23, #1

  (520) 0x4232e4 FADD	D2, D2, D3

  (520) 0x4232e8 LDR	D3, [X7, X24]

  (520) 0x4232ec FADD	D3, D3, D4

  (520) 0x4232f0 FADD	D2, D2, D3

  (520) 0x4232f4 LDR	D3, [X12, X24]

  (520) 0x4232f8 FMUL	D3, D3, D1

  (520) 0x4232fc FMUL	D2, D2, D3

  (520) 0x423300 STR	D2, [X0, X24]

  (520) 0x423304 LDP	D3, D2, [X11, #1016]

  (520) 0x423308 ADD	X11, X3, X24

  (520) 0x42330c FADD	D2, D2, D3

  (520) 0x423310 LDP	D4, D3, [X11, #1016]

  (520) 0x423314 FADD	D3, D3, D4

  (520) 0x423318 FADD	D2, D2, D3

  (520) 0x42331c LDR	D3, [X6, X24]

  (520) 0x423320 FMUL	D3, D1, D3

  (520) 0x423324 FMUL	D2, D2, D3

  (520) 0x423328 STR	D2, [X17, X24]

  (520) 0x42332c ADD	X24, X24, #8

  (520) 0x423330 B.HI	4232cc

(519) 0x423334 B	42310c

0x423338 LDR	W21, [SP, #12]

0x42333c ORR	X0, XZR, XZR

0x423340 ORR	W1, WZR, W21

0x423344 BL	404d30

0x423348 ORR	X0, XZR, XZR

0x42334c ORR	W1, WZR, W21

0x423350 BL	404900

0x423354 LDP	X20, X19, [SP, #176]

0x423358 LDP	X22, X21, [SP, #160]

0x42335c LDP	X24, X23, [SP, #144]

0x423360 LDP	X26, X25, [SP, #128]

0x423364 LDP	X28, X27, [SP, #112]

0x423368 LDP	X29, X30, [SP, #96]

0x42336c ADD	SP, SP, #192

0x423370 RET

0x423374 HINT	#0

0x423378 HINT	#0

0x42337c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	flux_calc_kernel.f90-pp.f90:49-65
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/flux_calc_kernel.f90-pp.f90:49-65.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 1.00 cycles (10.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.00 to 1.50 cycles (6.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	7.75	7.75	7.75	7.75	0.25	0.25	0.25	0.25	10.00	10.00	10.00	7.00	7.00
cycles	3.50	3.50	7.75	7.75	7.75	7.75	0.25	0.25	0.25	0.25	10.00	10.00	10.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Overall L1	10.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 423040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X6, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W19, W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42333c <__nv_flux_calc_kernel_module_flux_calc_kernel__F1L49_1_+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42333c <__nv_flux_calc_kernel_module_flux_calc_kernel__F1L49_1_+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, W10, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W19, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W19, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42311c <__nv_flux_calc_kernel_module_flux_calc_kernel__F1L49_1_+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W21, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	flux_calc_kernel.f90-pp.f90:49-65
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.00 to 1.50 cycles (6.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	7.75	7.75	7.75	7.75	0.25	0.25	0.25	0.25	10.00	10.00	10.00	7.00	7.00
cycles	3.50	3.50	7.75	7.75	7.75	7.75	0.25	0.25	0.25	0.25	10.00	10.00	10.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Overall L1	10.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 423040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X6, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W19, W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42333c <__nv_flux_calc_kernel_module_flux_calc_kernel__F1L49_1_+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42333c <__nv_flux_calc_kernel_module_flux_calc_kernel__F1L49_1_+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, W10, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W19, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W19, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42311c <__nv_flux_calc_kernel_module_flux_calc_kernel__F1L49_1_+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W21, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼__nv_flux_calc_kernel_module_flux_calc_kernel__F1L49_1_–	4.61	6.25
▼Loop 519 - flux_calc_kernel.f90-pp.f90:54-62 - exec–	0.01	0.02
○Loop 521 - flux_calc_kernel.f90-pp.f90:57-59 - exec	4.6	6.21
○Loop 520 - flux_calc_kernel.f90-pp.f90:57-61 - exec	0	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code