OV - exec - Function __nv_field_summary_kernel_module_field_summary_kernel__F1L54_1

	Function: __nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_	Module: exec	Source: field_summary_kernel.f90-pp.f90:54-75	Coverage: 0.34%

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/field_summary_kernel.f90-pp.f90: 54 - 75

--------------------------------------------------------------------------------

54: # 54 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90"

55:     !$OMP PARALLEL

56:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

57:     DO k=y_min,y_max

58:     !$OMP SIMD

59:       DO j=x_min,x_max

60:         vsqrd=0.0

61:         DO kv=k,k+1

62:           DO jv=j,j+1

63:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

64:           ENDDO

65:         ENDDO

66:         cell_vol=volume(j,k)

67:         cell_mass=cell_vol*density0(j,k)

68:         vol=vol+cell_vol

69:         mass=mass+cell_mass

70:         ie=ie+cell_mass*energy0(j,k)

71:         ke=ke+cell_mass*0.5*vsqrd

72:         press=press+cell_vol*pressure(j,k)

73:       ENDDO

74:     ENDDO

75:   !$OMP END DO

0x4222d0 STP	X29, X30, [SP, #928]!

0x4222d4 STP	X28, X27, [SP, #16]

0x4222d8 STP	X26, X25, [SP, #32]

0x4222dc STP	X24, X23, [SP, #48]

0x4222e0 STP	X22, X21, [SP, #64]

0x4222e4 STP	X20, X19, [SP, #80]

0x4222e8 ADDVL	SP, SP, #59

0x4222ec SUB	SP, SP, #96

0x4222f0 LDP	X8, X9, [X2, #40]

0x4222f4 LDR	W1, [X0]

0x4222f8 ORR	X0, XZR, XZR

0x4222fc ORR	X20, XZR, X2

0x422300 ADD	X3, SP, #92

0x422304 ADD	X4, SP, #88

0x422308 ADD	X5, SP, #84

0x42230c STR	WZR, [SP, #92]

0x422310 ADD	X6, SP, #80

0x422314 MOVZ	W2, #34

0x422318 MOVZ	W7, #1

0x42231c LDR	W19, [X9]

0x422320 LDR	W8, [X8]

0x422324 STR	W1, [SP, #28]

0x422328 STP	W19, W8, [SP, #84]

0x42232c MOVZ	W8, #1

0x422330 STR	W8, [SP, #80]

0x422334 STR	W8, [SP]

0x422338 BL	404c10

0x42233c LDRSW	X17, [SP, #88]

0x422340 MOVI	D18, #0

0x422344 CMP	W17, W19

0x422348 B.LE	422360

0x42234c MOVI	D19, #0

0x422350 MOVI	D20, #0

0x422354 MOVI	D21, #0

0x422358 MOVI	D22, #0

0x42235c B	422690

0x422360 LDR	W8, [SP, #84]

0x422364 MOVI	D19, #0

0x422368 MOVI	D20, #0

0x42236c SUBS	W8, W8, W17

0x422370 MOVI	D21, #0

0x422374 MOVI	D22, #0

0x422378 B.MI	422690

0x42237c LDP	X10, X9, [X20, #56]

0x422380 MOVI	D0, #0

0x422384 FMOV	D1, #0.2500000

0x422388 CNTD	X14, ALL

0x42238c PTRUE	P0.D, ALL

0x422390 ADD	W8, W8, #1

0x422394 MOVZ	X15, #1

0x422398 LDR	W9, [X9]

0x42239c LDRSW	X24, [X10]

0x4223a0 MOVZ	W10, #1

0x4223a4 FMOV	D2, #0.5000000

0x4223a8 FDUP	Z3.D, #80

0x4223ac DUP	Z4.D, #0

0x4223b0 MOVI	D18, #0

0x4223b4 MOVI	D19, #0

0x4223b8 MOVI	D20, #0

0x4223bc MOVI	D21, #0

0x4223c0 MOVI	D22, #0

0x4223c4 SUB	W19, W9, W24

0x4223c8 SUB	W9, W9, W24

0x4223cc STR	X24, [SP, #56]

0x4223d0 ADD	W26, W19, #1

0x4223d4 CMP	W26, #1

0x4223d8 STP	W26, W19, [SP, #48]

0x4223dc CSINC	W10, W10, W19, #10

0x4223e0 SUB	W9, W9, W10

0x4223e4 ADD	W9, W9, #1

0x4223e8 ADD	X27, X9, #1

0x4223ec UBFM	X9, X24, #61, #60

0x4223f0 STP	X9, X27, [SP, #32]

0x4223f4 B	422410

0x4223f8 HINT	#0

0x4223fc HINT	#0

(517) 0x422400 ADD	X16, X17, #1

(517) 0x422404 ORR	X17, XZR, X16

(517) 0x422408 SUBS	W8, W8, #1

(517) 0x42240c B.LE	422690

(517) 0x422410 TBNZ	W19, #31, 422400

0x422414 LDR	X9, [X20, #112]

0x422418 LDR	X0, [X20, #88]

0x42241c LDR	X3, [X20, #168]

0x422420 ADD	X16, X17, #1

0x422424 CMP	X27, X14

0x422428 LDP	X7, X21, [X20, #232]

0x42242c LDR	X2, [X9]

0x422430 LDP	X9, X18, [X20, #152]

0x422434 LDR	X1, [X9]

0x422438 LDR	X9, [X20, #184]

0x42243c MADD	X5, X2, X16, XZR

0x422440 LDR	X9, [X9]

0x422444 MADD	X6, X9, X17, XZR

0x422448 LDP	X9, X4, [X20, #216]

0x42244c LDR	X22, [X9]

0x422450 B.CS	422460

0x422454 ORR	X23, XZR, X24

0x422458 ORR	W28, WZR, W26

0x42245c B	4225a0

0x422460 UDIV	X9, X27, X14

0x422464 LDR	X12, [SP, #32]

0x422468 MADD	X10, X17, X2, XZR

0x42246c UBFM	X13, X1, #61, #60

0x422470 UBFM	X30, X5, #61, #60

0x422474 ORR	X25, XZR, XZR

0x422478 UBFM	X10, X10, #61, #60

0x42247c SUB	X10, X10, X13

0x422480 ADD	X11, X0, X12

0x422484 ADD	X19, X18, X12

0x422488 ORR	X12, XZR, X27

0x42248c ADD	X28, X19, X10

0x422490 ADD	X27, X11, X10

0x422494 MADD	X29, X9, X14, XZR

0x422498 SUB	X9, X12, X29

0x42249c ADD	X23, X29, X24

0x4224a0 STR	X9, [SP, #64]

0x4224a4 SUB	W9, W26, W29

0x4224a8 STR	W9, [SP, #76]

0x4224ac SUB	X9, X30, X13

0x4224b0 ADD	X30, X11, X9

0x4224b4 ADD	X19, X19, X9

0x4224b8 ADD	X9, X24, X6

0x4224bc SUB	X9, X9, X22

0x4224c0 UBFM	X10, X9, #61, #60

0x4224c4 ADD	X13, X21, X10

0x4224c8 ADD	X11, X7, X10

0x4224cc ADD	X9, X4, X10

0x4224d0 ADD	X10, X3, X10

0x4224d4 HINT	#0

0x4224d8 HINT	#0

0x4224dc HINT	#0

(511) 0x4224e0 UBFM	X12, X25, #61, #60

(511) 0x4224e4 ADD	X26, X28, X12

(511) 0x4224e8 ADD	X24, X27, X12

(511) 0x4224ec LD1D	{Z5.D}, P0/Z, [X26, MUL VL]

(511) 0x4224f0 LD1D	{Z6.D}, P0/Z, [X24, MUL VL]

(511) 0x4224f4 LD1D	{Z7.D}, P0/Z, [X24, X15,LSL #3]

(511) 0x4224f8 ADD	X24, X19, X12

(511) 0x4224fc ADD	X12, X30, X12

(511) 0x422500 FMUL	Z6.D, Z6.D, Z6.D

(511) 0x422504 FMUL	Z7.D, Z7.D, Z7.D

(511) 0x422508 FMAD	Z5.D, P0/M, Z5.D, Z6.D

(511) 0x42250c LD1D	{Z6.D}, P0/Z, [X26, X15,LSL #3]

(511) 0x422510 FMAD	Z5.D, P0/M, Z3.D, Z4.D

(511) 0x422514 FMAD	Z6.D, P0/M, Z6.D, Z7.D

(511) 0x422518 FMLA	Z5.D, P0/M, Z6.D, Z3.D

(511) 0x42251c LD1D	{Z6.D}, P0/Z, [X24, MUL VL]

(511) 0x422520 LD1D	{Z7.D}, P0/Z, [X12, MUL VL]

(511) 0x422524 LD1D	{Z16.D}, P0/Z, [X11, X25,LSL #3]

(511) 0x422528 FMUL	Z7.D, Z7.D, Z7.D

(511) 0x42252c FMAD	Z6.D, P0/M, Z6.D, Z7.D

(511) 0x422530 LD1D	{Z7.D}, P0/Z, [X24, X15,LSL #3]

(511) 0x422534 FMLA	Z5.D, P0/M, Z6.D, Z3.D

(511) 0x422538 LD1D	{Z6.D}, P0/Z, [X12, X15,LSL #3]

(511) 0x42253c FMUL	Z6.D, Z6.D, Z6.D

(511) 0x422540 FMLA	Z6.D, P0/M, Z7.D, Z7.D

(511) 0x422544 LD1D	{Z7.D}, P0/Z, [X9, X25,LSL #3]

(511) 0x422548 FMLA	Z5.D, P0/M, Z6.D, Z3.D

(511) 0x42254c LD1D	{Z6.D}, P0/Z, [X10, X25,LSL #3]

(511) 0x422550 FMUL	Z7.D, Z6.D, Z7.D

(511) 0x422554 MOVPRFX	Z17, Z7

(511) 0x422558 FMUL	Z17.D, P0/M, Z17.D, #0

(511) 0x42255c FMUL	Z5.D, Z5.D, Z17.D

(511) 0x422560 LD1D	{Z17.D}, P0/Z, [X13, X25,LSL #3]

(511) 0x422564 FADDA	D22, P0, D22, Z6.D

(511) 0x422568 ADD	X25, X25, X14

(511) 0x42256c CMP	X29, X25

(511) 0x422570 FMUL	Z16.D, Z7.D, Z16.D

(511) 0x422574 FADDA	D18, P0, D18, Z5.D

(511) 0x422578 FADDA	D21, P0, D21, Z7.D

(511) 0x42257c FMUL	Z17.D, Z6.D, Z17.D

(511) 0x422580 FADDA	D19, P0, D19, Z16.D

(511) 0x422584 FADDA	D20, P0, D20, Z17.D

(511) 0x422588 B.NE	4224e0

0x42258c LDP	X24, X9, [SP, #56]

0x422590 LDP	W26, W19, [SP, #48]

0x422594 LDR	X27, [SP, #40]

0x422598 LDR	W28, [SP, #76]

0x42259c CBZ	X9, 422404

0x4225a0 MADD	X12, X2, X17, XZR

0x4225a4 ADD	X9, X23, X6

0x4225a8 ADD	X17, X23, X5

0x4225ac ORR	X25, XZR, XZR

0x4225b0 ADD	X12, X23, X12

0x4225b4 SUB	X9, X9, X22

0x4225b8 UBFM	X13, X9, #61, #60

0x4225bc SUB	X17, X17, X1

0x4225c0 SUB	X12, X12, X1

0x4225c4 UBFM	X2, X17, #61, #60

0x4225c8 ADD	X11, X21, X13

0x4225cc ADD	X9, X7, X13

0x4225d0 ADD	X10, X4, X13

0x4225d4 ADD	X13, X3, X13

0x4225d8 ADD	W3, W28, #1

0x4225dc UBFM	X12, X12, #61, #60

0x4225e0 ADD	X17, X0, X2

0x4225e4 ADD	X2, X18, X2

0x4225e8 ADD	X18, X18, X12

0x4225ec ADD	X0, X0, X12

0x4225f0 HINT	#0

0x4225f4 HINT	#0

0x4225f8 HINT	#0

0x4225fc HINT	#0

(518) 0x422600 ADD	X1, X0, X25

(518) 0x422604 ADD	X12, X18, X25

(518) 0x422608 SUB	W3, W3, #1

(518) 0x42260c CMP	W3, #1

(518) 0x422610 LDP	D5, D6, [X1]

(518) 0x422614 LDP	D7, D16, [X12]

(518) 0x422618 ADD	X1, X17, X25

(518) 0x42261c ADD	X12, X2, X25

(518) 0x422620 FMUL	D6, D6, D6

(518) 0x422624 FMUL	D5, D5, D5

(518) 0x422628 FMADD	D6, D16, D16, D6

(518) 0x42262c FMADD	D5, D7, D7, D5

(518) 0x422630 LDP	D7, D16, [X1]

(518) 0x422634 FMADD	D5, D5, D1, D0

(518) 0x422638 FMUL	D7, D7, D7

(518) 0x42263c FMADD	D5, D6, D1, D5

(518) 0x422640 LDP	D17, D6, [X12]

(518) 0x422644 FMADD	D7, D17, D17, D7

(518) 0x422648 FMADD	D5, D7, D1, D5

(518) 0x42264c FMUL	D7, D16, D16

(518) 0x422650 LDR	D16, [X9, X25]

(518) 0x422654 FMADD	D6, D6, D6, D7

(518) 0x422658 LDR	D7, [X10, X25]

(518) 0x42265c FMADD	D5, D6, D1, D5

(518) 0x422660 LDR	D6, [X13, X25]

(518) 0x422664 FMUL	D7, D6, D7

(518) 0x422668 FADD	D22, D22, D6

(518) 0x42266c FADD	D21, D21, D7

(518) 0x422670 FMADD	D19, D7, D16, D19

(518) 0x422674 FMUL	D7, D7, D2

(518) 0x422678 FMADD	D18, D5, D7, D18

(518) 0x42267c LDR	D5, [X11, X25]

(518) 0x422680 ADD	X25, X25, #8

(518) 0x422684 FMADD	D20, D6, D5, D20

(518) 0x422688 B.GT	422600

0x42268c B	422404

0x422690 ADD	X8, SP, #96

0x422694 ORR	X0, XZR, XZR

0x422698 STR	Z22, [X8, MUL VL]

0x42269c ADD	X8, SP, #96

0x4226a0 STR	Z21, [X8, #1, MUL VL]

0x4226a4 ADD	X8, SP, #96

0x4226a8 STR	Z20, [X8, #2, MUL VL]

0x4226ac ADD	X8, SP, #96

0x4226b0 STR	Z19, [X8, #3, MUL VL]

0x4226b4 ADD	X8, SP, #96

0x4226b8 STR	Z18, [X8, #4, MUL VL]

0x4226bc LDR	W1, [SP, #28]

0x4226c0 BL	404d30

0x4226c4 ADD	X8, SP, #96

0x4226c8 LDR	Z1, [X8, MUL VL]

0x4226cc LDR	X8, [X20]

0x4226d0 LDAR	X9, [X8]

0x4226d4 ORR	X8, XZR, X9

0x4226d8 HINT	#0

0x4226dc HINT	#0

(512) 0x4226e0 FMOV	D0, X9

(512) 0x4226e4 LDR	X10, [X20]

(512) 0x4226e8 FADD	D0, D1, D0

(512) 0x4226ec FMOV	X11, D0

(512) 0x4226f0 CASAL	X8, X11, [X10]

(512) 0x4226f4 CMP	X8, X9

(512) 0x4226f8 ORR	X9, XZR, X8

(512) 0x4226fc B.NE	4226e0

0x422700 LDR	X8, [X20, #8]

0x422704 ADD	X10, SP, #96

0x422708 LDAR	X9, [X8]

0x42270c LDR	Z1, [X10, #1, MUL VL]

0x422710 ORR	X8, XZR, X9

0x422714 HINT	#0

0x422718 HINT	#0

0x42271c HINT	#0

(513) 0x422720 FMOV	D0, X9

(513) 0x422724 LDR	X10, [X20, #8]

(513) 0x422728 FADD	D0, D1, D0

(513) 0x42272c FMOV	X11, D0

(513) 0x422730 CASAL	X8, X11, [X10]

(513) 0x422734 CMP	X8, X9

(513) 0x422738 ORR	X9, XZR, X8

(513) 0x42273c B.NE	422720

0x422740 LDR	X8, [X20, #16]

0x422744 ADD	X10, SP, #96

0x422748 LDAR	X9, [X8]

0x42274c LDR	Z1, [X10, #4, MUL VL]

0x422750 ADD	X10, SP, #96

0x422754 LDR	Z2, [X10, #3, MUL VL]

0x422758 ADD	X10, SP, #96

0x42275c LDR	Z3, [X10, #2, MUL VL]

0x422760 ORR	X8, XZR, X9

(514) 0x422764 FMOV	D0, X9

(514) 0x422768 LDR	X10, [X20, #16]

(514) 0x42276c FADD	D0, D3, D0

(514) 0x422770 FMOV	X11, D0

(514) 0x422774 CASAL	X8, X11, [X10]

(514) 0x422778 CMP	X8, X9

(514) 0x42277c ORR	X9, XZR, X8

(514) 0x422780 B.NE	422764

0x422784 LDR	X8, [X20, #24]

0x422788 LDAR	X9, [X8]

0x42278c ORR	X8, XZR, X9

0x422790 HINT	#0

0x422794 HINT	#0

0x422798 HINT	#0

0x42279c HINT	#0

(515) 0x4227a0 FMOV	D0, X9

(515) 0x4227a4 LDR	X10, [X20, #24]

(515) 0x4227a8 FADD	D0, D2, D0

(515) 0x4227ac FMOV	X11, D0

(515) 0x4227b0 CASAL	X8, X11, [X10]

(515) 0x4227b4 CMP	X8, X9

(515) 0x4227b8 ORR	X9, XZR, X8

(515) 0x4227bc B.NE	4227a0

0x4227c0 LDR	X8, [X20, #32]

0x4227c4 LDAR	X9, [X8]

0x4227c8 ORR	X8, XZR, X9

(516) 0x4227cc FMOV	D0, X9

(516) 0x4227d0 LDR	X10, [X20, #32]

(516) 0x4227d4 FADD	D0, D1, D0

(516) 0x4227d8 FMOV	X11, D0

(516) 0x4227dc CASAL	X8, X11, [X10]

(516) 0x4227e0 CMP	X8, X9

(516) 0x4227e4 ORR	X9, XZR, X8

(516) 0x4227e8 B.NE	4227cc

0x4227ec LDR	W1, [SP, #28]

0x4227f0 ORR	X0, XZR, XZR

0x4227f4 BL	404900

0x4227f8 ADDVL	SP, SP, #5

0x4227fc ADD	SP, SP, #96

0x422800 LDP	X20, X19, [SP, #80]

0x422804 LDP	X22, X21, [SP, #64]

0x422808 LDP	X24, X23, [SP, #48]

0x42280c LDP	X26, X25, [SP, #32]

0x422810 LDP	X28, X27, [SP, #16]

0x422814 LDP	X29, X30, [SP], #96

0x422818 RET

0x42281c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	field_summary_kernel.f90-pp.f90:54-75
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/field_summary_kernel.f90-pp.f90:54-75.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.50 to 5.00 cycles (5.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.50 to 21.33 cycles (1.20x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.50 to 1.50 cycles (17.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 560 bytes. The binary function is storing 324 bytes.

General properties

nb instructions	217
loop length	868
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

24.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	25.50	25.50	25.50	25.50	6.00	6.00	6.00	6.00	21.33	21.33	21.33	8.00	8.00
cycles	6.00	6.00	25.50	25.50	25.50	25.50	6.00	6.00	6.00	6.00	21.33	21.33	21.33	8.00	8.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	24.13
Overall L1	25.50

Vectorization ratios

INT

all	14%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	14%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.50 cycles. At this rate:

22% of peak load performance is reached (21.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.71 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4222d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADDVL SP, SP, #59	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X9, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X6, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W19, W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X17, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D18, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CMP W17, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 422360 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D19, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D21, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D22, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 422690 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D19, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SUBS W8, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVI D21, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D22, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B.MI 422690 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D2, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDUP Z3.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z4.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MOVI D18, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D19, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D21, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D22, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SUB W19, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W26, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP W26, W19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSINC W10, W10, W19, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X9, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 422410 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDR X9, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDP X7, X21, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X9, X18, [X20, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X5, X2, X16, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X6, X9, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X9, X4, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CS 422460 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W28, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4225a0 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X27, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDR X12, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X17, X2, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X13, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X19, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X29, X9, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X9, X12, X29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X29, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W9, W26, W29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W9, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X9, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X24, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X10, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X7, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDP X24, X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP W26, W19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W28, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X9, 422404 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X12, X2, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X23, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X23, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X23, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X17, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X21, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X18, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 422404 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z22, [X8, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z21, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z20, [X8, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z19, [X8, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z18, [X8, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR Z1, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDAR X9, [X8]
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDAR X9, [X8]
LDR Z1, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X8, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDAR X9, [X8]
LDR Z1, [X10, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X10, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR Z2, [X10, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X10, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR Z3, [X10, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDAR X9, [X8]
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDR X8, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDAR X9, [X8]
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL SP, SP, #5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	field_summary_kernel.f90-pp.f90:54-75
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.50 to 5.00 cycles (5.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.50 to 1.50 cycles (17.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 560 bytes. The binary function is storing 324 bytes.

General properties

nb instructions	217
loop length	868
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

24.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	25.50	25.50	25.50	25.50	6.00	6.00	6.00	6.00	21.33	21.33	21.33	8.00	8.00
cycles	6.00	6.00	25.50	25.50	25.50	25.50	6.00	6.00	6.00	6.00	21.33	21.33	21.33	8.00	8.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	24.13
Overall L1	25.50

Vectorization ratios

INT

all	14%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	14%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.50 cycles. At this rate:

22% of peak load performance is reached (21.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.71 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4222d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADDVL SP, SP, #59	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X9, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X6, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W19, W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X17, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D18, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CMP W17, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 422360 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D19, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D21, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D22, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 422690 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D19, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SUBS W8, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVI D21, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D22, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B.MI 422690 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D2, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDUP Z3.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z4.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MOVI D18, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D19, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D21, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D22, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SUB W19, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W26, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP W26, W19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSINC W10, W10, W19, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X9, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 422410 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDR X9, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDP X7, X21, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X9, X18, [X20, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X5, X2, X16, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X6, X9, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X9, X4, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CS 422460 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W28, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4225a0 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X27, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDR X12, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X17, X2, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X13, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X19, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X29, X9, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X9, X12, X29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X29, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W9, W26, W29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W9, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X9, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X24, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X10, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X7, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDP X24, X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP W26, W19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W28, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X9, 422404 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X12, X2, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X23, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X23, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X23, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X17, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X21, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X18, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 422404 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z22, [X8, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z21, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z20, [X8, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z19, [X8, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z18, [X8, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR Z1, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDAR X9, [X8]
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDAR X9, [X8]
LDR Z1, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X8, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDAR X9, [X8]
LDR Z1, [X10, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X10, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR Z2, [X10, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X10, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR Z3, [X10, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDAR X9, [X8]
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDR X8, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDAR X9, [X8]
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL SP, SP, #5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_–	0.34	0.46
○Loop 511 - field_summary_kernel.f90-pp.f90:62-71 - exec	0.34	0.45
○Loop 518 - field_summary_kernel.f90-pp.f90:62-72 - exec	0	0
○Loop 516 - field_summary_kernel.f90-pp.f90:73-73 - exec	0	0
○Loop 517 - field_summary_kernel.f90-pp.f90:58-73 - exec	0	0
○Loop 515 - field_summary_kernel.f90-pp.f90:73-73 - exec	0	0
○Loop 512 - field_summary_kernel.f90-pp.f90:73-73 - exec	0	0
○Loop 513 - field_summary_kernel.f90-pp.f90:73-73 - exec	0	0
○Loop 514 - field_summary_kernel.f90-pp.f90:73-73 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code