| Function: advec_mom_kernel | Module: exec | Source: advec_mom_kernel.f90-pp.f90:79-254 [...] | Coverage: 34.41% |
|---|
| Function: advec_mom_kernel | Module: exec | Source: advec_mom_kernel.f90-pp.f90:79-254 [...] | Coverage: 34.41% |
|---|
/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 79 - 254 |
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79: # 79 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90" |
80: !$OMP PARALLEL |
81: # 81 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90" |
82: IF(mom_sweep.EQ.1)THEN ! x 1 |
83: !$OMP DO |
84: DO k=y_min-2,y_max+2 |
85: !$OMP SIMD |
86: DO j=x_min-2,x_max+2 |
87: post_vol(j,k)= volume(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k) |
88: pre_vol(j,k)=post_vol(j,k)+vol_flux_x(j+1,k )-vol_flux_x(j,k) |
89: ENDDO |
90: ENDDO |
91: !$OMP END DO |
92: ELSEIF(mom_sweep.EQ.2)THEN ! y 1 |
93: !$OMP DO |
94: DO k=y_min-2,y_max+2 |
95: !$OMP SIMD |
96: DO j=x_min-2,x_max+2 |
97: post_vol(j,k)= volume(j,k)+vol_flux_x(j+1,k )-vol_flux_x(j,k) |
98: pre_vol(j,k)=post_vol(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k) |
99: ENDDO |
100: ENDDO |
101: !$OMP END DO |
102: ELSEIF(mom_sweep.EQ.3)THEN ! x 2 |
103: !$OMP DO |
104: DO k=y_min-2,y_max+2 |
105: !$OMP SIMD |
106: DO j=x_min-2,x_max+2 |
107: post_vol(j,k)=volume(j,k) |
108: pre_vol(j,k)=post_vol(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k) |
109: ENDDO |
110: ENDDO |
111: !$OMP END DO |
112: ELSEIF(mom_sweep.EQ.4)THEN ! y 2 |
113: !$OMP DO |
114: DO k=y_min-2,y_max+2 |
115: !$OMP SIMD |
116: DO j=x_min-2,x_max+2 |
117: post_vol(j,k)=volume(j,k) |
118: pre_vol(j,k)=post_vol(j,k)+vol_flux_x(j+1,k )-vol_flux_x(j,k) |
119: ENDDO |
120: ENDDO |
121: !$OMP END DO |
122: ENDIF |
123: # 123 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90" |
124: IF(direction.EQ.1)THEN |
125: IF(which_vel.EQ.1)THEN |
126: !$OMP DO |
127: DO k=y_min,y_max+1 |
128: !$OMP SIMD |
129: DO j=x_min-2,x_max+2 |
130: ! Find staggered mesh mass fluxes, nodal masses and volumes. |
131: node_flux(j,k)=0.25_8*(mass_flux_x(j,k-1 )+mass_flux_x(j ,k) & |
132: +mass_flux_x(j+1,k-1)+mass_flux_x(j+1,k)) |
133: ENDDO |
134: ENDDO |
135: !$OMP END DO |
136: !$OMP DO |
137: DO k=y_min,y_max+1 |
138: !$OMP SIMD |
139: DO j=x_min-1,x_max+2 |
140: ! Staggered cell mass post advection |
141: node_mass_post(j,k)=0.25_8*(density1(j ,k-1)*post_vol(j ,k-1) & |
142: +density1(j ,k )*post_vol(j ,k ) & |
143: +density1(j-1,k-1)*post_vol(j-1,k-1) & |
144: +density1(j-1,k )*post_vol(j-1,k )) |
145: node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j-1,k)+node_flux(j,k) |
146: ENDDO |
147: ENDDO |
148: ENDIF |
149: # 149 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90" |
150: !$OMP DO PRIVATE(upwind,downwind,donor,dif,sigma,width,limiter,vdiffuw,vdiffdw,auw,adw,wind,advec_vel_s) |
151: DO k=y_min,y_max+1 |
152: DO j=x_min-1,x_max+1 |
153: IF(node_flux(j,k).LT.0.0)THEN |
154: upwind=j+2 |
155: donor=j+1 |
156: downwind=j |
157: dif=donor |
158: ELSE |
159: upwind=j-1 |
160: donor=j |
161: downwind=j+1 |
162: dif=upwind |
163: ENDIF |
164: sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k)) |
165: width=celldx(j) |
166: vdiffuw=vel1(donor,k)-vel1(upwind,k) |
167: vdiffdw=vel1(downwind,k)-vel1(donor,k) |
168: limiter=0.0 |
169: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
170: auw=ABS(vdiffuw) |
171: adw=ABS(vdiffdw) |
172: wind=1.0_8 |
173: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
174: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw) |
175: ENDIF |
176: advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter |
177: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
178: ENDDO |
179: ENDDO |
180: !$OMP END DO |
181: !$OMP DO |
182: DO k=y_min,y_max+1 |
183: !$OMP SIMD |
184: DO j=x_min,x_max+1 |
185: vel1 (j,k)=(vel1 (j,k)*node_mass_pre(j,k)+mom_flux(j-1,k)-mom_flux(j,k))/node_mass_post(j,k) |
186: ENDDO |
187: ENDDO |
188: !$OMP END DO |
189: ELSEIF(direction.EQ.2)THEN |
190: IF(which_vel.EQ.1)THEN |
191: !$OMP DO |
192: DO k=y_min-2,y_max+2 |
193: !$OMP SIMD |
194: DO j=x_min,x_max+1 |
195: ! Find staggered mesh mass fluxes and nodal masses and volumes. |
196: node_flux(j,k)=0.25_8*(mass_flux_y(j-1,k )+mass_flux_y(j ,k ) & |
197: +mass_flux_y(j-1,k+1)+mass_flux_y(j ,k+1)) |
198: ENDDO |
199: ENDDO |
200: !$OMP END DO |
201: !$OMP DO |
202: DO k=y_min-1,y_max+2 |
203: !$OMP SIMD |
204: DO j=x_min,x_max+1 |
205: node_mass_post(j,k)=0.25_8*(density1(j ,k-1)*post_vol(j ,k-1) & |
206: +density1(j ,k )*post_vol(j ,k ) & |
207: +density1(j-1,k-1)*post_vol(j-1,k-1) & |
208: +density1(j-1,k )*post_vol(j-1,k )) |
209: node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j,k-1)+node_flux(j,k) |
210: ENDDO |
211: ENDDO |
212: ENDIF |
213: !$OMP DO PRIVATE(upwind,donor,downwind,dif,sigma,width,limiter,vdiffuw,vdiffdw,auw,adw,wind,advec_vel_s) |
214: DO k=y_min-1,y_max+1 |
215: DO j=x_min,x_max+1 |
[...] |
227: # 227 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90" |
228: sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor)) |
229: width=celldy(k) |
230: vdiffuw=vel1(j,donor)-vel1(j,upwind) |
231: vdiffdw=vel1(j,downwind)-vel1(j,donor) |
232: limiter=0.0 |
233: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
234: auw=ABS(vdiffuw) |
235: adw=ABS(vdiffdw) |
236: wind=1.0_8 |
237: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
238: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw) |
239: ENDIF |
240: advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter |
241: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
242: ENDDO |
243: ENDDO |
244: !$OMP END DO |
245: !$OMP DO |
246: DO k=y_min,y_max+1 |
247: !$OMP SIMD |
248: DO j=x_min,x_max+1 |
249: vel1 (j,k)=(vel1(j,k)*node_mass_pre(j,k)+mom_flux(j,k-1)-mom_flux(j,k))/node_mass_post(j,k) |
250: ENDDO |
251: ENDDO |
252: !$OMP END DO |
253: ENDIF |
254: # 254 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90" |
0x41d130 SUB SP, SP, #352 |
0x41d134 STP X29, X30, [SP, #256] |
0x41d138 STP X28, X27, [SP, #272] |
0x41d13c STP X26, X25, [SP, #288] |
0x41d140 STP X24, X23, [SP, #304] |
0x41d144 STP X22, X21, [SP, #320] |
0x41d148 STP X20, X19, [SP, #336] |
0x41d14c LDR X8, [X2] |
0x41d150 LDR W29, [X0] |
0x41d154 ORR X20, XZR, X2 |
0x41d158 LDR W8, [X8] |
0x41d15c STR W29, [SP, #60] |
0x41d160 SUB W8, W8, #1 |
0x41d164 CMP W8, #3 |
0x41d168 B.HI 41d988 |
0x41d16c ADRP X9, |
0x41d170 ADD X9, X9, #3420 |
0x41d174 ADR X10, 41d184 |
0x41d178 LDRH W11, [X9, X8,LSL #1] |
0x41d17c ADD X10, X10, X11,LSL #2 |
0x41d180 BR X10 |
0x41d184 LDP X8, X9, [X20, #8] |
0x41d188 ORR X0, XZR, XZR |
0x41d18c ORR W1, WZR, W29 |
0x41d190 ADD X3, SP, #252 |
0x41d194 ADD X4, SP, #248 |
0x41d198 ADD X5, SP, #244 |
0x41d19c STR WZR, [SP, #252] |
0x41d1a0 LDR W8, [X8] |
0x41d1a4 LDR W9, [X9] |
0x41d1a8 ADD X6, SP, #240 |
0x41d1ac MOVZ W2, #34 |
0x41d1b0 MOVZ W7, #1 |
0x41d1b4 ADD W19, W9, #2 |
0x41d1b8 SUB W8, W8, #2 |
0x41d1bc STP W19, W8, [SP, #244] |
0x41d1c0 MOVZ W8, #1 |
0x41d1c4 STR W8, [SP, #240] |
0x41d1c8 STR W8, [SP] |
0x41d1cc BL 404c10 |
0x41d1d0 LDRSW X15, [SP, #248] |
0x41d1d4 CMP W15, W19 |
0x41d1d8 B.GT 41d970 |
0x41d1dc LDR W8, [SP, #244] |
0x41d1e0 SUBS W8, W8, W15 |
0x41d1e4 B.MI 41d970 |
0x41d1e8 LDP X10, X9, [X20, #24] |
0x41d1ec PTRUE P0.D, ALL |
0x41d1f0 ADD W8, W8, #1 |
0x41d1f4 MOVZ X13, #1 |
0x41d1f8 LDR W9, [X9] |
0x41d1fc LDR W10, [X10] |
0x41d200 SUB W12, W9, W10 |
0x41d204 SUB W11, W10, #2 |
0x41d208 SBFM X10, X11, #0, #31 |
0x41d20c ADD W9, W12, #5 |
0x41d210 ADD W11, W12, #4 |
0x41d214 CNTD X12, ALL |
0x41d218 ADD X11, X11, #1 |
0x41d21c B 41d230 |
(504) 0x41d220 ADD X14, X15, #1 |
(504) 0x41d224 ORR X15, XZR, X14 |
(504) 0x41d228 SUBS W8, W8, #1 |
(504) 0x41d22c B.LE 41d970 |
(504) 0x41d230 CMP W9, #0 |
(504) 0x41d234 B.LE 41d220 |
(504) 0x41d238 LDR X14, [X20, #128] |
(504) 0x41d23c LDP X17, X18, [X20, #160] |
(504) 0x41d240 ORR X6, XZR, X10 |
(504) 0x41d244 ORR W7, WZR, W9 |
(504) 0x41d248 LDR X16, [X14] |
(504) 0x41d24c ADD X14, X15, #1 |
(504) 0x41d250 LDR X2, [X17] |
(504) 0x41d254 LDP X17, X1, [X20, #184] |
(504) 0x41d258 CMP X11, X12 |
(504) 0x41d25c MADD X4, X14, X16, XZR |
(504) 0x41d260 MADD X5, X16, X15, XZR |
(504) 0x41d264 LDR X16, [X20, #64] |
(504) 0x41d268 LDR X16, [X16] |
(504) 0x41d26c MADD X16, X16, X15, XZR |
(504) 0x41d270 LDP X15, X3, [X20, #104] |
(504) 0x41d274 LDR X0, [X15] |
(504) 0x41d278 LDR X15, [X20, #40] |
(504) 0x41d27c B.CC 41d324 |
(504) 0x41d280 UDIV X6, X11, X12 |
(504) 0x41d284 ADD X19, X10, X5 |
(504) 0x41d288 ADD X26, X10, X16 |
(504) 0x41d28c ADD X7, X10, X4 |
(504) 0x41d290 ORR X21, XZR, XZR |
(504) 0x41d294 SUB X19, X19, X2 |
(504) 0x41d298 SUB X26, X26, X0 |
(504) 0x41d29c SUB X7, X7, X2 |
(504) 0x41d2a0 UBFM X25, X19, #61, #60 |
(504) 0x41d2a4 UBFM X28, X26, #61, #60 |
(504) 0x41d2a8 ADD X23, X18, X7,LSL #3 |
(504) 0x41d2ac ADD X19, X18, X25 |
(504) 0x41d2b0 ADD X25, X3, X25 |
(504) 0x41d2b4 ADD X26, X1, X28 |
(504) 0x41d2b8 ADD X27, X17, X28 |
(504) 0x41d2bc ADD X28, X15, X28 |
(504) 0x41d2c0 MADD X24, X6, X12, XZR |
(504) 0x41d2c4 SUB X22, X11, X24 |
(504) 0x41d2c8 ADD X6, X24, X10 |
(504) 0x41d2cc SUB W7, W9, W24 |
(504) 0x41d2d0 HINT #0 |
(504) 0x41d2d4 HINT #0 |
(504) 0x41d2d8 HINT #0 |
(504) 0x41d2dc HINT #0 |
(506) 0x41d2e0 LD1D {Z0.D}, P0/Z, [X23, X21,LSL #3] |
(506) 0x41d2e4 LD1D {Z1.D}, P0/Z, [X25, X21,LSL #3] |
(506) 0x41d2e8 ADD X29, X26, X21,LSL #3 |
(506) 0x41d2ec FADD Z0.D, Z0.D, Z1.D |
(506) 0x41d2f0 LD1D {Z1.D}, P0/Z, [X19, X21,LSL #3] |
(506) 0x41d2f4 FSUB Z0.D, Z0.D, Z1.D |
(506) 0x41d2f8 LD1D {Z1.D}, P0/Z, [X29, X13,LSL #3] |
(506) 0x41d2fc ST1D {Z0.D}, P0, [X28, X21,LSL #3] |
(506) 0x41d300 FADD Z0.D, Z0.D, Z1.D |
(506) 0x41d304 LD1D {Z1.D}, P0/Z, [X29, MUL VL] |
(506) 0x41d308 FSUB Z0.D, Z0.D, Z1.D |
(506) 0x41d30c ST1D {Z0.D}, P0, [X27, X21,LSL #3] |
(506) 0x41d310 ADD X21, X21, X12 |
(506) 0x41d314 CMP X24, X21 |
(506) 0x41d318 B.NE 41d2e0 |
(504) 0x41d31c LDR W29, [SP, #60] |
(504) 0x41d320 CBZ X22, 41d224 |
(504) 0x41d324 ADD X16, X6, X16 |
(504) 0x41d328 ADD X4, X6, X4 |
(504) 0x41d32c ADD X5, X6, X5 |
(504) 0x41d330 ORR X21, XZR, XZR |
(504) 0x41d334 SUB X16, X16, X0 |
(504) 0x41d338 SUB X4, X4, X2 |
(504) 0x41d33c UBFM X0, X16, #61, #60 |
(504) 0x41d340 SUB X5, X5, X2 |
(504) 0x41d344 ADD X2, X18, X4,LSL #3 |
(504) 0x41d348 UBFM X4, X5, #61, #60 |
(504) 0x41d34c ADD X16, X1, X0 |
(504) 0x41d350 ADD X18, X18, X4 |
(504) 0x41d354 ADD X3, X3, X4 |
(504) 0x41d358 ADD X17, X17, X0 |
(504) 0x41d35c ADD W4, W7, #1 |
(504) 0x41d360 ADD X16, X16, #8 |
(504) 0x41d364 ADD X15, X15, X0 |
(505) 0x41d368 LDR D0, [X2, X21] |
(505) 0x41d36c LDR D1, [X3, X21] |
(505) 0x41d370 ADD X0, X16, X21 |
(505) 0x41d374 SUB W4, W4, #1 |
(505) 0x41d378 CMP W4, #1 |
(505) 0x41d37c FADD D0, D0, D1 |
(505) 0x41d380 LDR D1, [X18, X21] |
(505) 0x41d384 FSUB D0, D0, S1 |
(505) 0x41d388 LDR D1, [X0] |
(505) 0x41d38c STR D0, [X15, X21] |
(505) 0x41d390 FADD D0, D0, D1 |
(505) 0x41d394 LDUR D1, [X0, #504] |
(505) 0x41d398 FSUB D0, D0, S1 |
(505) 0x41d39c STR D0, [X17, X21] |
(505) 0x41d3a0 ADD X21, X21, #8 |
(505) 0x41d3a4 B.HI 41d368 |
(504) 0x41d3a8 B 41d224 |
0x41d3ac LDP X8, X9, [X20, #8] |
0x41d3b0 ORR X0, XZR, XZR |
0x41d3b4 ORR W1, WZR, W29 |
0x41d3b8 ADD X3, SP, #236 |
0x41d3bc ADD X4, SP, #232 |
0x41d3c0 ADD X5, SP, #228 |
0x41d3c4 STR WZR, [SP, #236] |
0x41d3c8 LDR W8, [X8] |
0x41d3cc LDR W9, [X9] |
0x41d3d0 ADD X6, SP, #224 |
0x41d3d4 MOVZ W2, #34 |
0x41d3d8 MOVZ W7, #1 |
0x41d3dc ADD W19, W9, #2 |
0x41d3e0 SUB W8, W8, #2 |
0x41d3e4 STP W19, W8, [SP, #228] |
0x41d3e8 MOVZ W8, #1 |
0x41d3ec STR W8, [SP, #224] |
0x41d3f0 STR W8, [SP] |
0x41d3f4 BL 404c10 |
0x41d3f8 LDRSW X8, [SP, #232] |
0x41d3fc CMP W8, W19 |
0x41d400 B.GT 41d970 |
0x41d404 LDR W9, [SP, #228] |
0x41d408 SUBS W9, W9, W8 |
0x41d40c B.MI 41d970 |
0x41d410 LDP X11, X10, [X20, #24] |
0x41d414 PTRUE P0.D, ALL |
0x41d418 ADD W9, W9, #1 |
0x41d41c MOVZ X14, #1 |
0x41d420 LDR W10, [X10] |
0x41d424 LDR W11, [X11] |
0x41d428 SUB W13, W10, W11 |
0x41d42c SUB W12, W11, #2 |
0x41d430 SBFM X11, X12, #0, #31 |
0x41d434 ADD W10, W13, #5 |
0x41d438 ADD W12, W13, #4 |
0x41d43c CNTD X13, ALL |
0x41d440 ADD X12, X12, #1 |
0x41d444 B 41d454 |
(501) 0x41d448 ADD X8, X8, #1 |
(501) 0x41d44c SUBS W9, W9, #1 |
(501) 0x41d450 B.LE 41d970 |
(501) 0x41d454 CMP W10, #0 |
(501) 0x41d458 B.LE 41d448 |
(501) 0x41d45c LDR X15, [X20, #64] |
(501) 0x41d460 LDR X4, [X20, #40] |
(501) 0x41d464 LDP X5, X3, [X20, #184] |
(501) 0x41d468 ORR X6, XZR, X11 |
(501) 0x41d46c ORR W21, WZR, W10 |
(501) 0x41d470 CMP X12, X13 |
(501) 0x41d474 LDR X15, [X15] |
(501) 0x41d478 MADD X18, X15, X8, XZR |
(501) 0x41d47c LDP X16, X15, [X20, #104] |
(501) 0x41d480 LDR X2, [X16] |
(501) 0x41d484 LDR X16, [X20, #128] |
(501) 0x41d488 LDR X0, [X16] |
(501) 0x41d48c LDP X17, X16, [X20, #160] |
(501) 0x41d490 LDR X17, [X17] |
(501) 0x41d494 MADD X1, X0, X8, XZR |
(501) 0x41d498 ADD X8, X8, #1 |
(501) 0x41d49c MADD X0, X8, X0, XZR |
(501) 0x41d4a0 B.CC 41d544 |
(501) 0x41d4a4 UDIV X6, X12, X13 |
(501) 0x41d4a8 ADD X19, X11, X18 |
(501) 0x41d4ac ADD X26, X11, X1 |
(501) 0x41d4b0 ADD X28, X11, X0 |
(501) 0x41d4b4 ORR X7, XZR, XZR |
(501) 0x41d4b8 SUB X19, X19, X2 |
(501) 0x41d4bc SUB X26, X26, X17 |
(501) 0x41d4c0 SUB X28, X28, X17 |
(501) 0x41d4c4 UBFM X19, X19, #61, #60 |
(501) 0x41d4c8 UBFM X27, X26, #61, #60 |
(501) 0x41d4cc ADD X28, X16, X28,LSL #3 |
(501) 0x41d4d0 ADD X23, X3, X19 |
(501) 0x41d4d4 ADD X25, X5, X19 |
(501) 0x41d4d8 ADD X19, X4, X19 |
(501) 0x41d4dc ADD X26, X16, X27 |
(501) 0x41d4e0 ADD X27, X15, X27 |
(501) 0x41d4e4 MADD X24, X6, X13, XZR |
(501) 0x41d4e8 SUB X22, X12, X24 |
(501) 0x41d4ec ADD X6, X24, X11 |
(501) 0x41d4f0 SUB W21, W10, W24 |
(501) 0x41d4f4 HINT #0 |
(501) 0x41d4f8 HINT #0 |
(501) 0x41d4fc HINT #0 |
(503) 0x41d500 ADD X29, X23, X7,LSL #3 |
(503) 0x41d504 LD1D {Z1.D}, P0/Z, [X27, X7,LSL #3] |
(503) 0x41d508 LD1D {Z0.D}, P0/Z, [X29, X14,LSL #3] |
(503) 0x41d50c FADD Z0.D, Z0.D, Z1.D |
(503) 0x41d510 LD1D {Z1.D}, P0/Z, [X29, MUL VL] |
(503) 0x41d514 FSUB Z0.D, Z0.D, Z1.D |
(503) 0x41d518 LD1D {Z1.D}, P0/Z, [X28, X7,LSL #3] |
(503) 0x41d51c ST1D {Z0.D}, P0, [X19, X7,LSL #3] |
(503) 0x41d520 FADD Z0.D, Z0.D, Z1.D |
(503) 0x41d524 LD1D {Z1.D}, P0/Z, [X26, X7,LSL #3] |
(503) 0x41d528 FSUB Z0.D, Z0.D, Z1.D |
(503) 0x41d52c ST1D {Z0.D}, P0, [X25, X7,LSL #3] |
(503) 0x41d530 ADD X7, X7, X13 |
(503) 0x41d534 CMP X24, X7 |
(503) 0x41d538 B.NE 41d500 |
(501) 0x41d53c LDR W29, [SP, #60] |
(501) 0x41d540 CBZ X22, 41d44c |
(501) 0x41d544 ADD X18, X6, X18 |
(501) 0x41d548 ADD X1, X6, X1 |
(501) 0x41d54c ADD X0, X6, X0 |
(501) 0x41d550 ORR X7, XZR, XZR |
(501) 0x41d554 SUB X2, X18, X2 |
(501) 0x41d558 SUB X1, X1, X17 |
(501) 0x41d55c ADD W18, W21, #1 |
(501) 0x41d560 UBFM X19, X2, #61, #60 |
(501) 0x41d564 SUB X17, X0, X17 |
(501) 0x41d568 ADD X2, X5, X19 |
(501) 0x41d56c ADD X3, X3, X19 |
(501) 0x41d570 UBFM X5, X1, #61, #60 |
(501) 0x41d574 ADD X4, X4, X19 |
(501) 0x41d578 ADD X1, X16, X5 |
(501) 0x41d57c ADD X15, X15, X5 |
(501) 0x41d580 ADD X16, X16, X17,LSL #3 |
(501) 0x41d584 ADD X3, X3, #8 |
(502) 0x41d588 ADD X17, X3, X7 |
(502) 0x41d58c LDR D1, [X15, X7] |
(502) 0x41d590 SUB W18, W18, #1 |
(502) 0x41d594 CMP W18, #1 |
(502) 0x41d598 LDR D0, [X17] |
(502) 0x41d59c FADD D0, D0, D1 |
(502) 0x41d5a0 LDUR D1, [X17, #504] |
(502) 0x41d5a4 FSUB D0, D0, S1 |
(502) 0x41d5a8 LDR D1, [X16, X7] |
(502) 0x41d5ac STR D0, [X4, X7] |
(502) 0x41d5b0 FADD D0, D0, D1 |
(502) 0x41d5b4 LDR D1, [X1, X7] |
(502) 0x41d5b8 FSUB D0, D0, S1 |
(502) 0x41d5bc STR D0, [X2, X7] |
(502) 0x41d5c0 ADD X7, X7, #8 |
(502) 0x41d5c4 B.HI 41d588 |
(501) 0x41d5c8 B 41d44c |
0x41d5cc LDP X8, X9, [X20, #8] |
0x41d5d0 ORR X0, XZR, XZR |
0x41d5d4 ORR W1, WZR, W29 |
0x41d5d8 ADD X3, SP, #220 |
0x41d5dc ADD X4, SP, #216 |
0x41d5e0 ADD X5, SP, #212 |
0x41d5e4 STR WZR, [SP, #220] |
0x41d5e8 LDR W8, [X8] |
0x41d5ec LDR W9, [X9] |
0x41d5f0 ADD X6, SP, #208 |
0x41d5f4 MOVZ W2, #34 |
0x41d5f8 MOVZ W7, #1 |
0x41d5fc ADD W19, W9, #2 |
0x41d600 SUB W8, W8, #2 |
0x41d604 STP W19, W8, [SP, #212] |
0x41d608 MOVZ W8, #1 |
0x41d60c STR W8, [SP, #208] |
0x41d610 STR W8, [SP] |
0x41d614 BL 404c10 |
0x41d618 LDRSW X8, [SP, #216] |
0x41d61c CMP W8, W19 |
0x41d620 B.GT 41d970 |
0x41d624 LDR W9, [SP, #212] |
0x41d628 SUBS W9, W9, W8 |
0x41d62c B.MI 41d970 |
0x41d630 LDP X11, X10, [X20, #24] |
0x41d634 PTRUE P0.D, ALL |
0x41d638 ADD W9, W9, #1 |
0x41d63c LDR W10, [X10] |
0x41d640 LDR W11, [X11] |
0x41d644 SUB W13, W10, W11 |
0x41d648 SUB W12, W11, #2 |
0x41d64c SBFM X11, X12, #0, #31 |
0x41d650 ADD W10, W13, #5 |
0x41d654 ADD W12, W13, #4 |
0x41d658 CNTD X13, ALL |
0x41d65c ADD X12, X12, #1 |
0x41d660 B 41d670 |
(498) 0x41d664 ADD X8, X8, #1 |
(498) 0x41d668 SUBS W9, W9, #1 |
(498) 0x41d66c B.LE 41d970 |
(498) 0x41d670 CMP W10, #0 |
(498) 0x41d674 B.LE 41d664 |
(498) 0x41d678 LDR X18, [X20, #64] |
(498) 0x41d67c LDR X14, [X20, #128] |
(498) 0x41d680 LDR X2, [X20, #184] |
(498) 0x41d684 ORR X5, XZR, X11 |
(498) 0x41d688 ORR W4, WZR, W10 |
(498) 0x41d68c CMP X12, X13 |
(498) 0x41d690 LDR X18, [X18] |
(498) 0x41d694 LDR X17, [X14] |
(498) 0x41d698 LDP X15, X14, [X20, #160] |
(498) 0x41d69c MADD X0, X18, X8, XZR |
(498) 0x41d6a0 LDP X18, X3, [X20, #104] |
(498) 0x41d6a4 LDR X15, [X15] |
(498) 0x41d6a8 MADD X16, X17, X8, XZR |
(498) 0x41d6ac ADD X8, X8, #1 |
(498) 0x41d6b0 MADD X17, X8, X17, XZR |
(498) 0x41d6b4 LDR X1, [X18] |
(498) 0x41d6b8 LDR X18, [X20, #40] |
(498) 0x41d6bc B.CC 41d738 |
(498) 0x41d6c0 UDIV X4, X12, X13 |
(498) 0x41d6c4 ADD X5, X11, X16 |
(498) 0x41d6c8 ADD X23, X11, X0 |
(498) 0x41d6cc ADD X25, X11, X17 |
(498) 0x41d6d0 ORR X6, XZR, XZR |
(498) 0x41d6d4 SUB X5, X5, X15 |
(498) 0x41d6d8 SUB X23, X23, X1 |
(498) 0x41d6dc SUB X25, X25, X15 |
(498) 0x41d6e0 UBFM X22, X5, #61, #60 |
(498) 0x41d6e4 UBFM X24, X23, #61, #60 |
(498) 0x41d6e8 ADD X25, X14, X25,LSL #3 |
(498) 0x41d6ec ADD X21, X14, X22 |
(498) 0x41d6f0 ADD X22, X3, X22 |
(498) 0x41d6f4 ADD X23, X2, X24 |
(498) 0x41d6f8 ADD X24, X18, X24 |
(498) 0x41d6fc MADD X19, X4, X13, XZR |
(498) 0x41d700 SUB X7, X12, X19 |
(498) 0x41d704 ADD X5, X19, X11 |
(498) 0x41d708 SUB W4, W10, W19 |
(500) 0x41d70c LD1D {Z0.D}, P0/Z, [X22, X6,LSL #3] |
(500) 0x41d710 LD1D {Z1.D}, P0/Z, [X25, X6,LSL #3] |
(500) 0x41d714 ST1D {Z0.D}, P0, [X24, X6,LSL #3] |
(500) 0x41d718 FADD Z0.D, Z0.D, Z1.D |
(500) 0x41d71c LD1D {Z1.D}, P0/Z, [X21, X6,LSL #3] |
(500) 0x41d720 FSUB Z0.D, Z0.D, Z1.D |
(500) 0x41d724 ST1D {Z0.D}, P0, [X23, X6,LSL #3] |
(500) 0x41d728 ADD X6, X6, X13 |
(500) 0x41d72c CMP X19, X6 |
(500) 0x41d730 B.NE 41d70c |
(498) 0x41d734 CBZ X7, 41d668 |
(498) 0x41d738 ADD X16, X5, X16 |
(498) 0x41d73c ADD X0, X5, X0 |
(498) 0x41d740 ADD X17, X5, X17 |
(498) 0x41d744 ORR X6, XZR, XZR |
(498) 0x41d748 SUB X16, X16, X15 |
(498) 0x41d74c SUB X0, X0, X1 |
(498) 0x41d750 UBFM X7, X16, #61, #60 |
(498) 0x41d754 SUB X15, X17, X15 |
(498) 0x41d758 UBFM X1, X0, #61, #60 |
(498) 0x41d75c ADD X16, X14, X7 |
(498) 0x41d760 ADD X3, X3, X7 |
(498) 0x41d764 ADD X0, X2, X1 |
(498) 0x41d768 ADD X18, X18, X1 |
(498) 0x41d76c ADD X14, X14, X15,LSL #3 |
(498) 0x41d770 ADD W15, W4, #1 |
(498) 0x41d774 HINT #0 |
(498) 0x41d778 HINT #0 |
(498) 0x41d77c HINT #0 |
(499) 0x41d780 LDR D0, [X3, X6] |
(499) 0x41d784 LDR D1, [X14, X6] |
(499) 0x41d788 SUB W15, W15, #1 |
(499) 0x41d78c CMP W15, #1 |
(499) 0x41d790 STR D0, [X18, X6] |
(499) 0x41d794 FADD D0, D0, D1 |
(499) 0x41d798 LDR D1, [X16, X6] |
(499) 0x41d79c FSUB D0, D0, S1 |
(499) 0x41d7a0 STR D0, [X0, X6] |
(499) 0x41d7a4 ADD X6, X6, #8 |
(499) 0x41d7a8 B.HI 41d780 |
(498) 0x41d7ac B 41d668 |
0x41d7b0 LDP X8, X9, [X20, #8] |
0x41d7b4 ORR X0, XZR, XZR |
0x41d7b8 ORR W1, WZR, W29 |
0x41d7bc ADD X3, SP, #204 |
0x41d7c0 ADD X4, SP, #200 |
0x41d7c4 ADD X5, SP, #196 |
0x41d7c8 STR WZR, [SP, #204] |
0x41d7cc LDR W8, [X8] |
0x41d7d0 LDR W9, [X9] |
0x41d7d4 ADD X6, SP, #192 |
0x41d7d8 MOVZ W2, #34 |
0x41d7dc MOVZ W7, #1 |
0x41d7e0 ADD W19, W9, #2 |
0x41d7e4 SUB W8, W8, #2 |
0x41d7e8 STP W19, W8, [SP, #196] |
0x41d7ec MOVZ W8, #1 |
0x41d7f0 STR W8, [SP, #192] |
0x41d7f4 STR W8, [SP] |
0x41d7f8 BL 404c10 |
0x41d7fc LDRSW X8, [SP, #200] |
0x41d800 CMP W8, W19 |
0x41d804 B.GT 41d970 |
0x41d808 LDR W9, [SP, #196] |
0x41d80c SUBS W9, W9, W8 |
0x41d810 B.MI 41d970 |
0x41d814 LDP X11, X10, [X20, #24] |
0x41d818 PTRUE P0.D, ALL |
0x41d81c ADD W9, W9, #1 |
0x41d820 MOVZ X14, #1 |
0x41d824 LDR W10, [X10] |
0x41d828 LDR W11, [X11] |
0x41d82c SUB W13, W10, W11 |
0x41d830 SUB W12, W11, #2 |
0x41d834 SBFM X11, X12, #0, #31 |
0x41d838 ADD W10, W13, #5 |
0x41d83c ADD W12, W13, #4 |
0x41d840 CNTD X13, ALL |
0x41d844 ADD X12, X12, #1 |
0x41d848 B 41d858 |
(495) 0x41d84c ADD X8, X8, #1 |
(495) 0x41d850 SUBS W9, W9, #1 |
(495) 0x41d854 B.LE 41d970 |
(495) 0x41d858 CMP W10, #1 |
(495) 0x41d85c B.LT 41d84c |
(495) 0x41d860 LDR X15, [X20, #128] |
(495) 0x41d864 LDP X16, X1, [X20, #184] |
(495) 0x41d868 ORR X4, XZR, X11 |
(495) 0x41d86c ORR W5, WZR, W10 |
(495) 0x41d870 LDR X18, [X15] |
(495) 0x41d874 LDR X15, [X20, #160] |
(495) 0x41d878 CMP X12, X13 |
(495) 0x41d87c LDR X2, [X15] |
(495) 0x41d880 LDR X15, [X20, #64] |
(495) 0x41d884 LDR X17, [X15] |
(495) 0x41d888 LDP X15, X3, [X20, #104] |
(495) 0x41d88c LDR X0, [X15] |
(495) 0x41d890 LDR X15, [X20, #40] |
(495) 0x41d894 B.CC 41d910 |
(495) 0x41d898 UDIV X4, X12, X13 |
(495) 0x41d89c MADD X22, X17, X8, X11 |
(495) 0x41d8a0 MADD X19, X18, X8, X11 |
(495) 0x41d8a4 ORR X7, XZR, XZR |
(495) 0x41d8a8 SUB X22, X22, X0 |
(495) 0x41d8ac SUB X19, X19, X2 |
(495) 0x41d8b0 UBFM X24, X22, #61, #60 |
(495) 0x41d8b4 ADD X19, X3, X19,LSL #3 |
(495) 0x41d8b8 ADD X22, X1, X24 |
(495) 0x41d8bc ADD X23, X16, X24 |
(495) 0x41d8c0 ADD X24, X15, X24 |
(495) 0x41d8c4 MADD X21, X4, X13, XZR |
(495) 0x41d8c8 SUB X6, X12, X21 |
(495) 0x41d8cc ADD X4, X21, X11 |
(495) 0x41d8d0 SUB W5, W10, W21 |
(495) 0x41d8d4 HINT #0 |
(495) 0x41d8d8 HINT #0 |
(495) 0x41d8dc HINT #0 |
(497) 0x41d8e0 ADD X25, X22, X7,LSL #3 |
(497) 0x41d8e4 LD1D {Z0.D}, P0/Z, [X19, X7,LSL #3] |
(497) 0x41d8e8 LD1D {Z1.D}, P0/Z, [X25, X14,LSL #3] |
(497) 0x41d8ec ST1D {Z0.D}, P0, [X24, X7,LSL #3] |
(497) 0x41d8f0 FADD Z0.D, Z0.D, Z1.D |
(497) 0x41d8f4 LD1D {Z1.D}, P0/Z, [X25, MUL VL] |
(497) 0x41d8f8 FSUB Z0.D, Z0.D, Z1.D |
(497) 0x41d8fc ST1D {Z0.D}, P0, [X23, X7,LSL #3] |
(497) 0x41d900 ADD X7, X7, X13 |
(497) 0x41d904 CMP X21, X7 |
(497) 0x41d908 B.NE 41d8e0 |
(495) 0x41d90c CBZ X6, 41d84c |
(495) 0x41d910 MADD X17, X17, X8, X4 |
(495) 0x41d914 MADD X18, X18, X8, X4 |
(495) 0x41d918 SUB X17, X17, X0 |
(495) 0x41d91c SUB X18, X18, X2 |
(495) 0x41d920 ADD W2, W5, #1 |
(495) 0x41d924 UBFM X0, X17, #61, #60 |
(495) 0x41d928 ADD X18, X3, X18,LSL #3 |
(495) 0x41d92c ADD X17, X1, X0 |
(495) 0x41d930 ADD X16, X16, X0 |
(495) 0x41d934 ADD X15, X15, X0 |
(495) 0x41d938 ADD X17, X17, #8 |
(495) 0x41d93c HINT #0 |
(496) 0x41d940 LDR D1, [X17] |
(496) 0x41d944 LDR D0, [X18], #8 |
(496) 0x41d948 SUB W2, W2, #1 |
(496) 0x41d94c STR D0, [X15], #8 |
(496) 0x41d950 CMP W2, #1 |
(496) 0x41d954 FADD D0, D0, D1 |
(496) 0x41d958 LDUR D1, [X17, #504] |
(496) 0x41d95c ADD X17, X17, #8 |
(496) 0x41d960 FSUB D0, D0, S1 |
(496) 0x41d964 STR D0, [X16], #8 |
(496) 0x41d968 B.HI 41d940 |
(495) 0x41d96c B 41d84c |
0x41d970 ORR X0, XZR, XZR |
0x41d974 ORR W1, WZR, W29 |
0x41d978 BL 404d30 |
0x41d97c ORR X0, XZR, XZR |
0x41d980 ORR W1, WZR, W29 |
0x41d984 BL 404900 |
0x41d988 LDR X8, [X20, #208] |
0x41d98c LDR W8, [X8] |
0x41d990 CMP W8, #2 |
0x41d994 B.EQ 41db6c |
0x41d998 CMP W8, #1 |
0x41d99c B.NE 41ead8 |
0x41d9a0 LDR X8, [X20, #216] |
0x41d9a4 LDR W8, [X8] |
0x41d9a8 CMP W8, #1 |
0x41d9ac B.NE 41e2c8 |
0x41d9b0 LDP X8, X9, [X20, #8] |
0x41d9b4 ORR X0, XZR, XZR |
0x41d9b8 ORR W1, WZR, W29 |
0x41d9bc MOVZ W21, #1 |
0x41d9c0 ADD X3, SP, #188 |
0x41d9c4 ADD X4, SP, #184 |
0x41d9c8 STR WZR, [SP, #188] |
0x41d9cc LDR W9, [X9] |
0x41d9d0 LDR W8, [X8] |
0x41d9d4 ADD X5, SP, #180 |
0x41d9d8 ADD X6, SP, #176 |
0x41d9dc MOVZ W2, #34 |
0x41d9e0 MOVZ W7, #1 |
0x41d9e4 STR W21, [SP, #176] |
0x41d9e8 STR W21, [SP] |
0x41d9ec ADD W19, W9, #1 |
0x41d9f0 STP W19, W8, [SP, #180] |
0x41d9f4 BL 404c10 |
0x41d9f8 LDRSW X8, [SP, #184] |
0x41d9fc CMP W8, W19 |
0x41da00 B.GT 41dd5c |
0x41da04 LDR W9, [SP, #180] |
0x41da08 SUBS W9, W9, W8 |
0x41da0c B.MI 41dd5c |
0x41da10 LDP X11, X10, [X20, #24] |
0x41da14 CNTD X14, ALL |
0x41da18 FMOV D0, #0.2500000 |
0x41da1c PTRUE P0.D, ALL |
0x41da20 FDUP Z1.D, #80 |
0x41da24 ADD W9, W9, #1 |
0x41da28 MOVZ X15, #1 |
0x41da2c LDR W10, [X10] |
0x41da30 LDR W11, [X11] |
0x41da34 SUB W13, W10, W11 |
0x41da38 SUB W12, W11, #2 |
0x41da3c SBFM X11, X12, #0, #31 |
0x41da40 ADD W12, W13, #4 |
0x41da44 ADD W10, W13, #5 |
0x41da48 SUB X13, X8, #1 |
0x41da4c ADD X12, X12, #1 |
0x41da50 B 41da70 |
0x41da54 HINT #0 |
0x41da58 HINT #0 |
0x41da5c HINT #0 |
(492) 0x41da60 ADD X8, X8, #1 |
(492) 0x41da64 SUBS W9, W9, #1 |
(492) 0x41da68 ADD X13, X13, #1 |
(492) 0x41da6c B.LE 41dd5c |
(492) 0x41da70 CMP W10, #1 |
(492) 0x41da74 B.LT 41da60 |
(492) 0x41da78 LDR X16, [X20, #64] |
(492) 0x41da7c LDR X17, [X20, #104] |
(492) 0x41da80 LDP X0, X18, [X20, #224] |
(492) 0x41da84 ORR X1, XZR, X11 |
(492) 0x41da88 ORR W2, WZR, W10 |
(492) 0x41da8c CMP X12, X14 |
(492) 0x41da90 LDR X16, [X16] |
(492) 0x41da94 LDR X17, [X17] |
(492) 0x41da98 B.CC 41db20 |
(492) 0x41da9c UDIV X1, X12, X14 |
(492) 0x41daa0 MADD X6, X16, X8, X11 |
(492) 0x41daa4 MADD X19, X16, X13, X11 |
(492) 0x41daa8 ORR X4, XZR, XZR |
(492) 0x41daac SUB X6, X6, X17 |
(492) 0x41dab0 SUB X19, X19, X17 |
(492) 0x41dab4 UBFM X7, X6, #61, #60 |
(492) 0x41dab8 ADD X19, X18, X19,LSL #3 |
(492) 0x41dabc ADD X6, X18, X7 |
(492) 0x41dac0 ADD X7, X0, X7 |
(492) 0x41dac4 MADD X5, X1, X14, XZR |
(492) 0x41dac8 SUB X3, X12, X5 |
(492) 0x41dacc ADD X1, X5, X11 |
(492) 0x41dad0 SUB W2, W10, W5 |
(492) 0x41dad4 HINT #0 |
(492) 0x41dad8 HINT #0 |
(492) 0x41dadc HINT #0 |
(494) 0x41dae0 UBFM X22, X4, #61, #60 |
(494) 0x41dae4 ADD X23, X6, X22 |
(494) 0x41dae8 ADD X22, X19, X22 |
(494) 0x41daec LD1D {Z2.D}, P0/Z, [X23, X15,LSL #3] |
(494) 0x41daf0 LD1D {Z3.D}, P0/Z, [X22, X15,LSL #3] |
(494) 0x41daf4 FADD Z2.D, Z2.D, Z3.D |
(494) 0x41daf8 LD1D {Z3.D}, P0/Z, [X23, MUL VL] |
(494) 0x41dafc LD1D {Z4.D}, P0/Z, [X22, MUL VL] |
(494) 0x41db00 FADD Z3.D, Z3.D, Z4.D |
(494) 0x41db04 FADD Z2.D, Z2.D, Z3.D |
(494) 0x41db08 FMUL Z2.D, Z2.D, Z1.D |
(494) 0x41db0c ST1D {Z2.D}, P0, [X7, X4,LSL #3] |
(494) 0x41db10 ADD X4, X4, X14 |
(494) 0x41db14 CMP X5, X4 |
(494) 0x41db18 B.NE 41dae0 |
(492) 0x41db1c CBZ X3, 41da60 |
(492) 0x41db20 MADD X3, X16, X8, X1 |
(492) 0x41db24 MADD X16, X16, X13, X1 |
(492) 0x41db28 SUB X3, X3, X17 |
(492) 0x41db2c SUB X16, X16, X17 |
(492) 0x41db30 ADD W17, W2, #1 |
(492) 0x41db34 UBFM X4, X3, #61, #60 |
(492) 0x41db38 ADD X16, X18, X16,LSL #3 |
(492) 0x41db3c ADD X3, X18, X4 |
(492) 0x41db40 ADD X0, X0, X4 |
(493) 0x41db44 LDR Q2, [X3], #8 |
(493) 0x41db48 LDR Q3, [X16], #8 |
(493) 0x41db4c FADD V2.2D, V2.2D, V3.2D |
(493) 0x41db50 SUB W17, W17, #1 |
(493) 0x41db54 CMP W17, #1 |
(493) 0x41db58 FADDP D2, V2.2D |
(493) 0x41db5c FMUL D2, D2, D0 |
(493) 0x41db60 STR D2, [X0], #8 |
(493) 0x41db64 B.HI 41db44 |
(492) 0x41db68 B 41da60 |
0x41db6c LDR X8, [X20, #216] |
0x41db70 LDR W8, [X8] |
0x41db74 CMP W8, #1 |
0x41db78 B.NE 41e6cc |
0x41db7c LDP X8, X9, [X20, #8] |
0x41db80 ORR X0, XZR, XZR |
0x41db84 ORR W1, WZR, W29 |
0x41db88 MOVZ W21, #1 |
0x41db8c ADD X3, SP, #124 |
0x41db90 ADD X4, SP, #120 |
0x41db94 STR WZR, [SP, #124] |
0x41db98 LDR W8, [X8] |
0x41db9c LDR W9, [X9] |
0x41dba0 ADD X5, SP, #116 |
0x41dba4 ADD X6, SP, #112 |
0x41dba8 MOVZ W2, #34 |
0x41dbac MOVZ W7, #1 |
0x41dbb0 STR W21, [SP, #112] |
0x41dbb4 STR W21, [SP] |
0x41dbb8 ADD W19, W9, #2 |
0x41dbbc SUB W8, W8, #2 |
0x41dbc0 STP W19, W8, [SP, #116] |
0x41dbc4 BL 404c10 |
0x41dbc8 LDRSW X0, [SP, #120] |
0x41dbcc CMP W0, W19 |
0x41dbd0 B.GT 41e00c |
0x41dbd4 LDR W8, [SP, #116] |
0x41dbd8 SUBS W8, W8, W0 |
0x41dbdc B.MI 41e00c |
0x41dbe0 LDP X10, X9, [X20, #24] |
0x41dbe4 CNTD X12, ALL |
0x41dbe8 FMOV D0, #0.2500000 |
0x41dbec PTRUE P0.D, ALL |
0x41dbf0 FDUP Z1.D, #80 |
0x41dbf4 ADD W8, W8, #1 |
0x41dbf8 MOVN X13, #0 |
0x41dbfc LDR W11, [X9] |
0x41dc00 LDRSW X9, [X10] |
0x41dc04 SUB W11, W11, W9 |
0x41dc08 ADD W10, W11, #2 |
0x41dc0c ADD W11, W11, #1 |
0x41dc10 ADD X11, X11, #1 |
0x41dc14 B 41dc30 |
0x41dc18 HINT #0 |
0x41dc1c HINT #0 |
(488) 0x41dc20 ADD X14, X0, #1 |
(490) 0x41dc24 ORR X0, XZR, X14 |
(490) 0x41dc28 SUBS W8, W8, #1 |
(490) 0x41dc2c B.LE 41e00c |
(490) 0x41dc30 CMP W10, #0 |
(490) 0x41dc34 B.LE 41dc20 |
(490) 0x41dc38 LDR X14, [X20, #128] |
(490) 0x41dc3c LDR X1, [X20, #64] |
(490) 0x41dc40 LDR X15, [X20, #160] |
(490) 0x41dc44 ORR X3, XZR, X9 |
(490) 0x41dc48 ORR W4, WZR, W10 |
(490) 0x41dc4c CMP X11, X12 |
(490) 0x41dc50 LDR X16, [X20, #304] |
(490) 0x41dc54 LDR X2, [X20, #224] |
(490) 0x41dc58 LDR X17, [X14] |
(490) 0x41dc5c LDR X1, [X1] |
(490) 0x41dc60 ADD X14, X0, #1 |
(490) 0x41dc64 LDR X15, [X15] |
(490) 0x41dc68 MADD X18, X14, X17, XZR |
(490) 0x41dc6c MADD X17, X17, X0, XZR |
(490) 0x41dc70 MADD X0, X1, X0, XZR |
(490) 0x41dc74 LDR X1, [X20, #104] |
(490) 0x41dc78 LDR X1, [X1] |
(490) 0x41dc7c B.CC 41dd00 |
(490) 0x41dc80 UDIV X3, X11, X12 |
(490) 0x41dc84 ADD X19, X9, X18 |
(490) 0x41dc88 ADD X22, X9, X17 |
(490) 0x41dc8c ADD X23, X9, X0 |
(490) 0x41dc90 ORR X6, XZR, XZR |
(490) 0x41dc94 SUB X19, X19, X15 |
(490) 0x41dc98 SUB X22, X22, X15 |
(490) 0x41dc9c SUB X23, X23, X1 |
(490) 0x41dca0 ADD X19, X16, X19,LSL #3 |
(490) 0x41dca4 ADD X22, X16, X22,LSL #3 |
(490) 0x41dca8 ADD X23, X2, X23,LSL #3 |
(490) 0x41dcac MADD X7, X3, X12, XZR |
(490) 0x41dcb0 SUB X5, X11, X7 |
(490) 0x41dcb4 ADD X3, X7, X9 |
(490) 0x41dcb8 SUB W4, W10, W7 |
(490) 0x41dcbc HINT #0 |
(491) 0x41dcc0 UBFM X24, X6, #61, #60 |
(491) 0x41dcc4 ADD X25, X19, X24 |
(491) 0x41dcc8 ADD X24, X22, X24 |
(491) 0x41dccc LD1D {Z2.D}, P0/Z, [X25, MUL VL] |
(491) 0x41dcd0 LD1D {Z3.D}, P0/Z, [X25, X13,LSL #3] |
(491) 0x41dcd4 FADD Z2.D, Z2.D, Z3.D |
(491) 0x41dcd8 LD1D {Z3.D}, P0/Z, [X24, MUL VL] |
(491) 0x41dcdc LD1D {Z4.D}, P0/Z, [X24, X13,LSL #3] |
(491) 0x41dce0 FADD Z3.D, Z3.D, Z4.D |
(491) 0x41dce4 FADD Z2.D, Z2.D, Z3.D |
(491) 0x41dce8 FMUL Z2.D, Z2.D, Z1.D |
(491) 0x41dcec ST1D {Z2.D}, P0, [X23, X6,LSL #3] |
(491) 0x41dcf0 ADD X6, X6, X12 |
(491) 0x41dcf4 CMP X7, X6 |
(491) 0x41dcf8 B.NE 41dcc0 |
(490) 0x41dcfc CBZ X5, 41dc24 |
(490) 0x41dd00 ADD X18, X3, X18 |
(490) 0x41dd04 ADD X0, X3, X0 |
(490) 0x41dd08 ADD W4, W4, #1 |
(490) 0x41dd0c ADD X17, X3, X17 |
(490) 0x41dd10 SUB X18, X18, X15 |
(490) 0x41dd14 SUB X0, X0, X1 |
(490) 0x41dd18 SUB X15, X17, X15 |
(490) 0x41dd1c ADD X18, X16, X18,LSL #3 |
(490) 0x41dd20 ADD X0, X2, X0,LSL #3 |
(490) 0x41dd24 ADD X15, X16, X15,LSL #3 |
(489) 0x41dd28 LDP D3, D2, [X18, #1016] |
(489) 0x41dd2c SUB W4, W4, #1 |
(489) 0x41dd30 ADD X18, X18, #8 |
(489) 0x41dd34 CMP W4, #1 |
(489) 0x41dd38 FADD D2, D2, D3 |
(489) 0x41dd3c LDP D4, D3, [X15, #1016] |
(489) 0x41dd40 ADD X15, X15, #8 |
(489) 0x41dd44 FADD D3, D3, D4 |
(489) 0x41dd48 FADD D2, D2, D3 |
(489) 0x41dd4c FMUL D2, D2, D0 |
(489) 0x41dd50 STR D2, [X0], #8 |
(489) 0x41dd54 B.HI 41dd28 |
(490) 0x41dd58 B 41dc24 |
0x41dd5c ORR X0, XZR, XZR |
0x41dd60 ORR W1, WZR, W29 |
0x41dd64 BL 404d30 |
0x41dd68 ORR X0, XZR, XZR |
0x41dd6c ORR W1, WZR, W29 |
0x41dd70 BL 404900 |
0x41dd74 LDP X8, X9, [X20, #8] |
0x41dd78 ORR X0, XZR, XZR |
0x41dd7c ORR W1, WZR, W29 |
0x41dd80 ADD X3, SP, #172 |
0x41dd84 ADD X4, SP, #168 |
0x41dd88 ADD X5, SP, #164 |
0x41dd8c STR WZR, [SP, #172] |
0x41dd90 LDR W9, [X9] |
0x41dd94 LDR W8, [X8] |
0x41dd98 ADD X6, SP, #160 |
0x41dd9c MOVZ W2, #34 |
0x41dda0 MOVZ W7, #1 |
0x41dda4 STR W21, [SP, #160] |
0x41dda8 STR W21, [SP] |
0x41ddac ADD W19, W9, #1 |
0x41ddb0 STP W19, W8, [SP, #164] |
0x41ddb4 BL 404c10 |
0x41ddb8 LDRSW X8, [SP, #168] |
0x41ddbc CMP W8, W19 |
0x41ddc0 B.GT 41e2b0 |
0x41ddc4 LDR W9, [SP, #164] |
0x41ddc8 SUBS W9, W9, W8 |
0x41ddcc B.MI 41e2b0 |
0x41ddd0 LDP X11, X10, [X20, #24] |
0x41ddd4 CNTD X14, ALL |
0x41ddd8 FMOV D0, #0.2500000 |
0x41dddc PTRUE P0.D, ALL |
0x41dde0 FDUP Z1.D, #80 |
0x41dde4 ADD W9, W9, #1 |
0x41dde8 MOVN X15, #0 |
0x41ddec LDR W10, [X10] |
0x41ddf0 LDR W11, [X11] |
0x41ddf4 SUB W13, W10, W11 |
0x41ddf8 SUB W12, W11, #1 |
0x41ddfc SBFM X30, X12, #0, #31 |
0x41de00 ADD W12, W13, #3 |
0x41de04 ADD W22, W13, #4 |
0x41de08 SUB X13, X8, #1 |
0x41de0c ADD X27, X12, #1 |
0x41de10 STR W22, [SP, #40] |
0x41de14 STP X27, X30, [SP, #24] |
0x41de18 B 41de30 |
0x41de1c HINT #0 |
(482) 0x41de20 ADD X8, X8, #1 |
(482) 0x41de24 SUBS W9, W9, #1 |
(482) 0x41de28 ADD X13, X13, #1 |
(482) 0x41de2c B.LE 41e2b0 |
(482) 0x41de30 CMP W22, #1 |
(482) 0x41de34 B.LT 41de20 |
(482) 0x41de38 LDR X16, [X20, #64] |
(482) 0x41de3c LDR X17, [X20, #104] |
(482) 0x41de40 LDR X18, [X20, #128] |
(482) 0x41de44 ORR X6, XZR, X30 |
(482) 0x41de48 ORR W21, WZR, W22 |
(482) 0x41de4c CMP X27, X14 |
(482) 0x41de50 LDR X0, [X20, #160] |
(482) 0x41de54 LDR X1, [X20, #40] |
(482) 0x41de58 LDP X3, X2, [X20, #240] |
(482) 0x41de5c LDR X4, [X20, #224] |
(482) 0x41de60 LDR X5, [X20, #256] |
(482) 0x41de64 LDR X16, [X16] |
(482) 0x41de68 LDR X17, [X17] |
(482) 0x41de6c LDR X18, [X18] |
(482) 0x41de70 LDR X0, [X0] |
(482) 0x41de74 B.CC 41df68 |
(482) 0x41de78 UDIV X6, X27, X14 |
(482) 0x41de7c MADD X19, X16, X8, X30 |
(482) 0x41de80 ORR X7, XZR, XZR |
(482) 0x41de84 SUB X19, X19, X17 |
(482) 0x41de88 UBFM X19, X19, #61, #60 |
(482) 0x41de8c ADD X23, X4, X19 |
(482) 0x41de90 ADD X24, X1, X19 |
(482) 0x41de94 ADD X25, X5, X19 |
(482) 0x41de98 MADD X26, X6, X14, XZR |
(482) 0x41de9c SUB X10, X27, X26 |
(482) 0x41dea0 ADD X27, X3, X19 |
(482) 0x41dea4 MADD X19, X18, X8, X30 |
(482) 0x41dea8 ADD X6, X26, X30 |
(482) 0x41deac SUB W21, W22, W26 |
(482) 0x41deb0 SUB X19, X19, X0 |
(482) 0x41deb4 STR X10, [SP, #48] |
(482) 0x41deb8 ADD X28, X2, X19,LSL #3 |
(482) 0x41debc MADD X19, X16, X13, X30 |
(482) 0x41dec0 SUB X19, X19, X17 |
(482) 0x41dec4 ADD X29, X1, X19,LSL #3 |
(482) 0x41dec8 MADD X19, X18, X13, X30 |
(482) 0x41decc SUB X19, X19, X0 |
(482) 0x41ded0 ADD X30, X2, X19,LSL #3 |
(482) 0x41ded4 HINT #0 |
(482) 0x41ded8 HINT #0 |
(482) 0x41dedc HINT #0 |
(484) 0x41dee0 UBFM X19, X7, #61, #60 |
(484) 0x41dee4 ADD X10, X29, X19 |
(484) 0x41dee8 ADD X11, X30, X19 |
(484) 0x41deec ADD X12, X24, X19 |
(484) 0x41def0 ADD X22, X28, X19 |
(484) 0x41def4 LD1D {Z4.D}, P0/Z, [X10, X15,LSL #3] |
(484) 0x41def8 LD1D {Z5.D}, P0/Z, [X11, X15,LSL #3] |
(484) 0x41defc LD1D {Z2.D}, P0/Z, [X12, X15,LSL #3] |
(484) 0x41df00 LD1D {Z3.D}, P0/Z, [X22, X15,LSL #3] |
(484) 0x41df04 FMUL Z4.D, Z4.D, Z5.D |
(484) 0x41df08 FMAD Z2.D, P0/M, Z3.D, Z4.D |
(484) 0x41df0c LD1D {Z3.D}, P0/Z, [X12, MUL VL] |
(484) 0x41df10 LD1D {Z4.D}, P0/Z, [X22, MUL VL] |
(484) 0x41df14 LD1D {Z5.D}, P0/Z, [X10, MUL VL] |
(484) 0x41df18 LD1D {Z6.D}, P0/Z, [X11, MUL VL] |
(484) 0x41df1c ADD X10, X23, X19 |
(484) 0x41df20 FMUL Z5.D, Z5.D, Z6.D |
(484) 0x41df24 FMAD Z3.D, P0/M, Z4.D, Z5.D |
(484) 0x41df28 FADD Z2.D, Z2.D, Z3.D |
(484) 0x41df2c FMUL Z2.D, Z2.D, Z1.D |
(484) 0x41df30 ST1D {Z2.D}, P0, [X27, X7,LSL #3] |
(484) 0x41df34 LD1D {Z3.D}, P0/Z, [X10, MUL VL] |
(484) 0x41df38 LD1D {Z4.D}, P0/Z, [X10, X15,LSL #3] |
(484) 0x41df3c FSUB Z2.D, Z2.D, Z4.D |
(484) 0x41df40 FADD Z2.D, Z3.D, Z2.D |
(484) 0x41df44 ST1D {Z2.D}, P0, [X25, X7,LSL #3] |
(484) 0x41df48 ADD X7, X7, X14 |
(484) 0x41df4c CMP X26, X7 |
(484) 0x41df50 B.NE 41dee0 |
(482) 0x41df54 LDR W29, [SP, #60] |
(482) 0x41df58 LDR W22, [SP, #40] |
(482) 0x41df5c LDP X27, X30, [SP, #24] |
(482) 0x41df60 LDR X10, [SP, #48] |
(482) 0x41df64 CBZ X10, 41de20 |
(482) 0x41df68 MADD X10, X16, X8, X6 |
(482) 0x41df6c MADD X12, X16, X13, X6 |
(482) 0x41df70 SUB X11, X1, #8 |
(482) 0x41df74 ADD W21, W21, #1 |
(482) 0x41df78 MADD X16, X18, X8, X6 |
(482) 0x41df7c ORR X7, XZR, XZR |
(482) 0x41df80 SUB X10, X10, X17 |
(482) 0x41df84 SUB X12, X12, X17 |
(482) 0x41df88 UBFM X10, X10, #61, #60 |
(482) 0x41df8c ADD X17, X11, X12,LSL #3 |
(482) 0x41df90 SUB X16, X16, X0 |
(482) 0x41df94 ADD X1, X4, X10 |
(482) 0x41df98 ADD X4, X5, X10 |
(482) 0x41df9c ADD X5, X11, X10 |
(482) 0x41dfa0 MADD X11, X18, X13, X6 |
(482) 0x41dfa4 ADD X3, X3, X10 |
(482) 0x41dfa8 SUB X10, X2, #8 |
(482) 0x41dfac ADD X16, X10, X16,LSL #3 |
(482) 0x41dfb0 SUB X11, X11, X0 |
(482) 0x41dfb4 ADD X18, X10, X11,LSL #3 |
(482) 0x41dfb8 HINT #0 |
(482) 0x41dfbc HINT #0 |
(483) 0x41dfc0 LDR Q4, [X17, X7] |
(483) 0x41dfc4 LDR Q5, [X18, X7] |
(483) 0x41dfc8 LDR Q2, [X5, X7] |
(483) 0x41dfcc ADD X10, X1, X7 |
(483) 0x41dfd0 SUB W21, W21, #1 |
(483) 0x41dfd4 FMUL V4.2D, V4.2D, V5.2D |
(483) 0x41dfd8 CMP W21, #1 |
(483) 0x41dfdc LDR Q3, [X16, X7] |
(483) 0x41dfe0 FMLA V4.2D, V3.2D, V2.2D |
(483) 0x41dfe4 FADDP D2, V4.2D |
(483) 0x41dfe8 LDP D4, D3, [X10, #1016] |
(483) 0x41dfec FMUL D2, D2, D0 |
(483) 0x41dff0 STR D2, [X3, X7] |
(483) 0x41dff4 FSUB D2, D2, S4 |
(483) 0x41dff8 FADD D2, D3, D2 |
(483) 0x41dffc STR D2, [X4, X7] |
(483) 0x41e000 ADD X7, X7, #8 |
(483) 0x41e004 B.HI 41dfc0 |
(482) 0x41e008 B 41de20 |
0x41e00c ORR X0, XZR, XZR |
0x41e010 ORR W1, WZR, W29 |
0x41e014 BL 404d30 |
0x41e018 ORR X0, XZR, XZR |
0x41e01c ORR W1, WZR, W29 |
0x41e020 BL 404900 |
0x41e024 LDP X8, X9, [X20, #8] |
0x41e028 ORR X0, XZR, XZR |
0x41e02c ORR W1, WZR, W29 |
0x41e030 ADD X3, SP, #108 |
0x41e034 ADD X4, SP, #104 |
0x41e038 ADD X5, SP, #100 |
0x41e03c STR WZR, [SP, #108] |
0x41e040 LDR W8, [X8] |
0x41e044 LDR W9, [X9] |
0x41e048 ADD X6, SP, #96 |
0x41e04c MOVZ W2, #34 |
0x41e050 MOVZ W7, #1 |
0x41e054 STR W21, [SP, #96] |
0x41e058 STR W21, [SP] |
0x41e05c SUB W8, W8, #1 |
0x41e060 ADD W19, W9, #2 |
0x41e064 STP W19, W8, [SP, #100] |
0x41e068 BL 404c10 |
0x41e06c LDRSW X8, [SP, #104] |
0x41e070 CMP W8, W19 |
0x41e074 B.GT 41e6b4 |
0x41e078 LDR W9, [SP, #100] |
0x41e07c SUBS W9, W9, W8 |
0x41e080 B.MI 41e6b4 |
0x41e084 LDP X11, X10, [X20, #24] |
0x41e088 CNTD X14, ALL |
0x41e08c FMOV D0, #0.2500000 |
0x41e090 PTRUE P0.D, ALL |
0x41e094 FDUP Z1.D, #80 |
0x41e098 ADD W9, W9, #1 |
0x41e09c SUB X13, X8, #1 |
0x41e0a0 MOVN X15, #0 |
0x41e0a4 LDR W12, [X10] |
0x41e0a8 LDRSW X22, [X11] |
0x41e0ac SUB W12, W12, W22 |
0x41e0b0 STR X22, [SP, #40] |
0x41e0b4 ADD W28, W12, #2 |
0x41e0b8 ADD W12, W12, #1 |
0x41e0bc ADD X30, X12, #1 |
0x41e0c0 STR W28, [SP, #32] |
0x41e0c4 STR X30, [SP, #24] |
0x41e0c8 B 41e0dc |
(485) 0x41e0cc ADD X8, X8, #1 |
(485) 0x41e0d0 SUBS W9, W9, #1 |
(485) 0x41e0d4 ADD X13, X13, #1 |
(485) 0x41e0d8 B.LE 41e6b4 |
(485) 0x41e0dc CMP W28, #1 |
(485) 0x41e0e0 B.LT 41e0cc |
(485) 0x41e0e4 LDR X16, [X20, #64] |
(485) 0x41e0e8 LDR X17, [X20, #160] |
(485) 0x41e0ec LDR X4, [X20, #40] |
(485) 0x41e0f0 ORR X7, XZR, X22 |
(485) 0x41e0f4 ORR W6, WZR, W28 |
(485) 0x41e0f8 CMP X30, X14 |
(485) 0x41e0fc LDP X2, X5, [X20, #240] |
(485) 0x41e100 LDR X1, [X20, #224] |
(485) 0x41e104 LDR X3, [X20, #256] |
(485) 0x41e108 LDR X18, [X16] |
(485) 0x41e10c LDR X16, [X20, #104] |
(485) 0x41e110 LDR X17, [X17] |
(485) 0x41e114 LDR X0, [X16] |
(485) 0x41e118 LDR X16, [X20, #128] |
(485) 0x41e11c LDR X16, [X16] |
(485) 0x41e120 B.CC 41e20c |
(485) 0x41e124 UDIV X6, X30, X14 |
(485) 0x41e128 MADD X19, X16, X8, X22 |
(485) 0x41e12c MADD X7, X18, X8, X22 |
(485) 0x41e130 ORR X21, XZR, XZR |
(485) 0x41e134 SUB X19, X19, X17 |
(485) 0x41e138 SUB X7, X7, X0 |
(485) 0x41e13c UBFM X7, X7, #61, #60 |
(485) 0x41e140 ADD X23, X4, X7 |
(485) 0x41e144 ADD X24, X3, X7 |
(485) 0x41e148 ADD X25, X1, X7 |
(485) 0x41e14c ADD X26, X2, X7 |
(485) 0x41e150 MADD X27, X6, X14, XZR |
(485) 0x41e154 SUB W6, W28, W27 |
(485) 0x41e158 ADD X28, X5, X19,LSL #3 |
(485) 0x41e15c MADD X19, X18, X13, X22 |
(485) 0x41e160 SUB X10, X30, X27 |
(485) 0x41e164 ADD X7, X27, X22 |
(485) 0x41e168 SUB X19, X19, X0 |
(485) 0x41e16c STR X10, [SP, #48] |
(485) 0x41e170 UBFM X19, X19, #61, #60 |
(485) 0x41e174 ADD X29, X4, X19 |
(485) 0x41e178 ADD X30, X1, X19 |
(485) 0x41e17c MADD X19, X16, X13, X22 |
(485) 0x41e180 SUB X19, X19, X17 |
(485) 0x41e184 ADD X19, X5, X19,LSL #3 |
(487) 0x41e188 UBFM X12, X21, #61, #60 |
(487) 0x41e18c ADD X22, X23, X12 |
(487) 0x41e190 ADD X11, X28, X12 |
(487) 0x41e194 ADD X10, X29, X12 |
(487) 0x41e198 ADD X12, X19, X12 |
(487) 0x41e19c LD1D {Z4.D}, P0/Z, [X10, X15,LSL #3] |
(487) 0x41e1a0 LD1D {Z5.D}, P0/Z, [X12, X15,LSL #3] |
(487) 0x41e1a4 LD1D {Z2.D}, P0/Z, [X22, X15,LSL #3] |
(487) 0x41e1a8 LD1D {Z3.D}, P0/Z, [X11, X15,LSL #3] |
(487) 0x41e1ac FMUL Z4.D, Z4.D, Z5.D |
(487) 0x41e1b0 FMAD Z2.D, P0/M, Z3.D, Z4.D |
(487) 0x41e1b4 LD1D {Z3.D}, P0/Z, [X22, MUL VL] |
(487) 0x41e1b8 LD1D {Z4.D}, P0/Z, [X11, MUL VL] |
(487) 0x41e1bc LD1D {Z5.D}, P0/Z, [X10, MUL VL] |
(487) 0x41e1c0 LD1D {Z6.D}, P0/Z, [X12, MUL VL] |
(487) 0x41e1c4 FMUL Z5.D, Z5.D, Z6.D |
(487) 0x41e1c8 FMAD Z3.D, P0/M, Z4.D, Z5.D |
(487) 0x41e1cc LD1D {Z4.D}, P0/Z, [X30, X21,LSL #3] |
(487) 0x41e1d0 FADD Z2.D, Z2.D, Z3.D |
(487) 0x41e1d4 LD1D {Z3.D}, P0/Z, [X25, X21,LSL #3] |
(487) 0x41e1d8 FMUL Z2.D, Z2.D, Z1.D |
(487) 0x41e1dc ST1D {Z2.D}, P0, [X26, X21,LSL #3] |
(487) 0x41e1e0 FSUB Z2.D, Z2.D, Z4.D |
(487) 0x41e1e4 FADD Z2.D, Z3.D, Z2.D |
(487) 0x41e1e8 ST1D {Z2.D}, P0, [X24, X21,LSL #3] |
(487) 0x41e1ec ADD X21, X21, X14 |
(487) 0x41e1f0 CMP X27, X21 |
(487) 0x41e1f4 B.NE 41e188 |
(485) 0x41e1f8 LDR W29, [SP, #60] |
(485) 0x41e1fc LDP X22, X10, [SP, #40] |
(485) 0x41e200 LDR W28, [SP, #32] |
(485) 0x41e204 LDR X30, [SP, #24] |
(485) 0x41e208 CBZ X10, 41e0cc |
(485) 0x41e20c MADD X10, X18, X8, X7 |
(485) 0x41e210 MADD X18, X18, X13, X7 |
(485) 0x41e214 SUB X11, X4, #8 |
(485) 0x41e218 SUB X12, X5, #8 |
(485) 0x41e21c ORR X21, XZR, XZR |
(485) 0x41e220 SUB X10, X10, X0 |
(485) 0x41e224 SUB X5, X18, X0 |
(485) 0x41e228 UBFM X10, X10, #61, #60 |
(485) 0x41e22c ADD X18, X1, X10 |
(485) 0x41e230 ADD X0, X3, X10 |
(485) 0x41e234 ADD X2, X2, X10 |
(485) 0x41e238 ADD X3, X11, X10 |
(485) 0x41e23c MADD X10, X16, X8, X7 |
(485) 0x41e240 SUB X10, X10, X17 |
(485) 0x41e244 ADD X4, X12, X10,LSL #3 |
(485) 0x41e248 UBFM X10, X5, #61, #60 |
(485) 0x41e24c ADD X1, X1, X10 |
(485) 0x41e250 ADD X5, X11, X10 |
(485) 0x41e254 MADD X10, X16, X13, X7 |
(485) 0x41e258 SUB X10, X10, X17 |
(485) 0x41e25c ADD W17, W6, #1 |
(485) 0x41e260 ADD X16, X12, X10,LSL #3 |
(486) 0x41e264 LDR Q4, [X5, X21] |
(486) 0x41e268 LDR Q5, [X16, X21] |
(486) 0x41e26c LDR Q2, [X3, X21] |
(486) 0x41e270 SUB W17, W17, #1 |
(486) 0x41e274 CMP W17, #1 |
(486) 0x41e278 LDR Q3, [X4, X21] |
(486) 0x41e27c FMUL V4.2D, V4.2D, V5.2D |
(486) 0x41e280 FMLA V4.2D, V3.2D, V2.2D |
(486) 0x41e284 LDR D3, [X18, X21] |
(486) 0x41e288 FADDP D2, V4.2D |
(486) 0x41e28c LDR D4, [X1, X21] |
(486) 0x41e290 FMUL D2, D2, D0 |
(486) 0x41e294 STR D2, [X2, X21] |
(486) 0x41e298 FSUB D2, D2, S4 |
(486) 0x41e29c FADD D2, D3, D2 |
(486) 0x41e2a0 STR D2, [X0, X21] |
(486) 0x41e2a4 ADD X21, X21, #8 |
(486) 0x41e2a8 B.HI 41e264 |
(485) 0x41e2ac B 41e0cc |
0x41e2b0 ORR X0, XZR, XZR |
0x41e2b4 ORR W1, WZR, W29 |
0x41e2b8 BL 404d30 |
0x41e2bc ORR X0, XZR, XZR |
0x41e2c0 ORR W1, WZR, W29 |
0x41e2c4 BL 404900 |
0x41e2c8 LDP X8, X9, [X20, #8] |
0x41e2cc ORR X0, XZR, XZR |
0x41e2d0 ORR W1, WZR, W29 |
0x41e2d4 MOVZ W21, #1 |
0x41e2d8 ADD X3, SP, #156 |
0x41e2dc ADD X4, SP, #152 |
0x41e2e0 STR WZR, [SP, #156] |
0x41e2e4 LDR W9, [X9] |
0x41e2e8 LDR W8, [X8] |
0x41e2ec ADD X5, SP, #148 |
0x41e2f0 ADD X6, SP, #144 |
0x41e2f4 MOVZ W2, #34 |
0x41e2f8 MOVZ W7, #1 |
0x41e2fc STR W21, [SP, #144] |
0x41e300 STR W21, [SP] |
0x41e304 ADD W19, W9, #1 |
0x41e308 STP W19, W8, [SP, #148] |
0x41e30c BL 404c10 |
0x41e310 LDRSW X8, [SP, #152] |
0x41e314 CMP W8, W19 |
0x41e318 B.GT 41e4c0 |
0x41e31c LDR W9, [SP, #148] |
0x41e320 SUBS W9, W9, W8 |
0x41e324 B.MI 41e4c0 |
0x41e328 LDP X11, X10, [X20, #24] |
0x41e32c FMOV D0, #1.0000000 |
0x41e330 FMOV D1, #2.0000000 |
0x41e334 ADD W9, W9, #1 |
0x41e338 LDR W12, [X10] |
0x41e33c LDR W10, [X11] |
0x41e340 FMOV D2, #6.0000000 |
0x41e344 SUB W14, W12, W10 |
0x41e348 SUB W13, W10, #1 |
0x41e34c SBFM X12, X13, #0, #31 |
0x41e350 SBFM X13, X13, #61, #31 |
0x41e354 ADD W11, W14, #3 |
0x41e358 ADD W14, W14, #4 |
0x41e35c B 41e36c |
(480) 0x41e360 ADD X8, X8, #1 |
(480) 0x41e364 SUBS W9, W9, #1 |
(480) 0x41e368 B.LE 41e4c0 |
(480) 0x41e36c CMP W11, #1 |
(480) 0x41e370 B.LT 41e360 |
(480) 0x41e374 LDR X16, [X20, #64] |
(480) 0x41e378 LDR X17, [X20, #256] |
(480) 0x41e37c LDP X1, X2, [X20, #288] |
(480) 0x41e380 ORR X15, XZR, XZR |
(480) 0x41e384 LDR X16, [X16] |
(480) 0x41e388 MADD X18, X16, X8, XZR |
(480) 0x41e38c LDR X16, [X20, #104] |
(480) 0x41e390 LDR X0, [X16] |
(480) 0x41e394 SUB X16, X18, X0 |
(480) 0x41e398 ADD X18, X12, X18 |
(480) 0x41e39c UBFM X3, X16, #61, #60 |
(480) 0x41e3a0 SUB X18, X18, X0 |
(480) 0x41e3a4 ADD X16, X17, X3 |
(480) 0x41e3a8 ADD X17, X1, X3 |
(480) 0x41e3ac LDR X1, [X20, #224] |
(480) 0x41e3b0 UBFM X0, X18, #61, #60 |
(480) 0x41e3b4 ADD X18, X2, X0 |
(480) 0x41e3b8 ORR X2, XZR, X12 |
(480) 0x41e3bc ADD X0, X1, X0 |
(480) 0x41e3c0 ORR W1, WZR, W14 |
(480) 0x41e3c4 B 41e3ec |
(481) 0x41e3c8 FSUB D4, D0, S4 |
(481) 0x41e3cc SUB W1, W1, #1 |
(481) 0x41e3d0 ADD X2, X2, #1 |
(481) 0x41e3d4 CMP W1, #1 |
(481) 0x41e3d8 FMADD D4, D4, D16, D5 |
(481) 0x41e3dc FMUL D3, D3, D4 |
(481) 0x41e3e0 STR D3, [X18, X15,LSL #3] |
(481) 0x41e3e4 ADD X15, X15, #1 |
(481) 0x41e3e8 B.LE 41e360 |
(481) 0x41e3ec LDR D3, [X0, X15,LSL #3] |
(481) 0x41e3f0 FCMP D3, #0 |
(481) 0x41e3f4 B.MI 41e40c |
(481) 0x41e3f8 SUB W3, W2, #1 |
(481) 0x41e3fc ORR X5, XZR, X2 |
(481) 0x41e400 ADD X4, X2, #1 |
(481) 0x41e404 ORR W6, WZR, W3 |
(481) 0x41e408 B 41e41c |
(481) 0x41e40c ADD X4, X12, X15 |
(481) 0x41e410 ADD W3, W10, W15 |
(481) 0x41e414 ADD X5, X4, #1 |
(481) 0x41e418 ADD W6, W3, #1 |
(481) 0x41e41c SBFM X5, X5, #61, #31 |
(481) 0x41e420 FABS D4, D3 |
(481) 0x41e424 LDR D6, [X17, X6,SXTW #3] |
(481) 0x41e428 SBFM X4, X4, #61, #31 |
(481) 0x41e42c MOVI D16, #0 |
(481) 0x41e430 LDR D5, [X16, X5] |
(481) 0x41e434 FDIV D4, D4, D5 |
(481) 0x41e438 LDR D5, [X17, X5] |
(481) 0x41e43c FSUB D7, D5, S6 |
(481) 0x41e440 LDR D6, [X17, X4] |
(481) 0x41e444 FSUB D6, D6, S5 |
(481) 0x41e448 FMUL D17, D7, D6 |
(481) 0x41e44c FCMP D17, #0 |
(481) 0x41e450 B.LE 41e3c8 |
(481) 0x41e454 LDP X4, X5, [X20, #272] |
(481) 0x41e458 SBFM X3, X3, #0, #31 |
(481) 0x41e45c FABS D7, D7 |
(481) 0x41e460 FADD D18, D4, D0 |
(481) 0x41e464 LDR X5, [X5] |
(481) 0x41e468 FMUL D18, D18, D7 |
(481) 0x41e46c FABS D17, D6 |
(481) 0x41e470 SUB X3, X3, X5 |
(481) 0x41e474 SUB X6, X4, X5,LSL #3 |
(481) 0x41e478 LDR D19, [X4, X3,LSL #3] |
(481) 0x41e47c ADD X6, X6, X13 |
(481) 0x41e480 LDR D16, [X6, X15,LSL #3] |
(481) 0x41e484 FDIV D18, D18, D19 |
(481) 0x41e488 FSUB D19, D1, S4 |
(481) 0x41e48c FMUL D19, D19, D17 |
(481) 0x41e490 FDIV D19, D19, D16 |
(481) 0x41e494 FADD D18, D19, D18 |
(481) 0x41e498 FMUL D16, D16, D18 |
(481) 0x41e49c FDIV D16, D16, D2 |
(481) 0x41e4a0 FCMP D16, D7 |
(481) 0x41e4a4 FCSEL D7, D7, D16, #10 |
(481) 0x41e4a8 FCMP D7, D17 |
(481) 0x41e4ac FCSEL D7, D17, D7, #10 |
(481) 0x41e4b0 FCMP D6, #0 |
(481) 0x41e4b4 FNEG D16, D7 |
(481) 0x41e4b8 FCSEL D16, D7, D16, #8 |
(481) 0x41e4bc B 41e3c8 |
0x41e4c0 ORR X0, XZR, XZR |
0x41e4c4 ORR W1, WZR, W29 |
0x41e4c8 BL 404d30 |
0x41e4cc ORR X0, XZR, XZR |
0x41e4d0 ORR W1, WZR, W29 |
0x41e4d4 BL 404900 |
0x41e4d8 LDP X8, X9, [X20, #8] |
0x41e4dc ORR X0, XZR, XZR |
0x41e4e0 ORR W1, WZR, W29 |
0x41e4e4 ADD X3, SP, #140 |
0x41e4e8 ADD X4, SP, #136 |
0x41e4ec ADD X5, SP, #132 |
0x41e4f0 STR WZR, [SP, #140] |
0x41e4f4 LDR W9, [X9] |
0x41e4f8 LDR W8, [X8] |
0x41e4fc ADD X6, SP, #128 |
0x41e500 MOVZ W2, #34 |
0x41e504 MOVZ W7, #1 |
0x41e508 STR W21, [SP, #128] |
0x41e50c STR W21, [SP] |
0x41e510 ADD W19, W9, #1 |
0x41e514 STP W19, W8, [SP, #132] |
0x41e518 BL 404c10 |
0x41e51c LDRSW X8, [SP, #136] |
0x41e520 CMP W8, W19 |
0x41e524 B.GT 41eac0 |
0x41e528 LDR W9, [SP, #132] |
0x41e52c SUBS W9, W9, W8 |
0x41e530 B.MI 41eac0 |
0x41e534 LDP X11, X10, [X20, #24] |
0x41e538 CNTW X13, ALL |
0x41e53c PTRUE P0.D, ALL |
0x41e540 ADD W9, W9, #1 |
0x41e544 MOVN X14, #0 |
0x41e548 LDR W12, [X10] |
0x41e54c LDRSW X10, [X11] |
0x41e550 SUB W12, W12, W10 |
0x41e554 ADD W11, W12, #2 |
0x41e558 ADD W12, W12, #1 |
0x41e55c ADD X12, X12, #1 |
0x41e560 B 41e570 |
(477) 0x41e564 ADD X8, X8, #1 |
(477) 0x41e568 SUBS W9, W9, #1 |
(477) 0x41e56c B.LE 41eac0 |
(477) 0x41e570 CMP W11, #1 |
(477) 0x41e574 B.LT 41e564 |
(477) 0x41e578 LDR X15, [X20, #64] |
(477) 0x41e57c LDR X16, [X20, #256] |
(477) 0x41e580 LDR X1, [X20, #240] |
(477) 0x41e584 ORR X2, XZR, X10 |
(477) 0x41e588 ORR W4, WZR, W11 |
(477) 0x41e58c CMP X12, X13 |
(477) 0x41e590 LDR X17, [X15] |
(477) 0x41e594 LDR X15, [X20, #104] |
(477) 0x41e598 LDR X0, [X15] |
(477) 0x41e59c LDP X18, X15, [X20, #288] |
(477) 0x41e5a0 B.CC 41e650 |
(477) 0x41e5a4 UDIV X2, X12, X13 |
(477) 0x41e5a8 MADD X4, X17, X8, X10 |
(477) 0x41e5ac ORR X3, XZR, XZR |
(477) 0x41e5b0 SUB X7, X4, X0 |
(477) 0x41e5b4 UBFM X19, X7, #61, #60 |
(477) 0x41e5b8 ADDVL X26, X19, #1 |
(477) 0x41e5bc ADD X21, X15, X19 |
(477) 0x41e5c0 ADD X22, X1, X19 |
(477) 0x41e5c4 ADD X24, X18, X19 |
(477) 0x41e5c8 ADD X19, X16, X19 |
(477) 0x41e5cc ADD X7, X15, X26 |
(477) 0x41e5d0 ADD X23, X1, X26 |
(477) 0x41e5d4 ADD X25, X18, X26 |
(477) 0x41e5d8 ADD X26, X16, X26 |
(477) 0x41e5dc MADD X6, X2, X13, XZR |
(477) 0x41e5e0 SUB X5, X12, X6 |
(477) 0x41e5e4 ADD X2, X6, X10 |
(477) 0x41e5e8 SUB W4, W11, W6 |
(479) 0x41e5ec UBFM X27, X3, #61, #60 |
(479) 0x41e5f0 LD1D {Z2.D}, P0/Z, [X19, X3,LSL #3] |
(479) 0x41e5f4 LD1D {Z3.D}, P0/Z, [X26, X3,LSL #3] |
(479) 0x41e5f8 ADD X28, X21, X27 |
(479) 0x41e5fc ADD X27, X7, X27 |
(479) 0x41e600 LD1D {Z4.D}, P0/Z, [X24, X3,LSL #3] |
(479) 0x41e604 LD1D {Z5.D}, P0/Z, [X25, X3,LSL #3] |
(479) 0x41e608 LD1D {Z0.D}, P0/Z, [X28, X14,LSL #3] |
(479) 0x41e60c LD1D {Z1.D}, P0/Z, [X27, X14,LSL #3] |
(479) 0x41e610 FMLA Z0.D, P0/M, Z2.D, Z4.D |
(479) 0x41e614 FMLA Z1.D, P0/M, Z3.D, Z5.D |
(479) 0x41e618 LD1D {Z2.D}, P0/Z, [X28, MUL VL] |
(479) 0x41e61c LD1D {Z3.D}, P0/Z, [X27, MUL VL] |
(479) 0x41e620 FSUB Z0.D, Z0.D, Z2.D |
(479) 0x41e624 FSUB Z1.D, Z1.D, Z3.D |
(479) 0x41e628 LD1D {Z2.D}, P0/Z, [X22, X3,LSL #3] |
(479) 0x41e62c LD1D {Z3.D}, P0/Z, [X23, X3,LSL #3] |
(479) 0x41e630 FDIV Z0.D, P0/M, Z0.D, Z2.D |
(479) 0x41e634 FDIV Z1.D, P0/M, Z1.D, Z3.D |
(479) 0x41e638 ST1D {Z0.D}, P0, [X24, X3,LSL #3] |
(479) 0x41e63c ST1D {Z1.D}, P0, [X25, X3,LSL #3] |
(479) 0x41e640 ADD X3, X3, X13 |
(479) 0x41e644 CMP X6, X3 |
(479) 0x41e648 B.NE 41e5ec |
(477) 0x41e64c CBZ X5, 41e564 |
(477) 0x41e650 MADD X17, X17, X8, X2 |
(477) 0x41e654 ADD W3, W4, #1 |
(477) 0x41e658 SUB X17, X17, X0 |
(477) 0x41e65c UBFM X0, X17, #61, #60 |
(477) 0x41e660 ADD X17, X1, X0 |
(477) 0x41e664 ADD X18, X18, X0 |
(477) 0x41e668 ADD X16, X16, X0 |
(477) 0x41e66c ADD X15, X15, X0 |
(477) 0x41e670 HINT #0 |
(477) 0x41e674 HINT #0 |
(477) 0x41e678 HINT #0 |
(477) 0x41e67c HINT #0 |
(478) 0x41e680 LDUR D0, [X15, #504] |
(478) 0x41e684 LDR D2, [X18] |
(478) 0x41e688 LDR D1, [X16], #8 |
(478) 0x41e68c SUB W3, W3, #1 |
(478) 0x41e690 CMP W3, #1 |
(478) 0x41e694 FMADD D0, D1, D2, D0 |
(478) 0x41e698 LDR D2, [X15], #8 |
(478) 0x41e69c LDR D1, [X17], #8 |
(478) 0x41e6a0 FSUB D0, D0, S2 |
(478) 0x41e6a4 FDIV D0, D0, D1 |
(478) 0x41e6a8 STR D0, [X18], #8 |
(478) 0x41e6ac B.HI 41e680 |
(477) 0x41e6b0 B 41e564 |
0x41e6b4 ORR X0, XZR, XZR |
0x41e6b8 ORR W1, WZR, W29 |
0x41e6bc BL 404d30 |
0x41e6c0 ORR X0, XZR, XZR |
0x41e6c4 ORR W1, WZR, W29 |
0x41e6c8 BL 404900 |
0x41e6cc LDP X8, X9, [X20, #8] |
0x41e6d0 ORR X0, XZR, XZR |
0x41e6d4 ORR W1, WZR, W29 |
0x41e6d8 MOVZ W21, #1 |
0x41e6dc ADD X3, SP, #92 |
0x41e6e0 ADD X4, SP, #88 |
0x41e6e4 STR WZR, [SP, #92] |
0x41e6e8 LDR W8, [X8] |
0x41e6ec LDR W9, [X9] |
0x41e6f0 ADD X5, SP, #84 |
0x41e6f4 ADD X6, SP, #80 |
0x41e6f8 MOVZ W2, #34 |
0x41e6fc MOVZ W7, #1 |
0x41e700 STR W21, [SP, #80] |
0x41e704 STR W21, [SP] |
0x41e708 ADD W19, W9, #1 |
0x41e70c SUB W8, W8, #1 |
0x41e710 STP W19, W8, [SP, #84] |
0x41e714 BL 404c10 |
0x41e718 LDRSW X8, [SP, #88] |
0x41e71c CMP W8, W19 |
0x41e720 B.GT 41e8a8 |
0x41e724 LDR W9, [SP, #84] |
0x41e728 SUBS W9, W9, W8 |
0x41e72c B.MI 41e8a8 |
0x41e730 LDP X11, X10, [X20, #24] |
0x41e734 FMOV D0, #1.0000000 |
0x41e738 FMOV D1, #2.0000000 |
0x41e73c ADD W9, W9, #1 |
0x41e740 LDR W12, [X10] |
0x41e744 LDRSW X10, [X11] |
0x41e748 FMOV D2, #6.0000000 |
0x41e74c SUB W12, W12, W10 |
0x41e750 ADD W11, W12, #2 |
0x41e754 ADD W12, W12, #3 |
0x41e758 B 41e770 |
0x41e75c HINT #0 |
(475) 0x41e760 ADD X13, X8, #1 |
(475) 0x41e764 ORR X8, XZR, X13 |
(475) 0x41e768 SUBS W9, W9, #1 |
(475) 0x41e76c B.LE 41e8a8 |
(475) 0x41e770 CMP W11, #0 |
(475) 0x41e774 B.LE 41e760 |
(476) 0x41e778 LDR X13, [X20, #64] |
(476) 0x41e77c LDR X2, [X20, #224] |
(476) 0x41e780 LDR X15, [X20, #256] |
(476) 0x41e784 SUB W16, W8, #1 |
(476) 0x41e788 ADD W17, W8, #2 |
(476) 0x41e78c LDR X14, [X13] |
(476) 0x41e790 LDR X13, [X20, #104] |
(476) 0x41e794 MADD X18, X8, X14, XZR |
(476) 0x41e798 LDR X1, [X13] |
(476) 0x41e79c ADD X13, X8, #1 |
(476) 0x41e7a0 UBFM X3, X18, #61, #60 |
(476) 0x41e7a4 LDP X18, X0, [X20, #288] |
(476) 0x41e7a8 ADD X2, X2, X3 |
(476) 0x41e7ac SUB X1, X10, X1 |
(476) 0x41e7b0 ADD X0, X0, X3 |
(476) 0x41e7b4 ORR W3, WZR, W12 |
(476) 0x41e7b8 B 41e7e0 |
0x41e7bc HINT #0 |
(476) 0x41e7c0 FSUB D4, D0, S4 |
(476) 0x41e7c4 SUB W3, W3, #1 |
(476) 0x41e7c8 CMP W3, #1 |
(476) 0x41e7cc FMADD D4, D4, D16, D5 |
(476) 0x41e7d0 FMUL D3, D3, D4 |
(476) 0x41e7d4 STR D3, [X0, X1,LSL #3] |
(476) 0x41e7d8 ADD X1, X1, #1 |
(476) 0x41e7dc B.LE 41e764 |
(476) 0x41e7e0 LDR D3, [X2, X1,LSL #3] |
(476) 0x41e7e4 MOVI D16, #0 |
(476) 0x41e7e8 FCMP D3, #0 |
(476) 0x41e7ec FABS D4, D3 |
(476) 0x41e7f0 CSINC W5, W8, W8, #5 |
(476) 0x41e7f4 CSEL W4, W16, W17, #5 |
(476) 0x41e7f8 CSINC X6, X8, X8, #4 |
(476) 0x41e7fc SBFM X5, X5, #0, #31 |
(476) 0x41e800 SBFM X4, X4, #0, #31 |
(476) 0x41e804 MADD X5, X14, X5, X1 |
(476) 0x41e808 MADD X4, X14, X4, X1 |
(476) 0x41e80c LDR D5, [X15, X5,LSL #3] |
(476) 0x41e810 LDR D6, [X18, X4,LSL #3] |
(476) 0x41e814 MADD X4, X14, X6, X1 |
(476) 0x41e818 FDIV D4, D4, D5 |
(476) 0x41e81c LDR D5, [X18, X5,LSL #3] |
(476) 0x41e820 FSUB D7, D5, S6 |
(476) 0x41e824 LDR D6, [X18, X4,LSL #3] |
(476) 0x41e828 FSUB D6, D6, S5 |
(476) 0x41e82c FMUL D17, D7, D6 |
(476) 0x41e830 FCMP D17, #0 |
(476) 0x41e834 B.LE 41e7c0 |
(476) 0x41e838 LDP X5, X6, [X20, #312] |
(476) 0x41e83c FCMP D3, #0 |
(476) 0x41e840 FABS D7, D7 |
(476) 0x41e844 FADD D18, D4, D0 |
(476) 0x41e848 CSEL W4, W16, W13, #5 |
(476) 0x41e84c FMUL D18, D18, D7 |
(476) 0x41e850 FABS D17, D6 |
(476) 0x41e854 SBFM X4, X4, #0, #31 |
(476) 0x41e858 LDR X6, [X6] |
(476) 0x41e85c SUB X4, X4, X6 |
(476) 0x41e860 SUB X7, X8, X6 |
(476) 0x41e864 LDR D19, [X5, X4,LSL #3] |
(476) 0x41e868 LDR D16, [X5, X7,LSL #3] |
(476) 0x41e86c FDIV D18, D18, D19 |
(476) 0x41e870 FSUB D19, D1, S4 |
(476) 0x41e874 FMUL D19, D19, D17 |
(476) 0x41e878 FDIV D19, D19, D16 |
(476) 0x41e87c FADD D18, D19, D18 |
(476) 0x41e880 FMUL D16, D16, D18 |
(476) 0x41e884 FDIV D16, D16, D2 |
(476) 0x41e888 FCMP D16, D7 |
(476) 0x41e88c FCSEL D7, D7, D16, #10 |
(476) 0x41e890 FCMP D7, D17 |
(476) 0x41e894 FCSEL D7, D17, D7, #10 |
(476) 0x41e898 FCMP D6, #0 |
(476) 0x41e89c FNEG D16, D7 |
(476) 0x41e8a0 FCSEL D16, D7, D16, #8 |
(476) 0x41e8a4 B 41e7c0 |
0x41e8a8 ORR X0, XZR, XZR |
0x41e8ac ORR W1, WZR, W29 |
0x41e8b0 BL 404d30 |
0x41e8b4 ORR X0, XZR, XZR |
0x41e8b8 ORR W1, WZR, W29 |
0x41e8bc BL 404900 |
0x41e8c0 LDP X8, X9, [X20, #8] |
0x41e8c4 ORR X0, XZR, XZR |
0x41e8c8 ORR W1, WZR, W29 |
0x41e8cc ADD X3, SP, #76 |
0x41e8d0 ADD X4, SP, #72 |
0x41e8d4 ADD X5, SP, #68 |
0x41e8d8 STR WZR, [SP, #76] |
0x41e8dc LDR W9, [X9] |
0x41e8e0 LDR W8, [X8] |
0x41e8e4 ADD X6, SP, #64 |
0x41e8e8 MOVZ W2, #34 |
0x41e8ec MOVZ W7, #1 |
0x41e8f0 STR W21, [SP, #64] |
0x41e8f4 STR W21, [SP] |
0x41e8f8 ADD W19, W9, #1 |
0x41e8fc STP W19, W8, [SP, #68] |
0x41e900 BL 404c10 |
0x41e904 LDRSW X8, [SP, #72] |
0x41e908 CMP W8, W19 |
0x41e90c B.GT 41eac0 |
0x41e910 LDR W9, [SP, #68] |
0x41e914 SUBS W9, W9, W8 |
0x41e918 B.MI 41eac0 |
0x41e91c LDP X11, X10, [X20, #24] |
0x41e920 CNTW X14, ALL |
0x41e924 PTRUE P0.D, ALL |
0x41e928 ADD W9, W9, #1 |
0x41e92c SUB X13, X8, #1 |
0x41e930 LDR W12, [X10] |
0x41e934 LDRSW X10, [X11] |
0x41e938 SUB W12, W12, W10 |
0x41e93c ADD W11, W12, #2 |
0x41e940 ADD W12, W12, #1 |
0x41e944 ADD X12, X12, #1 |
0x41e948 B 41e95c |
(472) 0x41e94c ADD X8, X8, #1 |
(472) 0x41e950 SUBS W9, W9, #1 |
(472) 0x41e954 ADD X13, X13, #1 |
(472) 0x41e958 B.LE 41eac0 |
(472) 0x41e95c CMP W11, #1 |
(472) 0x41e960 B.LT 41e94c |
(472) 0x41e964 LDR X15, [X20, #64] |
(472) 0x41e968 LDP X16, X17, [X20, #288] |
(472) 0x41e96c LDR X1, [X20, #240] |
(472) 0x41e970 ORR X4, XZR, X10 |
(472) 0x41e974 ORR W2, WZR, W11 |
(472) 0x41e978 CMP X12, X14 |
(472) 0x41e97c LDR X18, [X15] |
(472) 0x41e980 LDR X15, [X20, #104] |
(472) 0x41e984 LDR X0, [X15] |
(472) 0x41e988 LDR X15, [X20, #256] |
(472) 0x41e98c B.CC 41ea58 |
(472) 0x41e990 UDIV X2, X12, X14 |
(472) 0x41e994 MADD X4, X18, X13, X10 |
(472) 0x41e998 MADD X5, X18, X8, X10 |
(472) 0x41e99c ORR X3, XZR, XZR |
(472) 0x41e9a0 SUB X4, X4, X0 |
(472) 0x41e9a4 SUB X19, X5, X0 |
(472) 0x41e9a8 UBFM X4, X4, #61, #60 |
(472) 0x41e9ac UBFM X27, X19, #61, #60 |
(472) 0x41e9b0 ADD X6, X17, X4 |
(472) 0x41e9b4 ADDVL X4, X4, #1 |
(472) 0x41e9b8 ADDVL X28, X27, #1 |
(472) 0x41e9bc ADD X22, X1, X27 |
(472) 0x41e9c0 ADD X24, X17, X27 |
(472) 0x41e9c4 ADD X26, X16, X27 |
(472) 0x41e9c8 ADD X27, X15, X27 |
(472) 0x41e9cc ADD X7, X17, X4 |
(472) 0x41e9d0 ADD X23, X1, X28 |
(472) 0x41e9d4 ADD X25, X17, X28 |
(472) 0x41e9d8 ADD X19, X16, X28 |
(472) 0x41e9dc ADD X28, X15, X28 |
(472) 0x41e9e0 MADD X21, X2, X14, XZR |
(472) 0x41e9e4 SUB X5, X12, X21 |
(472) 0x41e9e8 ADD X4, X21, X10 |
(472) 0x41e9ec SUB W2, W11, W21 |
(472) 0x41e9f0 HINT #0 |
(472) 0x41e9f4 HINT #0 |
(472) 0x41e9f8 HINT #0 |
(472) 0x41e9fc HINT #0 |
(474) 0x41ea00 LD1D {Z0.D}, P0/Z, [X6, X3,LSL #3] |
(474) 0x41ea04 LD1D {Z1.D}, P0/Z, [X7, X3,LSL #3] |
(474) 0x41ea08 LD1D {Z2.D}, P0/Z, [X27, X3,LSL #3] |
(474) 0x41ea0c LD1D {Z3.D}, P0/Z, [X28, X3,LSL #3] |
(474) 0x41ea10 LD1D {Z4.D}, P0/Z, [X26, X3,LSL #3] |
(474) 0x41ea14 FMLA Z0.D, P0/M, Z2.D, Z4.D |
(474) 0x41ea18 LD1D {Z5.D}, P0/Z, [X19, X3,LSL #3] |
(474) 0x41ea1c FMLA Z1.D, P0/M, Z3.D, Z5.D |
(474) 0x41ea20 LD1D {Z2.D}, P0/Z, [X24, X3,LSL #3] |
(474) 0x41ea24 LD1D {Z3.D}, P0/Z, [X25, X3,LSL #3] |
(474) 0x41ea28 FSUB Z0.D, Z0.D, Z2.D |
(474) 0x41ea2c FSUB Z1.D, Z1.D, Z3.D |
(474) 0x41ea30 LD1D {Z2.D}, P0/Z, [X22, X3,LSL #3] |
(474) 0x41ea34 LD1D {Z3.D}, P0/Z, [X23, X3,LSL #3] |
(474) 0x41ea38 FDIV Z0.D, P0/M, Z0.D, Z2.D |
(474) 0x41ea3c FDIV Z1.D, P0/M, Z1.D, Z3.D |
(474) 0x41ea40 ST1D {Z0.D}, P0, [X26, X3,LSL #3] |
(474) 0x41ea44 ST1D {Z1.D}, P0, [X19, X3,LSL #3] |
(474) 0x41ea48 ADD X3, X3, X14 |
(474) 0x41ea4c CMP X21, X3 |
(474) 0x41ea50 B.NE 41ea00 |
(472) 0x41ea54 CBZ X5, 41e94c |
(472) 0x41ea58 MADD X5, X18, X13, X4 |
(472) 0x41ea5c MADD X18, X18, X8, X4 |
(472) 0x41ea60 ORR X3, XZR, XZR |
(472) 0x41ea64 SUB X18, X18, X0 |
(472) 0x41ea68 SUB X5, X5, X0 |
(472) 0x41ea6c UBFM X0, X18, #61, #60 |
(472) 0x41ea70 ADD X5, X17, X5,LSL #3 |
(472) 0x41ea74 ADD X18, X1, X0 |
(472) 0x41ea78 ADD X17, X17, X0 |
(472) 0x41ea7c ADD X16, X16, X0 |
(472) 0x41ea80 ADD X15, X15, X0 |
(472) 0x41ea84 ADD W0, W2, #1 |
(473) 0x41ea88 LDR D0, [X5, X3] |
(473) 0x41ea8c LDR D1, [X15, X3] |
(473) 0x41ea90 LDR D2, [X16, X3] |
(473) 0x41ea94 SUB W0, W0, #1 |
(473) 0x41ea98 CMP W0, #1 |
(473) 0x41ea9c FMADD D0, D1, D2, D0 |
(473) 0x41eaa0 LDR D1, [X17, X3] |
(473) 0x41eaa4 FSUB D0, D0, S1 |
(473) 0x41eaa8 LDR D1, [X18, X3] |
(473) 0x41eaac FDIV D0, D0, D1 |
(473) 0x41eab0 STR D0, [X16, X3] |
(473) 0x41eab4 ADD X3, X3, #8 |
(473) 0x41eab8 B.HI 41ea88 |
(472) 0x41eabc B 41e94c |
0x41eac0 ORR X0, XZR, XZR |
0x41eac4 ORR W1, WZR, W29 |
0x41eac8 BL 404d30 |
0x41eacc ORR X0, XZR, XZR |
0x41ead0 ORR W1, WZR, W29 |
0x41ead4 BL 404900 |
0x41ead8 LDP X20, X19, [SP, #336] |
0x41eadc LDP X22, X21, [SP, #320] |
0x41eae0 LDP X24, X23, [SP, #304] |
0x41eae4 LDP X26, X25, [SP, #288] |
0x41eae8 LDP X28, X27, [SP, #272] |
0x41eaec LDP X29, X30, [SP, #256] |
0x41eaf0 ADD SP, SP, #352 |
0x41eaf4 RET |
0x41eaf8 HINT #0 |
0x41eafc HINT #0 |
| Path / |
| Source file and lines | advec_mom_kernel.f90-pp.f90:79-254 |
| Module | exec |
| nb instructions | 564 |
| loop length | 2256 |
| nb stack references | 0 |
| front end | 69.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 35.50 | 35.50 | 81.25 | 81.25 | 81.25 | 81.25 | 3.50 | 3.50 | 3.50 | 3.50 | 57.33 | 57.33 | 57.33 | 30.00 | 30.00 |
| cycles | 35.50 | 35.50 | 81.25 | 81.25 | 81.25 | 81.25 | 3.50 | 3.50 | 3.50 | 3.50 | 57.33 | 57.33 | 57.33 | 30.00 | 30.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 69.25 |
| Overall L1 | 81.25 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB SP, SP, #352 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP X29, X30, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X28, X27, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X26, X25, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X24, X23, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X22, X21, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X20, X19, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W29, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X20, XZR, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR W29, [SP, #60] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W8, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.HI 41d988 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x858> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X9, <45416c> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X9, X9, #3420 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADR X10, 41d184 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x54> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDRH W11, [X9, X8,LSL #1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X10, X10, X11,LSL #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BR X10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #252 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #248 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #244 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #252] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #240 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #244] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W8, [SP, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X15, [SP, #248] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W15, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W8, [SP, #244] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W8, W8, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X10, X9, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W12, W9, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W11, W10, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X10, X11, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W9, W12, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W12, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X12, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD X11, X11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41d230 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x100> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #236 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #232 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #228 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #236] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #228] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W8, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #232] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #228] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X11, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W13, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41d454 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x324> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #220 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #216 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #212 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #220] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #208 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #212] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W8, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #212] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X11, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W13, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41d670 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x540> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #204 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #200 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #196 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #204] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #196] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W8, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #200] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #196] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X11, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W13, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41d858 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x728> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X20, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.EQ 41db6c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xa3c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CMP W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 41ead8 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x19a8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X20, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 41e2c8 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1198> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #188 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #184 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #188] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X5, SP, #180 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #176 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #180] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41dd5c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xc2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #180] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41dd5c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xc2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTD X14, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FMOV D0, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FDUP Z1.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X15, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X11, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W13, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X13, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41da70 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x940> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [X20, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 41e6cc <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x159c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #124 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #120 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #124] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X5, SP, #116 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #112 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #116] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X0, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W0, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e00c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xedc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W8, [SP, #116] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W8, W8, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e00c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xedc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X10, X9, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTD X12, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FMOV D0, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FDUP Z1.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ADD W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X13, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W11, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W11, W11, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X11, X11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41dc30 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xb00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #172 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #168 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #164 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #172] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #160 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #164] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e2b0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #164] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e2b0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTD X14, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FMOV D0, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FDUP Z1.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X15, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X30, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W22, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X13, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X27, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W22, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X27, X30, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B 41de30 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xd00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #108 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #104 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #100 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #100] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e6b4 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1584> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #100] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e6b4 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1584> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTD X14, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FMOV D0, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FDUP Z1.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X13, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X15, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X22, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W12, W12, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X22, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W28, W12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X30, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W28, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR X30, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B 41e0dc <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xfac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #156 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #152 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #156] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X5, SP, #148 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #144 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #148] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e4c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1390> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #148] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e4c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1390> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| FMOV D0, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| FMOV D1, #2.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W10, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| FMOV D2, #6.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| SUB W14, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W13, W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X12, X13, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X13, X13, #61, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W14, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W14, W14, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41e36c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x123c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #140 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #136 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #132 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #140] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #128 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #132] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #132] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTW X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X14, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X10, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W12, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41e570 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1440> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #92 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #88 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #92] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X5, SP, #84 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #80 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #84] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e8a8 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1778> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #84] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e8a8 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1778> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| FMOV D0, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| FMOV D1, #2.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X10, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| FMOV D2, #6.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| SUB W12, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41e770 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1640> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #76 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #72 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #68 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #76] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #64 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #68] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #68] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTW X14, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X13, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X10, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W12, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41e95c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x182c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X20, X19, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X22, X21, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X24, X23, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X26, X25, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X28, X27, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X29, X30, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ADD SP, SP, #352 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 |
| Source file and lines | advec_mom_kernel.f90-pp.f90:79-254 |
| Module | exec |
| nb instructions | 564 |
| loop length | 2256 |
| nb stack references | 0 |
| front end | 69.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 35.50 | 35.50 | 81.25 | 81.25 | 81.25 | 81.25 | 3.50 | 3.50 | 3.50 | 3.50 | 57.33 | 57.33 | 57.33 | 30.00 | 30.00 |
| cycles | 35.50 | 35.50 | 81.25 | 81.25 | 81.25 | 81.25 | 3.50 | 3.50 | 3.50 | 3.50 | 57.33 | 57.33 | 57.33 | 30.00 | 30.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 69.25 |
| Overall L1 | 81.25 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB SP, SP, #352 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP X29, X30, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X28, X27, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X26, X25, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X24, X23, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X22, X21, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X20, X19, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W29, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X20, XZR, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR W29, [SP, #60] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W8, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.HI 41d988 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x858> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X9, <45416c> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X9, X9, #3420 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADR X10, 41d184 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x54> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDRH W11, [X9, X8,LSL #1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X10, X10, X11,LSL #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BR X10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #252 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #248 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #244 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #252] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #240 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #244] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W8, [SP, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X15, [SP, #248] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W15, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W8, [SP, #244] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W8, W8, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X10, X9, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W12, W9, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W11, W10, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X10, X11, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W9, W12, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W12, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X12, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD X11, X11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41d230 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x100> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #236 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #232 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #228 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #236] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #228] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W8, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #232] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #228] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X11, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W13, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41d454 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x324> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #220 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #216 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #212 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #220] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #208 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #212] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W8, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #212] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X11, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W13, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41d670 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x540> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #204 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #200 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #196 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #204] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #196] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W8, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #200] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #196] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X11, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W13, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41d858 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x728> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X20, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.EQ 41db6c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xa3c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CMP W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 41ead8 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x19a8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X20, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 41e2c8 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1198> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #188 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #184 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #188] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X5, SP, #180 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #176 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #180] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41dd5c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xc2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #180] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41dd5c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xc2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTD X14, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FMOV D0, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FDUP Z1.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X15, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X11, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W13, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X13, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41da70 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x940> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [X20, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 41e6cc <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x159c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #124 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #120 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #124] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X5, SP, #116 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #112 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #116] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X0, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W0, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e00c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xedc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W8, [SP, #116] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W8, W8, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e00c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xedc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X10, X9, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTD X12, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FMOV D0, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FDUP Z1.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ADD W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X13, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W11, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W11, W11, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W10, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X11, X11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41dc30 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xb00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #172 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #168 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #164 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #172] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #160 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #164] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e2b0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #164] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e2b0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTD X14, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FMOV D0, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FDUP Z1.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X15, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W10, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W11, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W13, W10, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W12, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X30, X12, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W13, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W22, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X13, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X27, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W22, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X27, X30, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B 41de30 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xd00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #108 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #104 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #100 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W9, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #100] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e6b4 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1584> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #100] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e6b4 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1584> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTD X14, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FMOV D0, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FDUP Z1.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X13, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X15, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X22, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W12, W12, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X22, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W28, W12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X30, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W28, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR X30, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B 41e0dc <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xfac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #156 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #152 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #156] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X5, SP, #148 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #144 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #148] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e4c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1390> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #148] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e4c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1390> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| FMOV D0, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| FMOV D1, #2.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W10, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| FMOV D2, #6.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| SUB W14, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W13, W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X12, X13, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X13, X13, #61, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W14, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W14, W14, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41e36c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x123c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #140 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #136 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #132 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #140] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #128 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #132] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #132] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTW X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X14, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X10, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W12, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41e570 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1440> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #92 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #88 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #92] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X5, SP, #84 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #80 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #84] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41e8a8 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1778> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #84] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41e8a8 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1778> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| FMOV D0, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| FMOV D1, #2.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X10, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| FMOV D2, #6.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| SUB W12, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41e770 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1640> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X8, X9, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, SP, #76 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, SP, #72 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #68 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR WZR, [SP, #76] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, SP, #64 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W21, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR W21, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD W19, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP W19, W8, [SP, #68] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 404c10 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDRSW X8, [SP, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W9, [SP, #68] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUBS W9, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.MI 41eac0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1990> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X10, [X20, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CNTW X14, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X13, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W12, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDRSW X10, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W12, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W11, W12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X12, X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41e95c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x182c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404d30 <@plt_start@+0x460> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W1, WZR, W29 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 404900 <@plt_start@+0x30> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X20, X19, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X22, X21, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X24, X23, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X26, X25, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X28, X27, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X29, X30, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ADD SP, SP, #352 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼advec_mom_kernel– | 34.41 | 46.64 |
| ▼Loop 476 - advec_mom_kernel.f90-pp.f90:214-242 - exec– | 3.86 | 5.21 |
| ○Loop 475 - advec_mom_kernel.f90-pp.f90:214-242 - exec | 0 | 0.01 |
| ▼Loop 504 - advec_mom_kernel.f90-pp.f90:85-89 - exec– | 0.01 | 0.01 |
| ○Loop 506 - advec_mom_kernel.f90-pp.f90:86-87 - exec | 2.79 | 3.77 |
| ○Loop 505 - advec_mom_kernel.f90-pp.f90:86-88 - exec | 0 | 0 |
| ▼Loop 501 - advec_mom_kernel.f90-pp.f90:95-99 - exec– | 0.01 | 0.01 |
| ○Loop 503 - advec_mom_kernel.f90-pp.f90:96-97 - exec | 2.71 | 3.66 |
| ○Loop 502 - advec_mom_kernel.f90-pp.f90:96-98 - exec | 0 | 0 |
| ▼Loop 480 - advec_mom_kernel.f90-pp.f90:151-178 - exec– | 0.01 | 0.02 |
| ○Loop 481 - advec_mom_kernel.f90-pp.f90:152-177 - exec | 3.62 | 4.88 |
| ▼Loop 482 - advec_mom_kernel.f90-pp.f90:138-146 - exec– | 0.01 | 0.01 |
| ○Loop 484 - advec_mom_kernel.f90-pp.f90:140-144 - exec | 2.79 | 3.77 |
| ○Loop 483 - advec_mom_kernel.f90-pp.f90:140-145 - exec | 0 | 0.01 |
| ▼Loop 472 - advec_mom_kernel.f90-pp.f90:247-250 - exec– | 0.01 | 0.01 |
| ○Loop 474 - advec_mom_kernel.f90-pp.f90:248-248 - exec | 4.7 | 6.35 |
| ○Loop 473 - advec_mom_kernel.f90-pp.f90:248-249 - exec | 0 | 0 |
| ▼Loop 485 - advec_mom_kernel.f90-pp.f90:203-210 - exec– | 0.01 | 0.01 |
| ○Loop 487 - advec_mom_kernel.f90-pp.f90:204-208 - exec | 3.09 | 4.18 |
| ○Loop 486 - advec_mom_kernel.f90-pp.f90:204-209 - exec | 0 | 0.01 |
| ▼Loop 477 - advec_mom_kernel.f90-pp.f90:183-186 - exec– | 0 | 0.01 |
| ○Loop 479 - advec_mom_kernel.f90-pp.f90:184-184 - exec | 4.49 | 6.07 |
| ○Loop 478 - advec_mom_kernel.f90-pp.f90:184-185 - exec | 0 | 0 |
| ▼Loop 488 - advec_mom_kernel.f90-pp.f90:193-198 - exec– | 0 | 0 |
| ▼Loop 490 - advec_mom_kernel.f90-pp.f90:193-198 - exec– | 0 | 0.01 |
| ○Loop 491 - advec_mom_kernel.f90-pp.f90:195-195 - exec | 1.06 | 1.43 |
| ○Loop 489 - advec_mom_kernel.f90-pp.f90:195-197 - exec | 0 | 0 |
| ▼Loop 492 - advec_mom_kernel.f90-pp.f90:128-133 - exec– | 0 | 0.01 |
| ○Loop 494 - advec_mom_kernel.f90-pp.f90:130-130 - exec | 1.05 | 1.42 |
| ○Loop 493 - advec_mom_kernel.f90-pp.f90:130-132 - exec | 0 | 0 |
| ▼Loop 498 - advec_mom_kernel.f90-pp.f90:105-109 - exec– | 0 | 0.01 |
| ○Loop 500 - advec_mom_kernel.f90-pp.f90:106-107 - exec | 2.14 | 2.89 |
| ○Loop 499 - advec_mom_kernel.f90-pp.f90:106-108 - exec | 0 | 0 |
| ▼Loop 495 - advec_mom_kernel.f90-pp.f90:115-119 - exec– | 0 | 0.01 |
| ○Loop 497 - advec_mom_kernel.f90-pp.f90:116-117 - exec | 2.04 | 2.76 |
| ○Loop 496 - advec_mom_kernel.f90-pp.f90:116-118 - exec | 0 | 0 |
