OV - exec - Function __nv_pdv_kernel_module_pdv_kernel__F1L67_1

	Function: __nv_pdv_kernel_module_pdv_kernel__F1L67_1_	Module: exec	Source: PdV_kernel.f90-pp.f90:67-143 [...]	Coverage: 15.23%

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90: 67 - 143

--------------------------------------------------------------------------------

67: # 67 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

68:     !$OMP PARALLEL

69: # 69 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

70:     IF(predict)THEN

71: # 71 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

72:       !$OMP DO PRIVATE(right_flux,left_flux,top_flux,bottom_flux,total_flux,min_cell_volume, &

73:       !$OMP            energy_change,recip_volume,volume_change_s)

74:       DO k=y_min,y_max

75:       !$OMP SIMD

76:         DO j=x_min,x_max

77: # 77 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

78:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

79:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

80:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

81:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

82:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

83:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

84:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

85:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

86:           total_flux=right_flux-left_flux+top_flux-bottom_flux

87: # 87 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

[...]

93:

94:           recip_volume=1.0/volume(j,k)

95: # 95 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

96:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

97: # 97 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

98:           energy1(j,k)=energy0(j,k)-energy_change

99: # 99 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

100:           density1(j,k)=density0(j,k)*volume_change_s

101: # 101 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

102:         ENDDO

[...]

109:       !$OMP            energy_change,recip_volume,volume_change_s)

110:       DO k=y_min,y_max

111:       !$OMP SIMD

112:         DO j=x_min,x_max

113: # 113 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

114:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

115:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

116:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

117:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

118:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

119:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

120:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

121:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

122:           total_flux=right_flux-left_flux+top_flux-bottom_flux

123: # 123 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

[...]

129:

130:           recip_volume=1.0/volume(j,k)

131: # 131 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

132:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

133: # 133 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

134:           energy1(j,k)=energy0(j,k)-energy_change

135: # 135 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

136:           density1(j,k)=density0(j,k)*volume_change_s

137: # 137 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

138:         ENDDO

139:       ENDDO

140:     !$OMP END DO

141: # 141 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

142:     ENDIF

143: # 143 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

0x418100 SUB	SP, SP, #384

0x418104 STP	X29, X30, [SP, #288]

0x418108 STP	X28, X27, [SP, #304]

0x41810c STP	X26, X25, [SP, #320]

0x418110 STP	X24, X23, [SP, #336]

0x418114 STP	X22, X21, [SP, #352]

0x418118 STP	X20, X19, [SP, #368]

0x41811c LDR	X8, [X2]

0x418120 LDR	W1, [X0]

0x418124 ORR	X20, XZR, X2

0x418128 LDRB	W8, [X8]

0x41812c STR	W1, [SP, #36]

0x418130 TBNZ	W8, #0, 41864c

0x418134 LDP	X8, X9, [X20, #8]

0x418138 ORR	X0, XZR, XZR

0x41813c ADD	X3, SP, #268

0x418140 ADD	X4, SP, #264

0x418144 ADD	X5, SP, #260

0x418148 STR	WZR, [SP, #268]

0x41814c LDR	W8, [X8]

0x418150 LDR	W19, [X9]

0x418154 ADD	X6, SP, #256

0x418158 MOVZ	W2, #34

0x41815c MOVZ	W7, #1

0x418160 STR	W8, [SP, #264]

0x418164 MOVZ	W8, #1

0x418168 STR	W19, [SP, #260]

0x41816c STR	W8, [SP, #256]

0x418170 STR	W8, [SP]

0x418174 BL	404c10

0x418178 LDRSW	X9, [SP, #264]

0x41817c CMP	W9, W19

0x418180 B.GT	418aa8

0x418184 LDR	W8, [SP, #260]

0x418188 SUBS	W8, W8, W9

0x41818c B.MI	418aa8

0x418190 LDP	X11, X10, [X20, #24]

0x418194 FMOV	V0.2D, #0.2500000

0x418198 CNTD	X13, ALL

0x41819c FMOV	D1, #0.2500000

0x4181a0 PTRUE	P0.D, ALL

0x4181a4 ADD	W8, W8, #1

0x4181a8 MOVZ	X14, #1

0x4181ac LDR	W10, [X10]

0x4181b0 LDRSW	X24, [X11]

0x4181b4 FMOV	D2, #-1.0000000

0x4181b8 FDUP	Z3.D, #80

0x4181bc FDUP	Z4.D, #112

0x4181c0 SUB	W15, W10, W24

0x4181c4 STR	X24, [SP, #24]

0x4181c8 ADDS	W16, W15, #1

0x4181cc STR	W15, [SP, #240]

0x4181d0 CSINC	W10, WZR, WZR, #0

0x4181d4 STR	W16, [SP, #232]

0x4181d8 SUB	W10, W16, W10

0x4181dc ADD	X25, X10, #1

0x4181e0 STR	X25, [SP, #224]

0x4181e4 B	4181f8

(53) 0x4181e8 ADD	X27, X9, #1

(53) 0x4181ec ORR	X9, XZR, X27

(53) 0x4181f0 SUBS	W8, W8, #1

(53) 0x4181f4 B.LE	418aa8

(53) 0x4181f8 TBNZ	W15, #31, 4181e8

0x4181fc LDR	X10, [X20, #64]

0x418200 LDP	X12, X0, [X20, #144]

0x418204 ADD	X27, X9, #1

0x418208 LDP	X11, X5, [X20, #104]

0x41820c ORR	X29, XZR, X24

0x418210 CMP	X25, X13

0x418214 LDR	X4, [X20, #40]

0x418218 LDR	X26, [X20, #200]

0x41821c LDP	X6, X18, [X20, #264]

0x418220 LDP	X7, X21, [X20, #216]

0x418224 LDP	X23, X19, [X20, #232]

0x418228 LDP	X1, X22, [X20, #248]

0x41822c LDR	X10, [X10]

0x418230 LDR	D5, [X12]

0x418234 LDR	X2, [X11]

0x418238 MADD	X12, X27, X10, XZR

0x41823c MADD	X3, X10, X9, XZR

0x418240 LDR	X10, [X20, #168]

0x418244 LDR	X10, [X10]

0x418248 MADD	X11, X10, X9, XZR

0x41824c LDP	X9, X28, [X20, #184]

0x418250 LDR	X17, [X9]

0x418254 MADD	X9, X27, X10, XZR

0x418258 ORR	W10, WZR, W16

0x41825c B.CC	4184d0

0x418260 UDIV	X15, X25, X13

0x418264 STR	X9, [SP, #248]

0x418268 ADD	X9, X24, X12

0x41826c ADD	X10, X24, X3

0x418270 STR	X11, [SP, #96]

0x418274 ADD	X11, X24, X11

0x418278 STR	W8, [SP, #112]

0x41827c ORR	X8, XZR, X13

0x418280 STR	X3, [SP, #128]

0x418284 STR	X27, [SP, #216]

0x418288 STP	X28, X12, [SP, #64]

0x41828c STR	X2, [SP, #144]

0x418290 ORR	X29, XZR, X17

0x418294 SUB	X9, X9, X2

0x418298 SUB	X10, X10, X2

0x41829c SUB	X11, X11, X17

0x4182a0 STR	X18, [SP, #80]

0x4182a4 ORR	X13, XZR, X24

0x4182a8 ORR	X24, XZR, X0

0x4182ac STP	X1, X6, [SP, #168]

0x4182b0 ORR	X30, XZR, XZR

0x4182b4 STP	X19, X4, [SP, #152]

0x4182b8 DUP	Z6.D, Z5.D[0]

0x4182bc STR	X22, [SP, #136]

0x4182c0 STR	X5, [SP, #208]

0x4182c4 STR	X29, [SP, #88]

0x4182c8 UBFM	X9, X9, #61, #60

0x4182cc UBFM	X3, X10, #61, #60

0x4182d0 UBFM	X27, X11, #61, #60

0x4182d4 STR	X24, [SP, #120]

0x4182d8 ADD	X11, X28, X9

0x4182dc ADD	X10, X18, X9

0x4182e0 ADD	X12, X5, X9

0x4182e4 ADD	X9, X6, X9

0x4182e8 ADD	X17, X28, X3

0x4182ec ADD	X18, X18, X3

0x4182f0 ADD	X0, X4, X3

0x4182f4 ADD	X2, X5, X3

0x4182f8 ADD	X3, X6, X3

0x4182fc ADD	X4, X22, X27

0x418300 ADD	X22, X1, X27

0x418304 MADD	X6, X15, X8, XZR

0x418308 SUB	X15, X25, X6

0x41830c STR	X15, [SP, #40]

0x418310 ADD	X15, X6, X13

0x418314 STR	X15, [SP, #48]

0x418318 SUB	W15, W16, W6

0x41831c ORR	X16, XZR, X7

0x418320 ADD	X7, X19, X27

0x418324 STR	W15, [SP, #60]

0x418328 ORR	X15, XZR, X23

0x41832c STP	X16, X21, [SP, #184]

0x418330 ADD	X23, X16, X27

0x418334 ORR	X16, XZR, X26

0x418338 ADD	X26, X21, X27

0x41833c STR	X15, [SP, #200]

0x418340 ADD	X28, X15, X27

0x418344 LDR	X15, [SP, #248]

0x418348 ADD	X25, X16, X27

0x41834c ADD	X27, X24, X27

0x418350 ADD	X15, X13, X15

0x418354 ORR	X13, XZR, X8

0x418358 STR	X16, [SP, #104]

0x41835c SUB	X15, X15, X29

0x418360 ADD	X15, X24, X15,LSL #3

(54) 0x418364 UBFM	X16, X30, #61, #60

(54) 0x418368 ADD	X1, X9, X16

(54) 0x41836c ADD	X5, X3, X16

(54) 0x418370 ADD	X19, X12, X16

(54) 0x418374 ADD	X21, X2, X16

(54) 0x418378 LD1D	{Z7.D}, P0/Z, [X1, MUL VL]

(54) 0x41837c LD1D	{Z16.D}, P0/Z, [X5, MUL VL]

(54) 0x418380 ADD	X24, X0, X16

(54) 0x418384 FADD	Z7.D, Z7.D, Z16.D

(54) 0x418388 LD1D	{Z16.D}, P0/Z, [X19, MUL VL]

(54) 0x41838c LD1D	{Z17.D}, P0/Z, [X21, MUL VL]

(54) 0x418390 FADD	Z16.D, Z16.D, Z17.D

(54) 0x418394 FADD	Z7.D, Z7.D, Z16.D

(54) 0x418398 LD1D	{Z16.D}, P0/Z, [X24, MUL VL]

(54) 0x41839c LD1D	{Z17.D}, P0/Z, [X5, X14,LSL #3]

(54) 0x4183a0 LD1D	{Z18.D}, P0/Z, [X21, X14,LSL #3]

(54) 0x4183a4 FMUL	Z7.D, Z7.D, Z16.D

(54) 0x4183a8 LD1D	{Z16.D}, P0/Z, [X1, X14,LSL #3]

(54) 0x4183ac ADD	X1, X18, X16

(54) 0x4183b0 FMUL	Z7.D, Z7.D, Z3.D

(54) 0x4183b4 FADD	Z16.D, Z16.D, Z17.D

(54) 0x4183b8 LD1D	{Z17.D}, P0/Z, [X19, X14,LSL #3]

(54) 0x4183bc FMUL	Z7.D, Z6.D, Z7.D

(54) 0x4183c0 FADD	Z17.D, Z17.D, Z18.D

(54) 0x4183c4 FADD	Z16.D, Z16.D, Z17.D

(54) 0x4183c8 LD1D	{Z17.D}, P0/Z, [X24, X14,LSL #3]

(54) 0x4183cc FMUL	Z16.D, Z17.D, Z16.D

(54) 0x4183d0 LD1D	{Z17.D}, P0/Z, [X1, X14,LSL #3]

(54) 0x4183d4 LD1D	{Z18.D}, P0/Z, [X1, MUL VL]

(54) 0x4183d8 ADD	X1, X17, X16

(54) 0x4183dc FMUL	Z16.D, Z16.D, Z3.D

(54) 0x4183e0 FADD	Z17.D, Z17.D, Z18.D

(54) 0x4183e4 LD1D	{Z18.D}, P0/Z, [X1, X14,LSL #3]

(54) 0x4183e8 LD1D	{Z19.D}, P0/Z, [X1, MUL VL]

(54) 0x4183ec ADD	X1, X10, X16

(54) 0x4183f0 ADD	X16, X11, X16

(54) 0x4183f4 FNMLS	Z7.D, P0/M, Z6.D, Z16.D

(54) 0x4183f8 FADD	Z18.D, Z18.D, Z19.D

(54) 0x4183fc FADD	Z17.D, Z17.D, Z18.D

(54) 0x418400 LD1D	{Z18.D}, P0/Z, [X27, X30,LSL #3]

(54) 0x418404 FMUL	Z17.D, Z17.D, Z18.D

(54) 0x418408 LD1D	{Z18.D}, P0/Z, [X1, X14,LSL #3]

(54) 0x41840c LD1D	{Z19.D}, P0/Z, [X1, MUL VL]

(54) 0x418410 FMUL	Z17.D, Z17.D, Z3.D

(54) 0x418414 FADD	Z18.D, Z18.D, Z19.D

(54) 0x418418 LD1D	{Z19.D}, P0/Z, [X16, X14,LSL #3]

(54) 0x41841c LD1D	{Z20.D}, P0/Z, [X16, MUL VL]

(54) 0x418420 LD1D	{Z16.D}, P0/Z, [X25, X30,LSL #3]

(54) 0x418424 FADD	Z19.D, Z19.D, Z20.D

(54) 0x418428 LD1D	{Z20.D}, P0/Z, [X23, X30,LSL #3]

(54) 0x41842c FADD	Z18.D, Z18.D, Z19.D

(54) 0x418430 LD1D	{Z19.D}, P0/Z, [X15, X30,LSL #3]

(54) 0x418434 FMUL	Z18.D, Z19.D, Z18.D

(54) 0x418438 LD1D	{Z19.D}, P0/Z, [X26, X30,LSL #3]

(54) 0x41843c FMUL	Z18.D, Z18.D, Z3.D

(54) 0x418440 FMLA	Z7.D, P0/M, Z6.D, Z18.D

(54) 0x418444 LD1D	{Z18.D}, P0/Z, [X28, X30,LSL #3]

(54) 0x418448 FDIV	Z20.D, P0/M, Z20.D, Z19.D

(54) 0x41844c FMLS	Z7.D, P0/M, Z6.D, Z17.D

(54) 0x418450 FDIV	Z18.D, P0/M, Z18.D, Z19.D

(54) 0x418454 FADD	Z17.D, Z16.D, Z7.D

(54) 0x418458 FDIVR	Z17.D, P0/M, Z17.D, Z16.D

(54) 0x41845c FDIVR	Z16.D, P0/M, Z16.D, Z4.D

(54) 0x418460 FADD	Z18.D, Z18.D, Z20.D

(54) 0x418464 FMUL	Z7.D, Z7.D, Z18.D

(54) 0x418468 LD1D	{Z18.D}, P0/Z, [X22, X30,LSL #3]

(54) 0x41846c FMSB	Z7.D, P0/M, Z16.D, Z18.D

(54) 0x418470 ST1D	{Z7.D}, P0, [X7, X30,LSL #3]

(54) 0x418474 FMUL	Z7.D, Z19.D, Z17.D

(54) 0x418478 ST1D	{Z7.D}, P0, [X4, X30,LSL #3]

(54) 0x41847c ADD	X30, X30, X13

(54) 0x418480 CMP	X6, X30

(54) 0x418484 B.NE	418364

0x418488 LDR	X24, [SP, #24]

0x41848c LDR	W15, [SP, #240]

0x418490 LDR	W16, [SP, #232]

0x418494 LDP	X27, X25, [SP, #216]

0x418498 LDP	X23, X5, [SP, #200]

0x41849c LDP	X7, X21, [SP, #184]

0x4184a0 LDR	W8, [SP, #112]

0x4184a4 LDP	X1, X6, [SP, #168]

0x4184a8 LDP	X19, X4, [SP, #152]

0x4184ac LDP	X22, X2, [SP, #136]

0x4184b0 LDP	X0, X3, [SP, #120]

0x4184b4 LDP	X11, X26, [SP, #96]

0x4184b8 LDP	X18, X17, [SP, #80]

0x4184bc LDP	X28, X12, [SP, #64]

0x4184c0 LDR	X9, [SP, #248]

0x4184c4 LDR	W10, [SP, #60]

0x4184c8 LDP	X30, X29, [SP, #40]

0x4184cc CBZ	X30, 4181ec

0x4184d0 ADD	X11, X29, X11

0x4184d4 ADD	X9, X29, X9

0x4184d8 ADD	X16, X18, #8

0x4184dc ADD	X15, X28, #8

0x4184e0 ORR	X25, XZR, X19

0x4184e4 ADD	W19, W10, #1

0x4184e8 ADD	X10, X29, X12

0x4184ec ORR	X28, XZR, X22

0x4184f0 ORR	X30, XZR, XZR

0x4184f4 SUB	X18, X11, X17

0x4184f8 UBFM	X22, X18, #61, #60

0x4184fc SUB	X9, X9, X17

0x418500 SUB	X12, X10, X2

0x418504 ADD	X10, X0, X9,LSL #3

0x418508 UBFM	X17, X12, #61, #60

0x41850c ADD	X18, X0, X22

0x418510 ADD	X0, X26, X22

0x418514 ORR	X26, XZR, X1

0x418518 ADD	X1, X29, X3

0x41851c ADD	X9, X15, X17

0x418520 ADD	X11, X16, X17

0x418524 ADD	X12, X5, X17

0x418528 ADD	X17, X6, X17

0x41852c ADD	X7, X7, X22

0x418530 ADD	X21, X21, X22

0x418534 SUB	X1, X1, X2

0x418538 UBFM	X1, X1, #61, #60

0x41853c ADD	X2, X15, X1

0x418540 ADD	X3, X16, X1

0x418544 ADD	X4, X4, X1

0x418548 ADD	X16, X5, X1

0x41854c ADD	X1, X6, X1

0x418550 ADD	X5, X28, X22

0x418554 ADD	X15, X25, X22

0x418558 ADD	X6, X26, X22

0x41855c ADD	X22, X23, X22

(52) 0x418560 LDR	Q6, [X17, X30]

(52) 0x418564 LDR	Q7, [X1, X30]

(52) 0x418568 LDR	Q16, [X16, X30]

(52) 0x41856c ADD	X23, X3, X30

(52) 0x418570 SUB	W19, W19, #1

(52) 0x418574 LDR	D19, [X7, X30]

(52) 0x418578 CMP	W19, #1

(52) 0x41857c FADD	V6.2D, V6.2D, V7.2D

(52) 0x418580 LDR	Q7, [X12, X30]

(52) 0x418584 FADD	V7.2D, V7.2D, V16.2D

(52) 0x418588 FADD	V6.2D, V6.2D, V7.2D

(52) 0x41858c LDR	Q7, [X4, X30]

(52) 0x418590 FMUL	V6.2D, V7.2D, V6.2D

(52) 0x418594 LDP	D16, D7, [X23, #1016]

(52) 0x418598 ADD	X23, X2, X30

(52) 0x41859c FMUL	V6.2D, V6.2D, V0.2D

(52) 0x4185a0 FADD	D7, D7, D16

(52) 0x4185a4 LDP	D17, D16, [X23, #1016]

(52) 0x4185a8 ADD	X23, X11, X30

(52) 0x4185ac FMUL	V6.2D, V6.2D, V5.D[0]

(52) 0x4185b0 FADD	D16, D16, D17

(52) 0x4185b4 FADD	D7, D7, D16

(52) 0x4185b8 LDR	D16, [X18, X30]

(52) 0x4185bc FMUL	D7, D7, D16

(52) 0x4185c0 LDP	D17, D16, [X23, #1016]

(52) 0x4185c4 ADD	X23, X9, X30

(52) 0x4185c8 FMUL	D7, D7, D1

(52) 0x4185cc FADD	D16, D16, D17

(52) 0x4185d0 LDP	D18, D17, [X23, #1016]

(52) 0x4185d4 FADD	D17, D17, D18

(52) 0x4185d8 LDR	D18, [X21, X30]

(52) 0x4185dc FADD	D16, D16, D17

(52) 0x4185e0 LDR	D17, [X10, X30]

(52) 0x4185e4 FDIV	D19, D19, D18

(52) 0x4185e8 FMUL	D16, D17, D16

(52) 0x4185ec DUP	V17.2D, V6.D[1]

(52) 0x4185f0 FSUB	V6.2D, V17.2D, V6.2D

(52) 0x4185f4 LDR	D17, [X22, X30]

(52) 0x4185f8 FMUL	D16, D16, D1

(52) 0x4185fc FMADD	D6, D5, D16, D6

(52) 0x418600 FDIV	D17, D17, D18

(52) 0x418604 FMSUB	D6, D5, D7, D6

(52) 0x418608 LDR	D7, [X0, X30]

(52) 0x41860c FADD	D16, D7, D6

(52) 0x418610 FDIV	D16, D7, D16

(52) 0x418614 FDIV	D7, D2, D7

(52) 0x418618 FADD	D17, D17, D19

(52) 0x41861c FMUL	D6, D6, D17

(52) 0x418620 LDR	D17, [X6, X30]

(52) 0x418624 FMADD	D6, D7, D6, D17

(52) 0x418628 STR	D6, [X15, X30]

(52) 0x41862c FMUL	D6, D18, D16

(52) 0x418630 STR	D6, [X5, X30]

(52) 0x418634 ADD	X30, X30, #8

(52) 0x418638 B.HI	418560

0x41863c LDR	W16, [SP, #232]

0x418640 LDR	W15, [SP, #240]

0x418644 LDR	X25, [SP, #224]

0x418648 B	4181ec

0x41864c LDP	X8, X9, [X20, #8]

0x418650 ORR	X0, XZR, XZR

0x418654 ADD	X3, SP, #284

0x418658 ADD	X4, SP, #280

0x41865c ADD	X5, SP, #276

0x418660 STR	WZR, [SP, #284]

0x418664 LDR	W8, [X8]

0x418668 LDR	W19, [X9]

0x41866c ADD	X6, SP, #272

0x418670 MOVZ	W2, #34

0x418674 MOVZ	W7, #1

0x418678 STR	W8, [SP, #280]

0x41867c MOVZ	W8, #1

0x418680 STR	W19, [SP, #276]

0x418684 STR	W8, [SP, #272]

0x418688 STR	W8, [SP]

0x41868c BL	404c10

0x418690 LDRSW	X9, [SP, #280]

0x418694 CMP	W9, W19

0x418698 B.GT	418aa8

0x41869c LDR	W8, [SP, #276]

0x4186a0 SUBS	W8, W8, W9

0x4186a4 B.MI	418aa8

0x4186a8 LDP	X11, X10, [X20, #24]

0x4186ac FMOV	V0.2D, #0.2500000

0x4186b0 FMOV	V1.2D, #0.5000000

0x4186b4 CNTD	X13, ALL

0x4186b8 PTRUE	P0.D, ALL

0x4186bc ADD	W8, W8, #1

0x4186c0 MOVZ	X14, #1

0x4186c4 LDR	W10, [X10]

0x4186c8 LDRSW	X21, [X11]

0x4186cc FMOV	D2, #0.2500000

0x4186d0 FMOV	D3, #0.5000000

0x4186d4 FMOV	D4, #-1.0000000

0x4186d8 FDUP	Z5.D, #80

0x4186dc FDUP	Z6.D, #96

0x4186e0 FDUP	Z7.D, #112

0x4186e4 SUB	W7, W10, W21

0x4186e8 STR	X21, [SP, #136]

0x4186ec ADDS	W23, W7, #1

0x4186f0 STR	W7, [SP, #128]

0x4186f4 CSINC	W10, WZR, WZR, #0

0x4186f8 STR	W23, [SP, #120]

0x4186fc SUB	W10, W23, W10

0x418700 ADD	X24, X10, #1

0x418704 STR	X24, [SP, #112]

0x418708 B	41871c

(50) 0x41870c ADD	X15, X9, #1

(50) 0x418710 ORR	X9, XZR, X15

(50) 0x418714 SUBS	W8, W8, #1

(50) 0x418718 B.LE	418aa8

(50) 0x41871c TBNZ	W7, #31, 41870c

0x418720 LDR	X10, [X20, #64]

0x418724 LDP	X12, X16, [X20, #144]

0x418728 ADD	X15, X9, #1

0x41872c LDP	X11, X18, [X20, #104]

0x418730 ORR	X19, XZR, X21

0x418734 ORR	W28, WZR, W23

0x418738 CMP	X24, X13

0x41873c LDR	X29, [X20, #40]

0x418740 LDR	X25, [X20, #200]

0x418744 LDP	X2, X3, [X20, #216]

0x418748 LDP	X4, X26, [X20, #232]

0x41874c LDP	X1, X30, [X20, #248]

0x418750 LDR	X10, [X10]

0x418754 LDR	D16, [X12]

0x418758 LDR	X22, [X11]

0x41875c MADD	X0, X15, X10, XZR

0x418760 MADD	X12, X10, X9, XZR

0x418764 LDR	X10, [X20, #168]

0x418768 LDR	X10, [X10]

0x41876c MADD	X6, X10, X9, XZR

0x418770 LDP	X9, X17, [X20, #184]

0x418774 MADD	X11, X15, X10, XZR

0x418778 LDR	X5, [X9]

0x41877c B.CC	418964

0x418780 ORR	X19, XZR, X17

0x418784 UDIV	X17, X24, X13

0x418788 ADD	X9, X21, X0

0x41878c ADD	X10, X21, X12

0x418790 ORR	W28, WZR, W23

0x418794 ORR	X23, XZR, X11

0x418798 ADD	X11, X21, X6

0x41879c STR	X6, [SP, #208]

0x4187a0 ORR	X6, XZR, X30

0x4187a4 STR	X12, [SP, #176]

0x4187a8 ORR	X27, XZR, XZR

0x4187ac DUP	Z17.D, Z16.D[0]

0x4187b0 STP	X1, X2, [SP, #216]

0x4187b4 STP	X3, X4, [SP, #232]

0x4187b8 STR	X26, [SP, #200]

0x4187bc SUB	X9, X9, X22

0x4187c0 SUB	X10, X10, X22

0x4187c4 SUB	X11, X11, X5

0x4187c8 STP	X19, X0, [SP, #152]

0x4187cc STR	X25, [SP, #248]

0x4187d0 STR	X23, [SP, #168]

0x4187d4 UBFM	X9, X9, #61, #60

0x4187d8 UBFM	X0, X10, #61, #60

0x4187dc UBFM	X7, X11, #61, #60

0x4187e0 ORR	X11, XZR, X29

0x4187e4 ADD	X29, X19, X9

0x4187e8 ADD	X10, X19, X0

0x4187ec ADD	X30, X18, X9

0x4187f0 ADD	X9, X6, X7

0x4187f4 ADD	X1, X1, X7

0x4187f8 ADD	X2, X2, X7

0x4187fc ADD	X3, X3, X7

0x418800 ADD	X4, X4, X7

0x418804 STP	X6, X11, [SP, #184]

0x418808 ADD	X12, X11, X0

0x41880c ADD	X11, X18, X0

0x418810 ADD	X6, X25, X7

0x418814 MADD	X17, X17, X13, XZR

0x418818 ADD	X19, X17, X21

0x41881c ADD	X21, X21, X23

0x418820 SUB	X0, X24, X17

0x418824 STR	X0, [SP, #144]

0x418828 SUB	X21, X21, X5

0x41882c SUB	W28, W28, W17

0x418830 ADD	X0, X26, X7

0x418834 ADD	X7, X16, X7

0x418838 ADD	X21, X16, X21,LSL #3

0x41883c HINT	#0

(51) 0x418840 UBFM	X23, X27, #61, #60

(51) 0x418844 ADD	X24, X30, X23

(51) 0x418848 ADD	X25, X11, X23

(51) 0x41884c ADD	X26, X12, X23

(51) 0x418850 LD1D	{Z18.D}, P0/Z, [X24, MUL VL]

(51) 0x418854 LD1D	{Z19.D}, P0/Z, [X25, MUL VL]

(51) 0x418858 FADD	Z18.D, Z18.D, Z19.D

(51) 0x41885c LD1D	{Z19.D}, P0/Z, [X26, MUL VL]

(51) 0x418860 LD1D	{Z20.D}, P0/Z, [X25, X14,LSL #3]

(51) 0x418864 FADD	Z18.D, Z18.D, Z18.D

(51) 0x418868 FMUL	Z18.D, Z18.D, Z19.D

(51) 0x41886c LD1D	{Z19.D}, P0/Z, [X24, X14,LSL #3]

(51) 0x418870 ADD	X24, X10, X23

(51) 0x418874 ADD	X23, X29, X23

(51) 0x418878 FMUL	Z18.D, Z18.D, Z5.D

(51) 0x41887c FADD	Z19.D, Z19.D, Z20.D

(51) 0x418880 LD1D	{Z20.D}, P0/Z, [X26, X14,LSL #3]

(51) 0x418884 FMUL	Z18.D, Z17.D, Z18.D

(51) 0x418888 FADD	Z19.D, Z19.D, Z19.D

(51) 0x41888c FMUL	Z18.D, P0/M, Z18.D, #0

(51) 0x418890 FMUL	Z19.D, Z20.D, Z19.D

(51) 0x418894 LD1D	{Z20.D}, P0/Z, [X24, X14,LSL #3]

(51) 0x418898 LD1D	{Z21.D}, P0/Z, [X24, MUL VL]

(51) 0x41889c FMUL	Z19.D, Z19.D, Z5.D

(51) 0x4188a0 FADD	Z20.D, Z20.D, Z21.D

(51) 0x4188a4 LD1D	{Z21.D}, P0/Z, [X7, X27,LSL #3]

(51) 0x4188a8 FMUL	Z19.D, Z17.D, Z19.D

(51) 0x4188ac FADD	Z20.D, Z20.D, Z20.D

(51) 0x4188b0 FNMLS	Z18.D, P0/M, Z19.D, Z6.D

(51) 0x4188b4 FMUL	Z20.D, Z20.D, Z21.D

(51) 0x4188b8 LD1D	{Z21.D}, P0/Z, [X23, X14,LSL #3]

(51) 0x4188bc LD1D	{Z22.D}, P0/Z, [X23, MUL VL]

(51) 0x4188c0 LD1D	{Z23.D}, P0/Z, [X2, X27,LSL #3]

(51) 0x4188c4 LD1D	{Z19.D}, P0/Z, [X6, X27,LSL #3]

(51) 0x4188c8 FMUL	Z20.D, Z20.D, Z5.D

(51) 0x4188cc FADD	Z21.D, Z21.D, Z22.D

(51) 0x4188d0 LD1D	{Z22.D}, P0/Z, [X21, X27,LSL #3]

(51) 0x4188d4 FMUL	Z20.D, Z17.D, Z20.D

(51) 0x4188d8 FADD	Z21.D, Z21.D, Z21.D

(51) 0x4188dc FMUL	Z21.D, Z22.D, Z21.D

(51) 0x4188e0 LD1D	{Z22.D}, P0/Z, [X3, X27,LSL #3]

(51) 0x4188e4 FMUL	Z21.D, Z21.D, Z5.D

(51) 0x4188e8 FMUL	Z21.D, Z17.D, Z21.D

(51) 0x4188ec FDIV	Z23.D, P0/M, Z23.D, Z22.D

(51) 0x4188f0 FMLA	Z18.D, P0/M, Z21.D, Z6.D

(51) 0x4188f4 LD1D	{Z21.D}, P0/Z, [X4, X27,LSL #3]

(51) 0x4188f8 FMLS	Z18.D, P0/M, Z20.D, Z6.D

(51) 0x4188fc FDIV	Z21.D, P0/M, Z21.D, Z22.D

(51) 0x418900 FADD	Z20.D, Z19.D, Z18.D

(51) 0x418904 FDIVR	Z20.D, P0/M, Z20.D, Z19.D

(51) 0x418908 FDIVR	Z19.D, P0/M, Z19.D, Z7.D

(51) 0x41890c FADD	Z21.D, Z21.D, Z23.D

(51) 0x418910 FMUL	Z18.D, Z18.D, Z21.D

(51) 0x418914 LD1D	{Z21.D}, P0/Z, [X1, X27,LSL #3]

(51) 0x418918 FMSB	Z18.D, P0/M, Z19.D, Z21.D

(51) 0x41891c ST1D	{Z18.D}, P0, [X0, X27,LSL #3]

(51) 0x418920 FMUL	Z18.D, Z22.D, Z20.D

(51) 0x418924 ST1D	{Z18.D}, P0, [X9, X27,LSL #3]

(51) 0x418928 ADD	X27, X27, X13

(51) 0x41892c CMP	X17, X27

(51) 0x418930 B.NE	418840

0x418934 LDP	X21, X9, [SP, #136]

0x418938 LDR	W7, [SP, #128]

0x41893c LDR	W23, [SP, #120]

0x418940 LDR	X24, [SP, #112]

0x418944 LDP	X4, X25, [SP, #240]

0x418948 LDP	X2, X3, [SP, #224]

0x41894c LDR	X17, [SP, #152]

0x418950 LDP	X6, X1, [SP, #208]

0x418954 LDP	X29, X26, [SP, #192]

0x418958 LDP	X12, X30, [SP, #176]

0x41895c LDP	X0, X11, [SP, #160]

0x418960 CBZ	X9, 418710

0x418964 ADD	X10, X19, X0

0x418968 ADD	X12, X19, X12

0x41896c ADD	X9, X17, #8

0x418970 ADD	W28, W28, #1

0x418974 ADD	X11, X19, X11

0x418978 ORR	X27, XZR, XZR

0x41897c SUB	X10, X10, X22

0x418980 SUB	X12, X12, X22

0x418984 UBFM	X17, X10, #61, #60

0x418988 SUB	X11, X11, X5

0x41898c UBFM	X0, X12, #61, #60

0x418990 ADD	X22, X16, X11,LSL #3

0x418994 ADD	X10, X9, X17

0x418998 ADD	X11, X18, X17

0x41899c ADD	X17, X18, X0

0x4189a0 ADD	X18, X19, X6

0x4189a4 ADD	X12, X9, X0

0x4189a8 ADD	X9, X29, X0

0x4189ac SUB	X18, X18, X5

0x4189b0 UBFM	X6, X18, #61, #60

0x4189b4 ADD	X18, X30, X6

0x4189b8 ADD	X0, X26, X6

0x4189bc ADD	X1, X1, X6

0x4189c0 ADD	X2, X2, X6

0x4189c4 ADD	X3, X3, X6

0x4189c8 ADD	X4, X4, X6

0x4189cc ADD	X5, X25, X6

0x4189d0 ADD	X16, X16, X6

0x4189d4 HINT	#0

0x4189d8 HINT	#0

0x4189dc HINT	#0

(49) 0x4189e0 LDR	Q17, [X11, X27]

(49) 0x4189e4 LDR	Q18, [X17, X27]

(49) 0x4189e8 ADD	X6, X12, X27

(49) 0x4189ec LDR	D21, [X3, X27]

(49) 0x4189f0 SUB	W28, W28, #1

(49) 0x4189f4 CMP	W28, #1

(49) 0x4189f8 LDR	D22, [X2, X27]

(49) 0x4189fc FDIV	D22, D22, D21

(49) 0x418a00 FADD	V17.2D, V17.2D, V18.2D

(49) 0x418a04 LDR	Q18, [X9, X27]

(49) 0x418a08 FADD	V17.2D, V17.2D, V17.2D

(49) 0x418a0c FMUL	V17.2D, V18.2D, V17.2D

(49) 0x418a10 LDP	D19, D18, [X6, #1016]

(49) 0x418a14 ADD	X6, X10, X27

(49) 0x418a18 FMUL	V17.2D, V17.2D, V0.2D

(49) 0x418a1c FADD	D18, D18, D19

(49) 0x418a20 LDR	D19, [X16, X27]

(49) 0x418a24 FMUL	V17.2D, V17.2D, V16.D[0]

(49) 0x418a28 FADD	D18, D18, D18

(49) 0x418a2c FMUL	V17.2D, V17.2D, V1.2D

(49) 0x418a30 FMUL	D18, D18, D19

(49) 0x418a34 LDP	D20, D19, [X6, #1016]

(49) 0x418a38 FMUL	D18, D18, D2

(49) 0x418a3c FADD	D19, D19, D20

(49) 0x418a40 LDR	D20, [X22, X27]

(49) 0x418a44 FMUL	D18, D16, D18

(49) 0x418a48 FADD	D19, D19, D19

(49) 0x418a4c FMUL	D19, D20, D19

(49) 0x418a50 DUP	V20.2D, V17.D[1]

(49) 0x418a54 FSUB	V17.2D, V20.2D, V17.2D

(49) 0x418a58 LDR	D20, [X4, X27]

(49) 0x418a5c FMUL	D19, D19, D2

(49) 0x418a60 FMUL	D19, D16, D19

(49) 0x418a64 FDIV	D20, D20, D21

(49) 0x418a68 FMADD	D17, D19, D3, D17

(49) 0x418a6c FMSUB	D17, D18, D3, D17

(49) 0x418a70 LDR	D18, [X5, X27]

(49) 0x418a74 FADD	D19, D18, D17

(49) 0x418a78 FDIV	D19, D18, D19

(49) 0x418a7c FDIV	D18, D4, D18

(49) 0x418a80 FADD	D20, D20, D22

(49) 0x418a84 FMUL	D17, D17, D20

(49) 0x418a88 LDR	D20, [X1, X27]

(49) 0x418a8c FMADD	D17, D18, D17, D20

(49) 0x418a90 STR	D17, [X0, X27]

(49) 0x418a94 FMUL	D17, D21, D19

(49) 0x418a98 STR	D17, [X18, X27]

(49) 0x418a9c ADD	X27, X27, #8

(49) 0x418aa0 B.HI	4189e0

0x418aa4 B	418710

0x418aa8 LDR	W19, [SP, #36]

0x418aac ORR	X0, XZR, XZR

0x418ab0 ORR	W1, WZR, W19

0x418ab4 BL	404d30

0x418ab8 ORR	X0, XZR, XZR

0x418abc ORR	W1, WZR, W19

0x418ac0 BL	404900

0x418ac4 LDP	X20, X19, [SP, #368]

0x418ac8 LDP	X22, X21, [SP, #352]

0x418acc LDP	X24, X23, [SP, #336]

0x418ad0 LDP	X26, X25, [SP, #320]

0x418ad4 LDP	X28, X27, [SP, #304]

0x418ad8 LDP	X29, X30, [SP, #288]

0x418adc ADD	SP, SP, #384

0x418ae0 RET

0x418ae4 HINT	#0

0x418ae8 HINT	#0

0x418aec HINT	#0

0x418af0 HINT	#0

0x418af4 HINT	#0

0x418af8 HINT	#0

0x418afc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	PdV_kernel.f90-pp.f90:67-143
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90:67-87,93-102,109-123,129-143.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 52.00 to 3.50 cycles (14.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 52.00 to 47.50 cycles (1.09x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 52.00 to 2.00 cycles (26.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 945 bytes. The binary function is storing 484 bytes.

General properties

nb instructions	392
loop length	1568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

47.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.00	9.00	52.00	52.00	52.00	52.00	3.75	3.75	3.75	3.75	48.17	47.83	48.00	27.50	27.50
cycles	9.00	9.00	52.00	52.00	52.00	52.00	3.75	3.75	3.75	3.75	48.17	47.83	48.00	27.50	27.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	47.63
Overall L1	52.00

Vectorization ratios

INT

all	1%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	5%

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

INT+FP

all	3%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 52.00 cycles. At this rate:

18% of peak load performance is reached (18.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 418100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRB W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
TBNZ W8, #0, 41864c <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #268	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #260	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W19, [SP, #260]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 418aa8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [SP, #260]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 418aa8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV V0.2D, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D1, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D2, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDUP Z3.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z4.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
SUB W15, W10, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADDS W16, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR W15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSINC W10, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W10, W16, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4181f8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X0, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X27, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X11, X5, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X29, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X4, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X20, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X6, X18, [X20, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X21, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X19, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X1, X22, [X20, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D5, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X12, X27, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X3, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X11, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X9, X28, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X27, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W10, WZR, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 4184d0 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X25, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
STR X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X24, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X24, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X8, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X12, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X29, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X13, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X1, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X30, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
DUP Z6.D, Z5.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR X22, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X29, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X3, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X28, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X5, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X6, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X28, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X5, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X22, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X6, X15, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X15, X25, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X15, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W15, W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X16, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X19, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W15, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X15, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X16, X21, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X23, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X16, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X21, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X15, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X24, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X15, X15, X29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X24, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X25, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X21, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X1, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X19, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X0, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X26, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X17, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X12, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X29, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBZ X30, 4181ec <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X29, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X29, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X29, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X30, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X11, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X22, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X10, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X0, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X17, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X26, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X29, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X15, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X28, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X25, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X26, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4181ec <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #284	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #276	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #284]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W19, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 418aa8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 418aa8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV V0.2D, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV V1.2D, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X21, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D3, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D4, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDUP Z5.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z6.D, #96	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z7.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
SUB W7, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADDS W23, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR W7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSINC W10, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W23, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W10, W23, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 41871c <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X16, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X15, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X11, X18, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W28, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X29, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X20, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X2, X3, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X4, X26, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X1, X30, [X20, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X22, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X0, X15, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X6, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X9, X17, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X11, X15, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X5, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 418964 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X17, X24, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADD X9, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X21, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W28, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X21, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X6, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z17.D, Z16.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STP X1, X2, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, X4, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X9, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X7, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, X29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X6, X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X12, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X25, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X17, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X19, X17, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X24, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X21, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W28, W28, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X26, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X16, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDP X21, X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X4, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X3, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X17, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X6, X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X0, X11, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBZ X9, 418710 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X19, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W28, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X19, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X17, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X16, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X29, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X6, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X30, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X26, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X25, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 418710 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	PdV_kernel.f90-pp.f90:67-143
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 52.00 to 2.00 cycles (26.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 945 bytes. The binary function is storing 484 bytes.

General properties

nb instructions	392
loop length	1568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

47.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.00	9.00	52.00	52.00	52.00	52.00	3.75	3.75	3.75	3.75	48.17	47.83	48.00	27.50	27.50
cycles	9.00	9.00	52.00	52.00	52.00	52.00	3.75	3.75	3.75	3.75	48.17	47.83	48.00	27.50	27.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	47.63
Overall L1	52.00

Vectorization ratios

INT

all	1%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	5%

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

INT+FP

all	3%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 52.00 cycles. At this rate:

18% of peak load performance is reached (18.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 418100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRB W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
TBNZ W8, #0, 41864c <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #268	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #260	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W19, [SP, #260]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 418aa8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [SP, #260]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 418aa8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV V0.2D, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D1, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D2, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDUP Z3.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z4.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
SUB W15, W10, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADDS W16, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR W15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSINC W10, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W10, W16, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4181f8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X0, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X27, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X11, X5, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X29, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X4, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X20, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X6, X18, [X20, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X21, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X19, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X1, X22, [X20, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D5, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X12, X27, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X3, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X11, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X9, X28, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X27, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W10, WZR, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 4184d0 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X25, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
STR X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X24, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X24, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X8, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X12, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X29, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X13, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X1, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X30, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
DUP Z6.D, Z5.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR X22, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X29, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X3, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X28, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X5, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X6, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X28, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X5, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X22, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X6, X15, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X15, X25, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X15, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W15, W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X16, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X19, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W15, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X15, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X16, X21, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X23, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X16, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X21, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X15, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X24, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X15, X15, X29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X24, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X25, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X21, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X1, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X19, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X0, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X26, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X17, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X12, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X29, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBZ X30, 4181ec <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X29, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X29, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X29, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X30, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X11, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X22, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X10, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X0, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X17, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X26, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X29, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X15, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X28, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X25, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X26, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4181ec <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #284	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #276	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #284]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W19, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 418aa8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 418aa8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV V0.2D, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV V1.2D, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X21, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D3, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D4, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDUP Z5.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z6.D, #96	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z7.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
SUB W7, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADDS W23, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR W7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSINC W10, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W23, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W10, W23, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 41871c <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X16, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X15, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X11, X18, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W28, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X29, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X20, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X2, X3, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X4, X26, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X1, X30, [X20, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X22, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X0, X15, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X6, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X9, X17, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X11, X15, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X5, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 418964 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X17, X24, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADD X9, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X21, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W28, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X21, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X6, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z17.D, Z16.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STP X1, X2, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, X4, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X9, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X7, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, X29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X6, X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X12, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X25, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X17, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X19, X17, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X24, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X21, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W28, W28, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X26, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X16, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDP X21, X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X4, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X3, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X17, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X6, X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X0, X11, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBZ X9, 418710 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X19, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W28, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X19, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X17, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X16, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X29, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X6, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X30, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X26, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X25, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 418710 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼__nv_pdv_kernel_module_pdv_kernel__F1L67_1_–	15.23	20.64
○Loop 54 - PdV_kernel.f90-pp.f90:113-135 - exec	8.48	11.46
○Loop 51 - PdV_kernel.f90-pp.f90:77-99 - exec	6.72	9.08
○Loop 53 - PdV_kernel.f90-pp.f90:111-138 - exec	0	0
○Loop 50 - PdV_kernel.f90-pp.f90:75-102 - exec	0	0
○Loop 49 - PdV_kernel.f90-pp.f90:77-101 - exec	0	0
○Loop 52 - PdV_kernel.f90-pp.f90:113-137 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code