OV - exec - Function __nv_reset_field_kernel_module_reset_field_kernel__F1L47_1

	Function: __nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_	Module: exec	Source: reset_field_kernel.f90-pp.f90:47-68	Coverage: 4.58%

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/reset_field_kernel.f90-pp.f90: 47 - 68

--------------------------------------------------------------------------------

47: # 47 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/reset_field_kernel.f90"

48:     !$OMP PARALLEL

49:     !$OMP DO

50:     DO k=y_min,y_max

51:     !$OMP SIMD

52:       DO j=x_min,x_max

53:         density0(j,k)=density1(j,k)

54:         energy0(j,k)=energy1(j,k)

55:       ENDDO

56:     ENDDO

57:     !$OMP END DO

58: # 58 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/reset_field_kernel.f90"

59:     !$OMP DO

60:     DO k=y_min,y_max+1

61:     !$OMP SIMD

62:       DO j=x_min,x_max+1

63:         xvel0(j,k)=xvel1(j,k)

64:         yvel0(j,k)=yvel1(j,k)

65:       ENDDO

66:     ENDDO

67:   !$OMP END DO

68: # 68 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/reset_field_kernel.f90"

0x42b0f0 SUB	SP, SP, #128

0x42b0f4 STR	X30, [SP, #32]

0x42b0f8 STP	X28, X27, [SP, #48]

0x42b0fc STP	X26, X25, [SP, #64]

0x42b100 STP	X24, X23, [SP, #80]

0x42b104 STP	X22, X21, [SP, #96]

0x42b108 STP	X20, X19, [SP, #112]

0x42b10c LDP	X8, X9, [X2]

0x42b110 LDR	W19, [X0]

0x42b114 ORR	X0, XZR, XZR

0x42b118 ORR	X20, XZR, X2

0x42b11c MOVZ	W21, #1

0x42b120 ADD	X3, SP, #44

0x42b124 ADD	X4, SP, #40

0x42b128 STR	WZR, [SP, #44]

0x42b12c ADD	X5, SP, #28

0x42b130 ADD	X6, SP, #24

0x42b134 MOVZ	W2, #34

0x42b138 LDR	W22, [X9]

0x42b13c LDR	W8, [X8]

0x42b140 ORR	W1, WZR, W19

0x42b144 MOVZ	W7, #1

0x42b148 STR	W21, [SP]

0x42b14c STR	W8, [SP, #40]

0x42b150 STP	W21, W22, [SP, #24]

0x42b154 BL	404c10

0x42b158 LDRSW	X8, [SP, #40]

0x42b15c CMP	W8, W22

0x42b160 B.GT	42b2a0

0x42b164 LDR	W9, [SP, #28]

0x42b168 SUBS	W9, W9, W8

0x42b16c B.MI	42b2a0

0x42b170 LDP	X11, X10, [X20, #16]

0x42b174 CNTW	X14, ALL

0x42b178 PTRUE	P0.D, ALL

0x42b17c ADD	W9, W9, #1

0x42b180 LDR	W12, [X10]

0x42b184 LDRSW	X10, [X11]

0x42b188 SUB	W11, W12, W10

0x42b18c ADDS	W12, W11, #1

0x42b190 CSINC	W13, WZR, WZR, #0

0x42b194 SUB	W13, W12, W13

0x42b198 ADD	X13, X13, #1

0x42b19c B	42b1ac

(623) 0x42b1a0 ADD	X8, X8, #1

(623) 0x42b1a4 SUBS	W9, W9, #1

(623) 0x42b1a8 B.LE	42b2a0

(623) 0x42b1ac TBNZ	W11, #31, 42b1a0

0x42b1b0 LDR	X15, [X20, #56]

0x42b1b4 LDP	X18, X0, [X20, #112]

0x42b1b8 ORR	X3, XZR, X10

0x42b1bc ORR	W2, WZR, W12

0x42b1c0 LDR	X17, [X15]

0x42b1c4 LDP	X16, X15, [X20, #96]

0x42b1c8 CMP	X13, X14

0x42b1cc LDR	X1, [X16]

0x42b1d0 LDR	X16, [X20, #32]

0x42b1d4 B.CC	42b250

0x42b1d8 UDIV	X2, X13, X14

0x42b1dc MADD	X3, X17, X8, X10

0x42b1e0 ORR	X4, XZR, XZR

0x42b1e4 SUB	X7, X3, X1

0x42b1e8 UBFM	X27, X7, #61, #60

0x42b1ec ADDVL	X28, X27, #1

0x42b1f0 ADD	X7, X18, X27

0x42b1f4 ADD	X23, X0, X27

0x42b1f8 ADD	X25, X16, X27

0x42b1fc ADD	X27, X15, X27

0x42b200 ADD	X22, X18, X28

0x42b204 ADD	X24, X0, X28

0x42b208 ADD	X26, X16, X28

0x42b20c ADD	X28, X15, X28

0x42b210 MADD	X6, X2, X14, XZR

0x42b214 SUB	X5, X13, X6

0x42b218 ADD	X3, X6, X10

0x42b21c SUB	W2, W12, W6

(624) 0x42b220 LD1D	{Z0.D}, P0/Z, [X27, X4,LSL #3]

(624) 0x42b224 LD1D	{Z1.D}, P0/Z, [X28, X4,LSL #3]

(624) 0x42b228 ST1D	{Z0.D}, P0, [X25, X4,LSL #3]

(624) 0x42b22c ST1D	{Z1.D}, P0, [X26, X4,LSL #3]

(624) 0x42b230 LD1D	{Z0.D}, P0/Z, [X23, X4,LSL #3]

(624) 0x42b234 LD1D	{Z1.D}, P0/Z, [X24, X4,LSL #3]

(624) 0x42b238 ST1D	{Z0.D}, P0, [X7, X4,LSL #3]

(624) 0x42b23c ST1D	{Z1.D}, P0, [X22, X4,LSL #3]

(624) 0x42b240 ADD	X4, X4, X14

(624) 0x42b244 CMP	X6, X4

(624) 0x42b248 B.NE	42b220

0x42b24c CBZ	X5, 42b1a0

0x42b250 MADD	X17, X17, X8, X3

0x42b254 SUB	X17, X17, X1

0x42b258 UBFM	X1, X17, #61, #60

0x42b25c ADD	X17, X0, X1

0x42b260 ADD	X18, X18, X1

0x42b264 ADD	X16, X16, X1

0x42b268 ADD	X15, X15, X1

0x42b26c ADD	W0, W2, #1

0x42b270 HINT	#0

0x42b274 HINT	#0

0x42b278 HINT	#0

0x42b27c HINT	#0

(619) 0x42b280 LDR	D0, [X15], #8

(619) 0x42b284 SUB	W0, W0, #1

(619) 0x42b288 STR	D0, [X16], #8

(619) 0x42b28c CMP	W0, #1

(619) 0x42b290 LDR	D0, [X17], #8

(619) 0x42b294 STR	D0, [X18], #8

(619) 0x42b298 B.HI	42b280

0x42b29c B	42b1a0

0x42b2a0 ORR	X0, XZR, XZR

0x42b2a4 ORR	W1, WZR, W19

0x42b2a8 BL	404d30

0x42b2ac ORR	X0, XZR, XZR

0x42b2b0 ORR	W1, WZR, W19

0x42b2b4 BL	404900

0x42b2b8 LDP	X8, X9, [X20]

0x42b2bc ORR	X0, XZR, XZR

0x42b2c0 ORR	W1, WZR, W19

0x42b2c4 ADD	X3, SP, #20

0x42b2c8 ADD	X4, SP, #16

0x42b2cc ADD	X5, SP, #12

0x42b2d0 STR	WZR, [SP, #20]

0x42b2d4 LDR	W9, [X9]

0x42b2d8 LDR	W8, [X8]

0x42b2dc ADD	X6, SP, #8

0x42b2e0 MOVZ	W2, #34

0x42b2e4 MOVZ	W7, #1

0x42b2e8 STR	W21, [SP, #8]

0x42b2ec STR	W21, [SP]

0x42b2f0 ADD	W22, W9, #1

0x42b2f4 STP	W22, W8, [SP, #12]

0x42b2f8 BL	404c10

0x42b2fc LDRSW	X8, [SP, #16]

0x42b300 CMP	W8, W22

0x42b304 B.GT	42b440

0x42b308 LDR	W9, [SP, #12]

0x42b30c SUBS	W9, W9, W8

0x42b310 B.MI	42b440

0x42b314 LDP	X11, X10, [X20, #16]

0x42b318 CNTW	X13, ALL

0x42b31c PTRUE	P0.D, ALL

0x42b320 ADD	W9, W9, #1

0x42b324 LDR	W12, [X10]

0x42b328 LDRSW	X10, [X11]

0x42b32c SUB	W12, W12, W10

0x42b330 ADD	W11, W12, #2

0x42b334 ADD	W12, W12, #1

0x42b338 ADD	X12, X12, #1

0x42b33c B	42b34c

(620) 0x42b340 ADD	X8, X8, #1

(620) 0x42b344 SUBS	W9, W9, #1

(620) 0x42b348 B.LE	42b440

(620) 0x42b34c CMP	W11, #1

(620) 0x42b350 B.LT	42b340

(620) 0x42b354 LDR	X14, [X20, #144]

(620) 0x42b358 LDP	X17, X18, [X20, #192]

(620) 0x42b35c ORR	X2, XZR, X10

(620) 0x42b360 ORR	W1, WZR, W11

(620) 0x42b364 LDR	X16, [X14]

(620) 0x42b368 LDP	X15, X14, [X20, #176]

(620) 0x42b36c CMP	X12, X13

(620) 0x42b370 LDR	X0, [X15]

(620) 0x42b374 LDR	X15, [X20, #128]

(620) 0x42b378 B.CC	42b3f4

(620) 0x42b37c UDIV	X1, X12, X13

(620) 0x42b380 MADD	X2, X16, X8, X10

(620) 0x42b384 ORR	X3, XZR, XZR

(620) 0x42b388 SUB	X6, X2, X0

(620) 0x42b38c UBFM	X25, X6, #61, #60

(620) 0x42b390 ADDVL	X26, X25, #1

(620) 0x42b394 ADD	X6, X17, X25

(620) 0x42b398 ADD	X21, X18, X25

(620) 0x42b39c ADD	X23, X15, X25

(620) 0x42b3a0 ADD	X25, X14, X25

(620) 0x42b3a4 ADD	X7, X17, X26

(620) 0x42b3a8 ADD	X22, X18, X26

(620) 0x42b3ac ADD	X24, X15, X26

(620) 0x42b3b0 ADD	X26, X14, X26

(620) 0x42b3b4 MADD	X5, X1, X13, XZR

(620) 0x42b3b8 SUB	X4, X12, X5

(620) 0x42b3bc ADD	X2, X5, X10

(620) 0x42b3c0 SUB	W1, W11, W5

  (622) 0x42b3c4 LD1D	{Z0.D}, P0/Z, [X25, X3,LSL #3]

  (622) 0x42b3c8 LD1D	{Z1.D}, P0/Z, [X26, X3,LSL #3]

  (622) 0x42b3cc ST1D	{Z0.D}, P0, [X23, X3,LSL #3]

  (622) 0x42b3d0 ST1D	{Z1.D}, P0, [X24, X3,LSL #3]

  (622) 0x42b3d4 LD1D	{Z0.D}, P0/Z, [X21, X3,LSL #3]

  (622) 0x42b3d8 LD1D	{Z1.D}, P0/Z, [X22, X3,LSL #3]

  (622) 0x42b3dc ST1D	{Z0.D}, P0, [X6, X3,LSL #3]

  (622) 0x42b3e0 ST1D	{Z1.D}, P0, [X7, X3,LSL #3]

  (622) 0x42b3e4 ADD	X3, X3, X13

  (622) 0x42b3e8 CMP	X5, X3

  (622) 0x42b3ec B.NE	42b3c4

(620) 0x42b3f0 CBZ	X4, 42b340

(620) 0x42b3f4 MADD	X16, X16, X8, X2

(620) 0x42b3f8 SUB	X16, X16, X0

(620) 0x42b3fc UBFM	X0, X16, #61, #60

(620) 0x42b400 ADD	X16, X18, X0

(620) 0x42b404 ADD	X17, X17, X0

(620) 0x42b408 ADD	X15, X15, X0

(620) 0x42b40c ADD	X14, X14, X0

(620) 0x42b410 ADD	W18, W1, #1

(620) 0x42b414 HINT	#0

(620) 0x42b418 HINT	#0

(620) 0x42b41c HINT	#0

  (621) 0x42b420 LDR	D0, [X14], #8

  (621) 0x42b424 SUB	W18, W18, #1

  (621) 0x42b428 STR	D0, [X15], #8

  (621) 0x42b42c CMP	W18, #1

  (621) 0x42b430 LDR	D0, [X16], #8

  (621) 0x42b434 STR	D0, [X17], #8

  (621) 0x42b438 B.HI	42b420

(620) 0x42b43c B	42b340

0x42b440 ORR	X0, XZR, XZR

0x42b444 ORR	W1, WZR, W19

0x42b448 BL	404d30

0x42b44c ORR	X0, XZR, XZR

0x42b450 ORR	W1, WZR, W19

0x42b454 BL	404900

0x42b458 LDP	X20, X19, [SP, #112]

0x42b45c LDP	X22, X21, [SP, #96]

0x42b460 LDP	X24, X23, [SP, #80]

0x42b464 LDP	X26, X25, [SP, #64]

0x42b468 LDP	X28, X27, [SP, #48]

0x42b46c LDR	X30, [SP, #32]

0x42b470 ADD	SP, SP, #128

0x42b474 RET

0x42b478 HINT	#0

0x42b47c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	reset_field_kernel.f90-pp.f90:47-68
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/reset_field_kernel.f90-pp.f90:47-68.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.75 to 2.00 cycles (10.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.75 to 14.33 cycles (1.45x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.75 to 3.00 cycles (6.92x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 268 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	142
loop length	568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.00	8.00	20.75	20.75	20.75	20.75	0.00	0.00	0.00	0.00	14.33	14.33	14.33	7.00	7.00
cycles	8.00	8.00	20.75	20.75	20.75	20.75	0.00	0.00	0.00	0.00	14.33	14.33	14.33	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	17.00
Overall L1	20.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.75 cycles. At this rate:

13% of peak load performance is reached (12.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.17 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42b0f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W21, W22, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42b2a0 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42b2a0 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W11, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDS W12, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42b1ac <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X0, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X3, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X16, X15, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X1, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 42b250 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X2, X13, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X3, X17, X8, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X4, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X28, X27, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X7, X18, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X0, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X15, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X18, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X0, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X16, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X15, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X6, X2, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X5, X13, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X6, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W12, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X5, 42b1a0 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X17, X17, X8, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X17, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X1, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W0, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 42b1a0 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42b440 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42b440 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42b34c <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	reset_field_kernel.f90-pp.f90:47-68
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.75 to 3.00 cycles (6.92x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 268 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	142
loop length	568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.00	8.00	20.75	20.75	20.75	20.75	0.00	0.00	0.00	0.00	14.33	14.33	14.33	7.00	7.00
cycles	8.00	8.00	20.75	20.75	20.75	20.75	0.00	0.00	0.00	0.00	14.33	14.33	14.33	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	17.00
Overall L1	20.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.75 cycles. At this rate:

13% of peak load performance is reached (12.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.17 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42b0f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W21, W22, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42b2a0 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42b2a0 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W11, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDS W12, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42b1ac <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X0, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X3, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X16, X15, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X1, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 42b250 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X2, X13, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X3, X17, X8, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X4, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X28, X27, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X7, X18, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X0, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X15, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X18, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X0, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X16, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X15, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X6, X2, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X5, X13, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X6, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W12, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X5, 42b1a0 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X17, X17, X8, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X17, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X1, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W0, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 42b1a0 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42b440 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42b440 <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42b34c <__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼__nv_reset_field_kernel_module_reset_field_kernel__F1L47_1_–	4.58	6.21
○Loop 624 - reset_field_kernel.f90-pp.f90:52-53 - exec	2.3	3.1
▼Loop 620 - reset_field_kernel.f90-pp.f90:61-65 - exec–	0	0.01
○Loop 622 - reset_field_kernel.f90-pp.f90:62-63 - exec	2.28	3.08
○Loop 621 - reset_field_kernel.f90-pp.f90:62-64 - exec	0	0
○Loop 619 - reset_field_kernel.f90-pp.f90:52-54 - exec	0	0
○Loop 623 - reset_field_kernel.f90-pp.f90:51-55 - exec	0	0

Report Configuration

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Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code