OV - exec - Function __nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1

	Function: __nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_	Module: exec	Source: initialise_chunk_kernel.f90-pp.f90:58-133	Coverage: 0.02%

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90-pp.f90: 58 - 133

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58: # 58 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

59:     !$OMP PARALLEL

60:     !$OMP DO

61:     DO j=x_min-2,x_max+3

62:       vertexx(j)=xmin+dx*float(j-x_min)

63:     ENDDO

64:     !$OMP END DO

65: # 65 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

66:     !$OMP DO

67:     DO j=x_min-2,x_max+3

68:       vertexdx(j)=dx

69:     ENDDO

70:     !$OMP END DO

71: # 71 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

72:     !$OMP DO

73:     DO k=y_min-2,y_max+3

74:       vertexy(k)=ymin+dy*float(k-y_min)

75:     ENDDO

76:     !$OMP END DO

77: # 77 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

78:     !$OMP DO

79:     DO k=y_min-2,y_max+3

80:       vertexdy(k)=dy

81:     ENDDO

82:     !$OMP END DO

83: # 83 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

84:     !$OMP DO

85:     DO j=x_min-2,x_max+2

86:       cellx(j)=0.5*(vertexx(j)+vertexx(j+1))

87:     ENDDO

88:     !$OMP END DO

89: # 89 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

90:     !$OMP DO

91:     DO j=x_min-2,x_max+2

92:       celldx(j)=dx

93:     ENDDO

94:     !$OMP END DO

95: # 95 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

96:     !$OMP DO

97:     DO k=y_min-2,y_max+2

98:       celly(k)=0.5*(vertexy(k)+vertexy(k+1))

99:     ENDDO

100:     !$OMP END DO

101: # 101 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

102:     !$OMP DO

103:     DO k=y_min-2,y_max+2

104:       celldy(k)=dy

105:     ENDDO

106:     !$OMP END DO

107: # 107 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

108:     !$OMP DO PRIVATE(j)

109:     DO k=y_min-2,y_max+2

110:     !$OMP SIMD

111:       DO j=x_min-2,x_max+2

112:         volume(j,k)=dx*dy

113:       ENDDO

114:     ENDDO

115:     !$OMP END DO

116: # 116 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

117:     !$OMP DO PRIVATE(j)

118:     DO k=y_min-2,y_max+2

119:     !$OMP SIMD

120:       DO j=x_min-2,x_max+2

121:         xarea(j,k)=celldy(k)

122:       ENDDO

123:     ENDDO

124:     !$OMP END DO

125: # 125 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90"

126:     !$OMP DO PRIVATE(j)

127:     DO k=y_min-2,y_max+2

128:     !$OMP SIMD

129:       DO j=x_min-2,x_max+2

130:         yarea(j,k)=celldx(j)

131:       ENDDO

132:     ENDDO

133:   !$OMP END DO

0x425a90 SUB	SP, SP, #240

0x425a94 STP	X30, X23, [SP, #192]

0x425a98 STP	X22, X21, [SP, #208]

0x425a9c STP	X20, X19, [SP, #224]

0x425aa0 LDP	X8, X9, [X2]

0x425aa4 LDR	W19, [X0]

0x425aa8 ORR	X0, XZR, XZR

0x425aac ORR	X20, XZR, X2

0x425ab0 MOVZ	W21, #1

0x425ab4 ADD	X3, SP, #188

0x425ab8 ADD	X4, SP, #184

0x425abc STR	WZR, [SP, #188]

0x425ac0 ADD	X5, SP, #180

0x425ac4 ADD	X6, SP, #176

0x425ac8 MOVZ	W2, #34

0x425acc STR	W21, [SP, #176]

0x425ad0 LDR	W8, [X8]

0x425ad4 LDR	W9, [X9]

0x425ad8 ORR	W1, WZR, W19

0x425adc MOVZ	W7, #1

0x425ae0 ADD	W22, W9, #3

0x425ae4 SUB	W8, W8, #2

0x425ae8 STR	W21, [SP]

0x425aec STP	W22, W8, [SP, #180]

0x425af0 BL	404c10

0x425af4 LDRSW	X12, [SP, #184]

0x425af8 CMP	W12, W22

0x425afc B.GT	425c20

0x425b00 LDR	W13, [SP, #180]

0x425b04 SUBS	W8, W13, W12

0x425b08 B.MI	425c20

0x425b0c LDR	X10, [X20, #64]

0x425b10 ADDS	W8, W8, #1

0x425b14 LDR	X9, [X20]

0x425b18 SUB	W13, W13, W12

0x425b1c CSINC	W14, WZR, WZR, #0

0x425b20 SUB	W13, W13, W14

0x425b24 LDR	D0, [X10]

0x425b28 LDP	X11, X10, [X20, #48]

0x425b2c LDR	W9, [X9]

0x425b30 ADD	W13, W13, #1

0x425b34 ADD	X15, X13, #1

0x425b38 CNTW	X13, ALL

0x425b3c CMP	X15, X13

0x425b40 LDR	D1, [X10]

0x425b44 LDR	X10, [X11]

0x425b48 LDR	X11, [X20, #16]

0x425b4c B.CC	425be0

0x425b50 UDIV	X16, X15, X13

0x425b54 CNTD	X18, ALL

0x425b58 ORR	X14, XZR, XZR

0x425b5c DUP	Z4.D, Z0.D[0]

0x425b60 DUP	Z5.D, Z1.D[0]

0x425b64 PTRUE	P0.D, ALL

0x425b68 SUB	W18, W18, W9

0x425b6c MADD	X17, X16, X13, XZR

0x425b70 DUP	Z6.D, X18

0x425b74 SUB	X18, X11, X10,LSL #3

0x425b78 ADD	X16, X17, X12

0x425b7c SUB	X15, X15, X17

0x425b80 SUB	W8, W8, W17

0x425b84 INDEX	Z2.D, X12, #1

0x425b88 ADD	X12, X18, X12,LSL #3

0x425b8c ADDVL	X18, X12, #1

0x425b90 DUP	Z3.D, X9

0x425b94 DUP	Z7.D, X13

0x425b98 HINT	#0

0x425b9c HINT	#0

(565) 0x425ba0 SUB	Z16.D, Z2.D, Z3.D

(565) 0x425ba4 ADD	Z17.D, Z6.D, Z2.D

(565) 0x425ba8 ADD	Z2.D, Z2.D, Z7.D

(565) 0x425bac SCVTF	Z16.S, P0/M, Z16.S

(565) 0x425bb0 SCVTF	Z17.S, P0/M, Z17.S

(565) 0x425bb4 FCVT	Z16.D, P0/M, Z16.S

(565) 0x425bb8 FCVT	Z17.D, P0/M, Z17.S

(565) 0x425bbc FMAD	Z16.D, P0/M, Z4.D, Z5.D

(565) 0x425bc0 FMAD	Z17.D, P0/M, Z4.D, Z5.D

(565) 0x425bc4 ST1D	{Z16.D}, P0, [X12, X14,LSL #3]

(565) 0x425bc8 ST1D	{Z17.D}, P0, [X18, X14,LSL #3]

(565) 0x425bcc ADD	X14, X14, X13

(565) 0x425bd0 CMP	X17, X14

(565) 0x425bd4 B.NE	425ba0

0x425bd8 ORR	X12, XZR, X16

0x425bdc CBZ	X15, 425c20

0x425be0 SUB	X10, X11, X10,LSL #3

0x425be4 SUB	W9, W12, W9

0x425be8 ADD	W8, W8, #1

0x425bec ADD	X10, X10, X12,LSL #3

0x425bf0 HINT	#0

0x425bf4 HINT	#0

0x425bf8 HINT	#0

0x425bfc HINT	#0

(564) 0x425c00 SCVTF	S2, W9

(564) 0x425c04 SUB	W8, W8, #1

(564) 0x425c08 ADD	W9, W9, #1

(564) 0x425c0c CMP	W8, #1

(564) 0x425c10 FCVT	D2, S2

(564) 0x425c14 FMADD	D2, D2, D0, D1

(564) 0x425c18 STR	D2, [X10], #8

(564) 0x425c1c B.HI	425c00

0x425c20 ORR	X0, XZR, XZR

0x425c24 ORR	W1, WZR, W19

0x425c28 BL	404d30

0x425c2c ORR	X0, XZR, XZR

0x425c30 ORR	W1, WZR, W19

0x425c34 BL	404900

0x425c38 LDP	X8, X9, [X20]

0x425c3c ORR	X0, XZR, XZR

0x425c40 ORR	W1, WZR, W19

0x425c44 ADD	X3, SP, #172

0x425c48 ADD	X4, SP, #168

0x425c4c ADD	X5, SP, #164

0x425c50 STR	WZR, [SP, #172]

0x425c54 LDR	W8, [X8]

0x425c58 LDR	W9, [X9]

0x425c5c ADD	X6, SP, #160

0x425c60 MOVZ	W2, #34

0x425c64 MOVZ	W7, #1

0x425c68 STR	W21, [SP, #160]

0x425c6c STR	W21, [SP]

0x425c70 SUB	W8, W8, #2

0x425c74 ADD	W22, W9, #3

0x425c78 STP	W22, W8, [SP, #164]

0x425c7c BL	404c10

0x425c80 LDRSW	X9, [SP, #168]

0x425c84 CMP	W9, W22

0x425c88 B.GT	425d38

0x425c8c LDR	W12, [SP, #164]

0x425c90 SUBS	W8, W12, W9

0x425c94 B.MI	425d38

0x425c98 LDP	X11, X10, [X20, #64]

0x425c9c ADDS	W8, W8, #1

0x425ca0 SUB	W12, W12, W9

0x425ca4 CSINC	W13, WZR, WZR, #0

0x425ca8 SUB	W12, W12, W13

0x425cac LDR	D0, [X11]

0x425cb0 LDR	X11, [X20, #48]

0x425cb4 ADD	W12, W12, #1

0x425cb8 ADD	X13, X12, #1

0x425cbc CNTW	X12, ALL

0x425cc0 CMP	X13, X12

0x425cc4 LDR	X11, [X11]

0x425cc8 B.CC	425d1c

0x425ccc UDIV	X15, X13, X12

0x425cd0 SUB	X17, X10, X11,LSL #3

0x425cd4 ORR	X14, XZR, XZR

0x425cd8 DUP	Z1.D, Z0.D[0]

0x425cdc PTRUE	P0.D, ALL

0x425ce0 MADD	X15, X15, X12, XZR

0x425ce4 ADD	X16, X15, X9

0x425ce8 ADD	X9, X17, X9,LSL #3

0x425cec SUB	X13, X13, X15

0x425cf0 SUB	W8, W8, W15

0x425cf4 ADDVL	X17, X9, #1

0x425cf8 HINT	#0

0x425cfc HINT	#0

(563) 0x425d00 ST1D	{Z1.D}, P0, [X9, X14,LSL #3]

(563) 0x425d04 ST1D	{Z1.D}, P0, [X17, X14,LSL #3]

(563) 0x425d08 ADD	X14, X14, X12

(563) 0x425d0c CMP	X15, X14

(563) 0x425d10 B.NE	425d00

0x425d14 ORR	X9, XZR, X16

0x425d18 CBZ	X13, 425d38

0x425d1c SUB	X10, X10, X11,LSL #3

0x425d20 ADD	W8, W8, #1

0x425d24 ADD	X9, X10, X9,LSL #3

(562) 0x425d28 SUB	W8, W8, #1

(562) 0x425d2c STR	D0, [X9], #8

(562) 0x425d30 CMP	W8, #1

(562) 0x425d34 B.HI	425d28

0x425d38 ORR	X0, XZR, XZR

0x425d3c ORR	W1, WZR, W19

0x425d40 BL	404d30

0x425d44 ORR	X0, XZR, XZR

0x425d48 ORR	W1, WZR, W19

0x425d4c BL	404900

0x425d50 LDP	X8, X9, [X20, #80]

0x425d54 ORR	X0, XZR, XZR

0x425d58 ORR	W1, WZR, W19

0x425d5c MOVZ	W21, #1

0x425d60 ADD	X3, SP, #156

0x425d64 ADD	X4, SP, #152

0x425d68 STR	WZR, [SP, #156]

0x425d6c LDR	W8, [X8]

0x425d70 LDR	W9, [X9]

0x425d74 ADD	X5, SP, #148

0x425d78 ADD	X6, SP, #144

0x425d7c MOVZ	W2, #34

0x425d80 MOVZ	W7, #1

0x425d84 STR	W21, [SP, #144]

0x425d88 STR	W21, [SP]

0x425d8c ADD	W22, W9, #3

0x425d90 SUB	W8, W8, #2

0x425d94 STP	W22, W8, [SP, #148]

0x425d98 BL	404c10

0x425d9c LDRSW	X12, [SP, #152]

0x425da0 CMP	W12, W22

0x425da4 B.GT	425ec0

0x425da8 LDR	W13, [SP, #148]

0x425dac SUBS	W8, W13, W12

0x425db0 B.MI	425ec0

0x425db4 LDR	X10, [X20, #144]

0x425db8 ADDS	W8, W8, #1

0x425dbc LDR	X9, [X20, #80]

0x425dc0 SUB	W13, W13, W12

0x425dc4 CSINC	W14, WZR, WZR, #0

0x425dc8 SUB	W13, W13, W14

0x425dcc LDR	D0, [X10]

0x425dd0 LDP	X11, X10, [X20, #128]

0x425dd4 LDR	W9, [X9]

0x425dd8 ADD	W13, W13, #1

0x425ddc ADD	X15, X13, #1

0x425de0 CNTW	X13, ALL

0x425de4 CMP	X15, X13

0x425de8 LDR	D1, [X10]

0x425dec LDR	X10, [X11]

0x425df0 LDR	X11, [X20, #96]

0x425df4 B.CC	425e80

0x425df8 UDIV	X16, X15, X13

0x425dfc CNTD	X18, ALL

0x425e00 ORR	X14, XZR, XZR

0x425e04 DUP	Z4.D, Z0.D[0]

0x425e08 DUP	Z5.D, Z1.D[0]

0x425e0c PTRUE	P0.D, ALL

0x425e10 SUB	W18, W18, W9

0x425e14 MADD	X17, X16, X13, XZR

0x425e18 DUP	Z6.D, X18

0x425e1c SUB	X18, X11, X10,LSL #3

0x425e20 ADD	X16, X17, X12

0x425e24 SUB	X15, X15, X17

0x425e28 SUB	W8, W8, W17

0x425e2c INDEX	Z2.D, X12, #1

0x425e30 ADD	X12, X18, X12,LSL #3

0x425e34 ADDVL	X18, X12, #1

0x425e38 DUP	Z3.D, X9

0x425e3c DUP	Z7.D, X13

(561) 0x425e40 SUB	Z16.D, Z2.D, Z3.D

(561) 0x425e44 ADD	Z17.D, Z6.D, Z2.D

(561) 0x425e48 ADD	Z2.D, Z2.D, Z7.D

(561) 0x425e4c SCVTF	Z16.S, P0/M, Z16.S

(561) 0x425e50 SCVTF	Z17.S, P0/M, Z17.S

(561) 0x425e54 FCVT	Z16.D, P0/M, Z16.S

(561) 0x425e58 FCVT	Z17.D, P0/M, Z17.S

(561) 0x425e5c FMAD	Z16.D, P0/M, Z4.D, Z5.D

(561) 0x425e60 FMAD	Z17.D, P0/M, Z4.D, Z5.D

(561) 0x425e64 ST1D	{Z16.D}, P0, [X12, X14,LSL #3]

(561) 0x425e68 ST1D	{Z17.D}, P0, [X18, X14,LSL #3]

(561) 0x425e6c ADD	X14, X14, X13

(561) 0x425e70 CMP	X17, X14

(561) 0x425e74 B.NE	425e40

0x425e78 ORR	X12, XZR, X16

0x425e7c CBZ	X15, 425ec0

0x425e80 SUB	X10, X11, X10,LSL #3

0x425e84 SUB	W9, W12, W9

0x425e88 ADD	W8, W8, #1

0x425e8c ADD	X10, X10, X12,LSL #3

0x425e90 HINT	#0

0x425e94 HINT	#0

0x425e98 HINT	#0

0x425e9c HINT	#0

(560) 0x425ea0 SCVTF	S2, W9

(560) 0x425ea4 SUB	W8, W8, #1

(560) 0x425ea8 ADD	W9, W9, #1

(560) 0x425eac CMP	W8, #1

(560) 0x425eb0 FCVT	D2, S2

(560) 0x425eb4 FMADD	D2, D2, D0, D1

(560) 0x425eb8 STR	D2, [X10], #8

(560) 0x425ebc B.HI	425ea0

0x425ec0 ORR	X0, XZR, XZR

0x425ec4 ORR	W1, WZR, W19

0x425ec8 BL	404d30

0x425ecc ORR	X0, XZR, XZR

0x425ed0 ORR	W1, WZR, W19

0x425ed4 BL	404900

0x425ed8 LDP	X8, X9, [X20, #80]

0x425edc ORR	X0, XZR, XZR

0x425ee0 ORR	W1, WZR, W19

0x425ee4 ADD	X3, SP, #140

0x425ee8 ADD	X4, SP, #136

0x425eec ADD	X5, SP, #132

0x425ef0 STR	WZR, [SP, #140]

0x425ef4 LDR	W8, [X8]

0x425ef8 LDR	W9, [X9]

0x425efc ADD	X6, SP, #128

0x425f00 MOVZ	W2, #34

0x425f04 MOVZ	W7, #1

0x425f08 STR	W21, [SP, #128]

0x425f0c STR	W21, [SP]

0x425f10 SUB	W8, W8, #2

0x425f14 ADD	W22, W9, #3

0x425f18 STP	W22, W8, [SP, #132]

0x425f1c BL	404c10

0x425f20 LDRSW	X9, [SP, #136]

0x425f24 CMP	W9, W22

0x425f28 B.GT	425fd8

0x425f2c LDR	W12, [SP, #132]

0x425f30 SUBS	W8, W12, W9

0x425f34 B.MI	425fd8

0x425f38 LDP	X11, X10, [X20, #144]

0x425f3c ADDS	W8, W8, #1

0x425f40 SUB	W12, W12, W9

0x425f44 CSINC	W13, WZR, WZR, #0

0x425f48 SUB	W12, W12, W13

0x425f4c LDR	D0, [X11]

0x425f50 LDR	X11, [X20, #128]

0x425f54 ADD	W12, W12, #1

0x425f58 ADD	X13, X12, #1

0x425f5c CNTW	X12, ALL

0x425f60 CMP	X13, X12

0x425f64 LDR	X11, [X11]

0x425f68 B.CC	425fbc

0x425f6c UDIV	X15, X13, X12

0x425f70 SUB	X17, X10, X11,LSL #3

0x425f74 ORR	X14, XZR, XZR

0x425f78 DUP	Z1.D, Z0.D[0]

0x425f7c PTRUE	P0.D, ALL

0x425f80 MADD	X15, X15, X12, XZR

0x425f84 ADD	X16, X15, X9

0x425f88 ADD	X9, X17, X9,LSL #3

0x425f8c SUB	X13, X13, X15

0x425f90 SUB	W8, W8, W15

0x425f94 ADDVL	X17, X9, #1

0x425f98 HINT	#0

0x425f9c HINT	#0

(559) 0x425fa0 ST1D	{Z1.D}, P0, [X9, X14,LSL #3]

(559) 0x425fa4 ST1D	{Z1.D}, P0, [X17, X14,LSL #3]

(559) 0x425fa8 ADD	X14, X14, X12

(559) 0x425fac CMP	X15, X14

(559) 0x425fb0 B.NE	425fa0

0x425fb4 ORR	X9, XZR, X16

0x425fb8 CBZ	X13, 425fd8

0x425fbc SUB	X10, X10, X11,LSL #3

0x425fc0 ADD	W8, W8, #1

0x425fc4 ADD	X9, X10, X9,LSL #3

(558) 0x425fc8 SUB	W8, W8, #1

(558) 0x425fcc STR	D0, [X9], #8

(558) 0x425fd0 CMP	W8, #1

(558) 0x425fd4 B.HI	425fc8

0x425fd8 ORR	X0, XZR, XZR

0x425fdc ORR	W1, WZR, W19

0x425fe0 BL	404d30

0x425fe4 ORR	X0, XZR, XZR

0x425fe8 ORR	W1, WZR, W19

0x425fec BL	404900

0x425ff0 LDP	X8, X9, [X20]

0x425ff4 ORR	X0, XZR, XZR

0x425ff8 ORR	W1, WZR, W19

0x425ffc MOVZ	W21, #1

0x426000 ADD	X3, SP, #124

0x426004 ADD	X4, SP, #120

0x426008 STR	WZR, [SP, #124]

0x42600c LDR	W8, [X8]

0x426010 LDR	W9, [X9]

0x426014 ADD	X5, SP, #116

0x426018 ADD	X6, SP, #112

0x42601c MOVZ	W2, #34

0x426020 MOVZ	W7, #1

0x426024 STR	W21, [SP, #112]

0x426028 STR	W21, [SP]

0x42602c ADD	W22, W9, #2

0x426030 SUB	W8, W8, #2

0x426034 STP	W22, W8, [SP, #116]

0x426038 BL	404c10

0x42603c LDRSW	X13, [SP, #120]

0x426040 CMP	W13, W22

0x426044 B.GT	42614c

0x426048 LDR	W12, [SP, #116]

0x42604c SUBS	W8, W12, W13

0x426050 B.MI	42614c

0x426054 ADDS	W8, W8, #1

0x426058 LDR	X9, [X20, #48]

0x42605c SUB	W12, W12, W13

0x426060 LDR	X11, [X20, #16]

0x426064 CSINC	W14, WZR, WZR, #0

0x426068 SUB	W12, W12, W14

0x42606c LDR	X10, [X9]

0x426070 LDR	X9, [X20, #160]

0x426074 ADD	W12, W12, #1

0x426078 ADD	X15, X12, #1

0x42607c CNTW	X12, ALL

0x426080 CMP	X15, X12

0x426084 B.CC	426110

0x426088 UDIV	X16, X15, X12

0x42608c UBFM	X18, X13, #61, #60

0x426090 UBFM	X0, X10, #61, #60

0x426094 ORR	X14, XZR, XZR

0x426098 PTRUE	P0.D, ALL

0x42609c SUB	X1, X18, X0

0x4260a0 ADDVL	X18, X18, #1

0x4260a4 SUB	X2, X18, X0

0x4260a8 ADD	X17, X9, X1

0x4260ac ADD	X0, X11, X1

0x4260b0 ADD	X18, X9, X2

0x4260b4 ADD	X1, X11, X2

0x4260b8 MOVZ	X2, #1

0x4260bc MADD	X16, X16, X12, XZR

0x4260c0 SUB	X15, X15, X16

0x4260c4 ADD	X13, X16, X13

0x4260c8 SUB	W8, W8, W16

(557) 0x4260cc UBFM	X3, X14, #61, #60

(557) 0x4260d0 ADD	X4, X0, X3

(557) 0x4260d4 ADD	X3, X1, X3

(557) 0x4260d8 LD1D	{Z0.D}, P0/Z, [X4, X2,LSL #3]

(557) 0x4260dc LD1D	{Z1.D}, P0/Z, [X3, X2,LSL #3]

(557) 0x4260e0 LD1D	{Z2.D}, P0/Z, [X4, MUL VL]

(557) 0x4260e4 LD1D	{Z3.D}, P0/Z, [X3, MUL VL]

(557) 0x4260e8 FADD	Z0.D, Z0.D, Z2.D

(557) 0x4260ec FADD	Z1.D, Z1.D, Z3.D

(557) 0x4260f0 FMUL	Z0.D, P0/M, Z0.D, #0

(557) 0x4260f4 FMUL	Z1.D, P0/M, Z1.D, #0

(557) 0x4260f8 ST1D	{Z0.D}, P0, [X17, X14,LSL #3]

(557) 0x4260fc ST1D	{Z1.D}, P0, [X18, X14,LSL #3]

(557) 0x426100 ADD	X14, X14, X12

(557) 0x426104 CMP	X16, X14

(557) 0x426108 B.NE	4260cc

0x42610c CBZ	X15, 42614c

0x426110 UBFM	X12, X13, #61, #60

0x426114 FMOV	D0, #0.5000000

0x426118 ADD	W8, W8, #1

0x42611c SUB	X12, X12, X10,LSL #3

0x426120 ADD	X10, X12, X11

0x426124 ADD	X9, X9, X12

0x426128 ADD	X10, X10, #8

(556) 0x42612c LDP	D2, D1, [X10, #1016]

(556) 0x426130 SUB	W8, W8, #1

(556) 0x426134 ADD	X10, X10, #8

(556) 0x426138 CMP	W8, #1

(556) 0x42613c FADD	D1, D1, D2

(556) 0x426140 FMUL	D1, D1, D0

(556) 0x426144 STR	D1, [X9], #8

(556) 0x426148 B.HI	42612c

0x42614c ORR	X0, XZR, XZR

0x426150 ORR	W1, WZR, W19

0x426154 BL	404d30

0x426158 ORR	X0, XZR, XZR

0x42615c ORR	W1, WZR, W19

0x426160 BL	404900

0x426164 LDP	X8, X9, [X20]

0x426168 ORR	X0, XZR, XZR

0x42616c ORR	W1, WZR, W19

0x426170 ADD	X3, SP, #108

0x426174 ADD	X4, SP, #104

0x426178 ADD	X5, SP, #100

0x42617c STR	WZR, [SP, #108]

0x426180 LDR	W8, [X8]

0x426184 LDR	W9, [X9]

0x426188 ADD	X6, SP, #96

0x42618c MOVZ	W2, #34

0x426190 MOVZ	W7, #1

0x426194 STR	W21, [SP, #96]

0x426198 STR	W21, [SP]

0x42619c SUB	W8, W8, #2

0x4261a0 ADD	W22, W9, #2

0x4261a4 STP	W22, W8, [SP, #100]

0x4261a8 BL	404c10

0x4261ac LDRSW	X9, [SP, #104]

0x4261b0 CMP	W9, W22

0x4261b4 B.GT	426270

0x4261b8 LDR	W12, [SP, #100]

0x4261bc SUBS	W8, W12, W9

0x4261c0 B.MI	426270

0x4261c4 LDR	X10, [X20, #64]

0x4261c8 ADDS	W8, W8, #1

0x4261cc SUB	W12, W12, W9

0x4261d0 LDR	X11, [X20, #184]

0x4261d4 CSINC	W13, WZR, WZR, #0

0x4261d8 SUB	W12, W12, W13

0x4261dc LDR	D0, [X10]

0x4261e0 LDR	X10, [X20, #48]

0x4261e4 ADD	W12, W12, #1

0x4261e8 ADD	X13, X12, #1

0x4261ec CNTW	X12, ALL

0x4261f0 CMP	X13, X12

0x4261f4 LDR	X10, [X10]

0x4261f8 B.CC	426244

0x4261fc UDIV	X15, X13, X12

0x426200 SUB	X17, X11, X10,LSL #3

0x426204 ORR	X14, XZR, XZR

0x426208 DUP	Z1.D, Z0.D[0]

0x42620c PTRUE	P0.D, ALL

0x426210 MADD	X15, X15, X12, XZR

0x426214 ADD	X16, X15, X9

0x426218 ADD	X9, X17, X9,LSL #3

0x42621c SUB	X13, X13, X15

0x426220 SUB	W8, W8, W15

0x426224 ADDVL	X17, X9, #1

(555) 0x426228 ST1D	{Z1.D}, P0, [X9, X14,LSL #3]

(555) 0x42622c ST1D	{Z1.D}, P0, [X17, X14,LSL #3]

(555) 0x426230 ADD	X14, X14, X12

(555) 0x426234 CMP	X15, X14

(555) 0x426238 B.NE	426228

0x42623c ORR	X9, XZR, X16

0x426240 CBZ	X13, 426270

0x426244 SUB	X10, X11, X10,LSL #3

0x426248 ADD	W8, W8, #1

0x42624c ADD	X9, X10, X9,LSL #3

0x426250 HINT	#0

0x426254 HINT	#0

0x426258 HINT	#0

0x42625c HINT	#0

(554) 0x426260 SUB	W8, W8, #1

(554) 0x426264 STR	D0, [X9], #8

(554) 0x426268 CMP	W8, #1

(554) 0x42626c B.HI	426260

0x426270 ORR	X0, XZR, XZR

0x426274 ORR	W1, WZR, W19

0x426278 BL	404d30

0x42627c ORR	X0, XZR, XZR

0x426280 ORR	W1, WZR, W19

0x426284 BL	404900

0x426288 LDP	X8, X9, [X20, #80]

0x42628c ORR	X0, XZR, XZR

0x426290 ORR	W1, WZR, W19

0x426294 MOVZ	W21, #1

0x426298 ADD	X3, SP, #92

0x42629c ADD	X4, SP, #88

0x4262a0 STR	WZR, [SP, #92]

0x4262a4 LDR	W8, [X8]

0x4262a8 LDR	W9, [X9]

0x4262ac ADD	X5, SP, #84

0x4262b0 ADD	X6, SP, #80

0x4262b4 MOVZ	W2, #34

0x4262b8 MOVZ	W7, #1

0x4262bc STR	W21, [SP, #80]

0x4262c0 STR	W21, [SP]

0x4262c4 ADD	W22, W9, #2

0x4262c8 SUB	W8, W8, #2

0x4262cc STP	W22, W8, [SP, #84]

0x4262d0 BL	404c10

0x4262d4 LDRSW	X13, [SP, #88]

0x4262d8 CMP	W13, W22

0x4262dc B.GT	4263e4

0x4262e0 LDR	W12, [SP, #84]

0x4262e4 SUBS	W8, W12, W13

0x4262e8 B.MI	4263e4

0x4262ec ADDS	W8, W8, #1

0x4262f0 LDR	X9, [X20, #128]

0x4262f4 SUB	W12, W12, W13

0x4262f8 LDR	X11, [X20, #96]

0x4262fc CSINC	W14, WZR, WZR, #0

0x426300 SUB	W12, W12, W14

0x426304 LDR	X10, [X9]

0x426308 LDR	X9, [X20, #192]

0x42630c ADD	W12, W12, #1

0x426310 ADD	X15, X12, #1

0x426314 CNTW	X12, ALL

0x426318 CMP	X15, X12

0x42631c B.CC	4263a8

0x426320 UDIV	X16, X15, X12

0x426324 UBFM	X18, X13, #61, #60

0x426328 UBFM	X0, X10, #61, #60

0x42632c ORR	X14, XZR, XZR

0x426330 PTRUE	P0.D, ALL

0x426334 SUB	X1, X18, X0

0x426338 ADDVL	X18, X18, #1

0x42633c SUB	X2, X18, X0

0x426340 ADD	X17, X9, X1

0x426344 ADD	X0, X11, X1

0x426348 ADD	X18, X9, X2

0x42634c ADD	X1, X11, X2

0x426350 MOVZ	X2, #1

0x426354 MADD	X16, X16, X12, XZR

0x426358 SUB	X15, X15, X16

0x42635c ADD	X13, X16, X13

0x426360 SUB	W8, W8, W16

(553) 0x426364 UBFM	X3, X14, #61, #60

(553) 0x426368 ADD	X4, X0, X3

(553) 0x42636c ADD	X3, X1, X3

(553) 0x426370 LD1D	{Z0.D}, P0/Z, [X4, X2,LSL #3]

(553) 0x426374 LD1D	{Z1.D}, P0/Z, [X3, X2,LSL #3]

(553) 0x426378 LD1D	{Z2.D}, P0/Z, [X4, MUL VL]

(553) 0x42637c LD1D	{Z3.D}, P0/Z, [X3, MUL VL]

(553) 0x426380 FADD	Z0.D, Z0.D, Z2.D

(553) 0x426384 FADD	Z1.D, Z1.D, Z3.D

(553) 0x426388 FMUL	Z0.D, P0/M, Z0.D, #0

(553) 0x42638c FMUL	Z1.D, P0/M, Z1.D, #0

(553) 0x426390 ST1D	{Z0.D}, P0, [X17, X14,LSL #3]

(553) 0x426394 ST1D	{Z1.D}, P0, [X18, X14,LSL #3]

(553) 0x426398 ADD	X14, X14, X12

(553) 0x42639c CMP	X16, X14

(553) 0x4263a0 B.NE	426364

0x4263a4 CBZ	X15, 4263e4

0x4263a8 UBFM	X12, X13, #61, #60

0x4263ac FMOV	D0, #0.5000000

0x4263b0 ADD	W8, W8, #1

0x4263b4 SUB	X12, X12, X10,LSL #3

0x4263b8 ADD	X10, X12, X11

0x4263bc ADD	X9, X9, X12

0x4263c0 ADD	X10, X10, #8

(552) 0x4263c4 LDP	D2, D1, [X10, #1016]

(552) 0x4263c8 SUB	W8, W8, #1

(552) 0x4263cc ADD	X10, X10, #8

(552) 0x4263d0 CMP	W8, #1

(552) 0x4263d4 FADD	D1, D1, D2

(552) 0x4263d8 FMUL	D1, D1, D0

(552) 0x4263dc STR	D1, [X9], #8

(552) 0x4263e0 B.HI	4263c4

0x4263e4 ORR	X0, XZR, XZR

0x4263e8 ORR	W1, WZR, W19

0x4263ec BL	404d30

0x4263f0 ORR	X0, XZR, XZR

0x4263f4 ORR	W1, WZR, W19

0x4263f8 BL	404900

0x4263fc LDP	X8, X9, [X20, #80]

0x426400 ORR	X0, XZR, XZR

0x426404 ORR	W1, WZR, W19

0x426408 ADD	X3, SP, #76

0x42640c ADD	X4, SP, #72

0x426410 ADD	X5, SP, #68

0x426414 STR	WZR, [SP, #76]

0x426418 LDR	W8, [X8]

0x42641c LDR	W9, [X9]

0x426420 ADD	X6, SP, #64

0x426424 MOVZ	W2, #34

0x426428 MOVZ	W7, #1

0x42642c STR	W21, [SP, #64]

0x426430 STR	W21, [SP]

0x426434 SUB	W8, W8, #2

0x426438 ADD	W22, W9, #2

0x42643c STP	W22, W8, [SP, #68]

0x426440 BL	404c10

0x426444 LDRSW	X9, [SP, #72]

0x426448 CMP	W9, W22

0x42644c B.GT	4264f8

0x426450 LDR	W12, [SP, #68]

0x426454 SUBS	W8, W12, W9

0x426458 B.MI	4264f8

0x42645c LDR	X10, [X20, #144]

0x426460 ADDS	W8, W8, #1

0x426464 SUB	W12, W12, W9

0x426468 LDR	X11, [X20, #216]

0x42646c CSINC	W13, WZR, WZR, #0

0x426470 SUB	W12, W12, W13

0x426474 LDR	D0, [X10]

0x426478 LDR	X10, [X20, #128]

0x42647c ADD	W12, W12, #1

0x426480 ADD	X13, X12, #1

0x426484 CNTW	X12, ALL

0x426488 CMP	X13, X12

0x42648c LDR	X10, [X10]

0x426490 B.CC	4264dc

0x426494 UDIV	X15, X13, X12

0x426498 SUB	X17, X11, X10,LSL #3

0x42649c ORR	X14, XZR, XZR

0x4264a0 DUP	Z1.D, Z0.D[0]

0x4264a4 PTRUE	P0.D, ALL

0x4264a8 MADD	X15, X15, X12, XZR

0x4264ac ADD	X16, X15, X9

0x4264b0 ADD	X9, X17, X9,LSL #3

0x4264b4 SUB	X13, X13, X15

0x4264b8 SUB	W8, W8, W15

0x4264bc ADDVL	X17, X9, #1

(551) 0x4264c0 ST1D	{Z1.D}, P0, [X9, X14,LSL #3]

(551) 0x4264c4 ST1D	{Z1.D}, P0, [X17, X14,LSL #3]

(551) 0x4264c8 ADD	X14, X14, X12

(551) 0x4264cc CMP	X15, X14

(551) 0x4264d0 B.NE	4264c0

0x4264d4 ORR	X9, XZR, X16

0x4264d8 CBZ	X13, 4264f8

0x4264dc SUB	X10, X11, X10,LSL #3

0x4264e0 ADD	W8, W8, #1

0x4264e4 ADD	X9, X10, X9,LSL #3

(550) 0x4264e8 SUB	W8, W8, #1

(550) 0x4264ec STR	D0, [X9], #8

(550) 0x4264f0 CMP	W8, #1

(550) 0x4264f4 B.HI	4264e8

0x4264f8 ORR	X0, XZR, XZR

0x4264fc ORR	W1, WZR, W19

0x426500 BL	404d30

0x426504 ORR	X0, XZR, XZR

0x426508 ORR	W1, WZR, W19

0x42650c BL	404900

0x426510 LDP	X8, X9, [X20, #80]

0x426514 ORR	X0, XZR, XZR

0x426518 ORR	W1, WZR, W19

0x42651c MOVZ	W21, #1

0x426520 ADD	X3, SP, #60

0x426524 ADD	X4, SP, #56

0x426528 STR	WZR, [SP, #60]

0x42652c LDR	W8, [X8]

0x426530 LDR	W9, [X9]

0x426534 ADD	X5, SP, #52

0x426538 ADD	X6, SP, #48

0x42653c MOVZ	W2, #34

0x426540 MOVZ	W7, #1

0x426544 STR	W21, [SP, #48]

0x426548 STR	W21, [SP]

0x42654c ADD	W22, W9, #2

0x426550 SUB	W8, W8, #2

0x426554 STP	W22, W8, [SP, #52]

0x426558 BL	404c10

0x42655c LDRSW	X8, [SP, #56]

0x426560 CMP	W8, W22

0x426564 B.GT	42665c

0x426568 LDR	W9, [SP, #52]

0x42656c SUBS	W9, W9, W8

0x426570 B.MI	42665c

0x426574 LDP	X11, X10, [X20]

0x426578 PTRUE	P0.D, ALL

0x42657c ADD	W9, W9, #1

0x426580 LDR	W10, [X10]

0x426584 LDR	W11, [X11]

0x426588 SUB	W13, W10, W11

0x42658c SUB	W12, W11, #2

0x426590 SBFM	X11, X12, #0, #31

0x426594 ADD	W10, W13, #5

0x426598 ADD	W12, W13, #4

0x42659c CNTW	X13, ALL

0x4265a0 ADD	X12, X12, #1

0x4265a4 B	4265b4

(547) 0x4265a8 ADD	X8, X8, #1

(547) 0x4265ac SUBS	W9, W9, #1

(547) 0x4265b0 B.LE	42665c

(547) 0x4265b4 CMP	W10, #1

(547) 0x4265b8 B.LT	4265a8

(547) 0x4265bc LDR	X14, [X20, #64]

(547) 0x4265c0 LDR	X15, [X20, #240]

(547) 0x4265c4 LDR	X16, [X20, #224]

(547) 0x4265c8 ORR	X17, XZR, X11

(547) 0x4265cc ORR	W18, WZR, W10

(547) 0x4265d0 CMP	X12, X13

(547) 0x4265d4 LDR	D0, [X14]

(547) 0x4265d8 LDR	X14, [X20, #144]

(547) 0x4265dc LDR	X15, [X15]

(547) 0x4265e0 LDR	D1, [X14]

(547) 0x4265e4 LDR	X14, [X20, #176]

(547) 0x4265e8 LDR	X14, [X14]

(547) 0x4265ec FMUL	D0, D0, D1

(547) 0x4265f0 B.CC	426638

(547) 0x4265f4 UDIV	X17, X12, X13

(547) 0x4265f8 MADD	X3, X14, X8, X11

(547) 0x4265fc ORR	X1, XZR, XZR

(547) 0x426600 DUP	Z1.D, Z0.D[0]

(547) 0x426604 SUB	X3, X3, X15

(547) 0x426608 ADD	X3, X16, X3,LSL #3

(547) 0x42660c ADDVL	X4, X3, #1

(547) 0x426610 MADD	X2, X17, X13, XZR

(547) 0x426614 SUB	X0, X12, X2

(547) 0x426618 ADD	X17, X2, X11

(547) 0x42661c SUB	W18, W10, W2

  (549) 0x426620 ST1D	{Z1.D}, P0, [X3, X1,LSL #3]

  (549) 0x426624 ST1D	{Z1.D}, P0, [X4, X1,LSL #3]

  (549) 0x426628 ADD	X1, X1, X13

  (549) 0x42662c CMP	X2, X1

  (549) 0x426630 B.NE	426620

(547) 0x426634 CBZ	X0, 4265a8

(547) 0x426638 MADD	X14, X14, X8, X17

(547) 0x42663c SUB	X14, X14, X15

(547) 0x426640 ADD	W15, W18, #1

(547) 0x426644 ADD	X14, X16, X14,LSL #3

  (548) 0x426648 SUB	W15, W15, #1

  (548) 0x42664c STR	D0, [X14], #8

  (548) 0x426650 CMP	W15, #1

  (548) 0x426654 B.HI	426648

(547) 0x426658 B	4265a8

0x42665c ORR	X0, XZR, XZR

0x426660 ORR	W1, WZR, W19

0x426664 BL	404d30

0x426668 ORR	X0, XZR, XZR

0x42666c ORR	W1, WZR, W19

0x426670 BL	404900

0x426674 LDP	X8, X9, [X20, #80]

0x426678 ORR	X0, XZR, XZR

0x42667c ORR	W1, WZR, W19

0x426680 ADD	X3, SP, #44

0x426684 ADD	X4, SP, #40

0x426688 ADD	X5, SP, #36

0x42668c STR	WZR, [SP, #44]

0x426690 LDR	W8, [X8]

0x426694 LDR	W9, [X9]

0x426698 ADD	X6, SP, #32

0x42669c MOVZ	W2, #34

0x4266a0 MOVZ	W7, #1

0x4266a4 STR	W21, [SP, #32]

0x4266a8 STR	W21, [SP]

0x4266ac SUB	W8, W8, #2

0x4266b0 ADD	W22, W9, #2

0x4266b4 STP	W22, W8, [SP, #36]

0x4266b8 BL	404c10

0x4266bc LDRSW	X8, [SP, #40]

0x4266c0 CMP	W8, W22

0x4266c4 B.GT	4267bc

0x4266c8 LDR	W9, [SP, #36]

0x4266cc SUBS	W9, W9, W8

0x4266d0 B.MI	4267bc

0x4266d4 LDP	X11, X10, [X20]

0x4266d8 PTRUE	P0.D, ALL

0x4266dc ADD	W9, W9, #1

0x4266e0 LDR	W10, [X10]

0x4266e4 LDR	W11, [X11]

0x4266e8 SUB	W13, W10, W11

0x4266ec SUB	W12, W11, #2

0x4266f0 SBFM	X11, X12, #0, #31

0x4266f4 ADD	W10, W13, #5

0x4266f8 ADD	W12, W13, #4

0x4266fc CNTW	X13, ALL

0x426700 ADD	X12, X12, #1

0x426704 B	426714

(544) 0x426708 ADD	X8, X8, #1

(544) 0x42670c SUBS	W9, W9, #1

(544) 0x426710 B.LE	4267bc

(544) 0x426714 CMP	W10, #1

(544) 0x426718 B.LT	426708

(544) 0x42671c LDR	X14, [X20, #128]

(544) 0x426720 LDR	X15, [X20, #216]

(544) 0x426724 LDR	X16, [X20, #248]

(544) 0x426728 ORR	X17, XZR, X11

(544) 0x42672c ORR	W18, WZR, W10

(544) 0x426730 CMP	X12, X13

(544) 0x426734 LDR	X14, [X14]

(544) 0x426738 SUB	X14, X8, X14

(544) 0x42673c LDR	D0, [X15, X14,LSL #3]

(544) 0x426740 LDR	X14, [X20, #40]

(544) 0x426744 LDR	X15, [X20, #264]

(544) 0x426748 LDR	X14, [X14]

(544) 0x42674c LDR	X15, [X15]

(544) 0x426750 B.CC	426798

(544) 0x426754 UDIV	X17, X12, X13

(544) 0x426758 MADD	X3, X14, X8, X11

(544) 0x42675c ORR	X1, XZR, XZR

(544) 0x426760 DUP	Z1.D, Z0.D[0]

(544) 0x426764 SUB	X3, X3, X15

(544) 0x426768 ADD	X3, X16, X3,LSL #3

(544) 0x42676c ADDVL	X4, X3, #1

(544) 0x426770 MADD	X2, X17, X13, XZR

(544) 0x426774 SUB	X0, X12, X2

(544) 0x426778 ADD	X17, X2, X11

(544) 0x42677c SUB	W18, W10, W2

  (546) 0x426780 ST1D	{Z1.D}, P0, [X3, X1,LSL #3]

  (546) 0x426784 ST1D	{Z1.D}, P0, [X4, X1,LSL #3]

  (546) 0x426788 ADD	X1, X1, X13

  (546) 0x42678c CMP	X2, X1

  (546) 0x426790 B.NE	426780

(544) 0x426794 CBZ	X0, 426708

(544) 0x426798 MADD	X14, X14, X8, X17

(544) 0x42679c SUB	X14, X14, X15

(544) 0x4267a0 ADD	W15, W18, #1

(544) 0x4267a4 ADD	X14, X16, X14,LSL #3

  (545) 0x4267a8 SUB	W15, W15, #1

  (545) 0x4267ac STR	D0, [X14], #8

  (545) 0x4267b0 CMP	W15, #1

  (545) 0x4267b4 B.HI	4267a8

(544) 0x4267b8 B	426708

0x4267bc ORR	X0, XZR, XZR

0x4267c0 ORR	W1, WZR, W19

0x4267c4 BL	404d30

0x4267c8 ORR	X0, XZR, XZR

0x4267cc ORR	W1, WZR, W19

0x4267d0 BL	404900

0x4267d4 LDP	X8, X9, [X20, #80]

0x4267d8 ORR	X0, XZR, XZR

0x4267dc ORR	W1, WZR, W19

0x4267e0 ADD	X3, SP, #28

0x4267e4 ADD	X4, SP, #24

0x4267e8 ADD	X5, SP, #20

0x4267ec STR	WZR, [SP, #28]

0x4267f0 LDR	W8, [X8]

0x4267f4 LDR	W9, [X9]

0x4267f8 ADD	X6, SP, #16

0x4267fc MOVZ	W2, #34

0x426800 MOVZ	W7, #1

0x426804 ADD	W21, W9, #2

0x426808 SUB	W8, W8, #2

0x42680c STP	W21, W8, [SP, #20]

0x426810 MOVZ	W8, #1

0x426814 STR	W8, [SP, #16]

0x426818 STR	W8, [SP]

0x42681c BL	404c10

0x426820 LDRSW	X8, [SP, #24]

0x426824 CMP	W8, W21

0x426828 B.GT	426958

0x42682c LDR	W9, [SP, #20]

0x426830 SUBS	W9, W9, W8

0x426834 B.MI	426958

0x426838 LDP	X11, X10, [X20]

0x42683c CNTW	X14, ALL

0x426840 RDVL	X15, #1

0x426844 ADD	W9, W9, #1

0x426848 LDR	W10, [X10]

0x42684c LDR	W11, [X11]

0x426850 PTRUE	P0.D, ALL

0x426854 SUB	W12, W10, W11

0x426858 SUB	W13, W11, #2

0x42685c SBFM	X11, X13, #0, #31

0x426860 SBFM	X13, X13, #61, #31

0x426864 ADD	W10, W12, #5

0x426868 ADD	W12, W12, #4

0x42686c ADD	X12, X12, #1

0x426870 B	42688c

0x426874 HINT	#0

0x426878 HINT	#0

0x42687c HINT	#0

(541) 0x426880 ADD	X8, X8, #1

(541) 0x426884 SUBS	W9, W9, #1

(541) 0x426888 B.LE	426958

(541) 0x42688c CMP	W10, #1

(541) 0x426890 B.LT	426880

(541) 0x426894 LDR	X16, [X20, #48]

(541) 0x426898 LDP	X17, X18, [X20, #176]

(541) 0x42689c LDR	X0, [X20, #240]

(541) 0x4268a0 ORR	X3, XZR, X11

(541) 0x4268a4 ORR	W2, WZR, W10

(541) 0x4268a8 CMP	X12, X14

(541) 0x4268ac LDR	X1, [X20, #272]

(541) 0x4268b0 LDR	X16, [X16]

(541) 0x4268b4 LDR	X17, [X17]

(541) 0x4268b8 LDR	X0, [X0]

(541) 0x4268bc B.CC	426924

(541) 0x4268c0 UDIV	X2, X12, X14

(541) 0x4268c4 ADD	X21, X18, X13

(541) 0x4268c8 UBFM	X22, X16, #61, #60

(541) 0x4268cc ORR	X4, XZR, XZR

(541) 0x4268d0 SUB	X7, X21, X22

(541) 0x4268d4 SUB	X22, X15, X22

(541) 0x4268d8 ADD	X21, X21, X22

(541) 0x4268dc MADD	X22, X17, X8, X11

(541) 0x4268e0 SUB	X22, X22, X0

(541) 0x4268e4 UBFM	X23, X22, #61, #60

(541) 0x4268e8 ADD	X22, X1, X23

(541) 0x4268ec ADDVL	X23, X23, #1

(541) 0x4268f0 ADD	X23, X1, X23

(541) 0x4268f4 MADD	X6, X2, X14, XZR

(541) 0x4268f8 SUB	X5, X12, X6

(541) 0x4268fc ADD	X3, X6, X11

(541) 0x426900 SUB	W2, W10, W6

  (543) 0x426904 LD1D	{Z0.D}, P0/Z, [X7, X4,LSL #3]

  (543) 0x426908 LD1D	{Z1.D}, P0/Z, [X21, X4,LSL #3]

  (543) 0x42690c ST1D	{Z0.D}, P0, [X22, X4,LSL #3]

  (543) 0x426910 ST1D	{Z1.D}, P0, [X23, X4,LSL #3]

  (543) 0x426914 ADD	X4, X4, X14

  (543) 0x426918 CMP	X6, X4

  (543) 0x42691c B.NE	426904

(541) 0x426920 CBZ	X5, 426880

(541) 0x426924 MADD	X17, X17, X8, X3

(541) 0x426928 SUB	X16, X18, X16,LSL #3

(541) 0x42692c ADD	W18, W2, #1

(541) 0x426930 SUB	X17, X17, X0

(541) 0x426934 ADD	X16, X16, X3,LSL #3

(541) 0x426938 ADD	X17, X1, X17,LSL #3

(541) 0x42693c HINT	#0

  (542) 0x426940 LDR	D0, [X16], #8

  (542) 0x426944 SUB	W18, W18, #1

  (542) 0x426948 STR	D0, [X17], #8

  (542) 0x42694c CMP	W18, #1

  (542) 0x426950 B.HI	426940

(541) 0x426954 B	426880

0x426958 ORR	X0, XZR, XZR

0x42695c ORR	W1, WZR, W19

0x426960 BL	404d30

0x426964 ORR	X0, XZR, XZR

0x426968 ORR	W1, WZR, W19

0x42696c BL	404900

0x426970 LDP	X20, X19, [SP, #224]

0x426974 LDP	X22, X21, [SP, #208]

0x426978 LDP	X30, X23, [SP, #192]

0x42697c ADD	SP, SP, #240

0x426980 RET

0x426984 HINT	#0

0x426988 HINT	#0

0x42698c HINT	#0

0x426990 HINT	#0

0x426994 HINT	#0

0x426998 HINT	#0

0x42699c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	initialise_chunk_kernel.f90-pp.f90:58-133
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90-pp.f90:58-133.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 113.25 to 17.00 cycles (6.66x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 113.25 to 65.44 cycles (1.73x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 113.25 to 16.50 cycles (6.86x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 836 bytes. The binary function is storing 268 bytes.

General properties

nb instructions	692
loop length	2768
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

83.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	37.50	37.50	113.25	113.25	113.25	113.25	5.00	5.00	1.00	1.00	52.50	52.17	52.33	23.50	23.50
cycles	37.50	37.50	113.25	113.25	113.25	113.25	5.00	5.00	1.00	1.00	52.50	52.17	52.33	23.50	23.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

8.00-4.00

Cycles summary

Front-end	83.00
Overall L1	113.25

Vectorization ratios

all	2%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 113.25 cycles. At this rate:

7% of peak load performance is reached (7.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425a90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X30, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #188]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #180	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W22, W8, [SP, #180]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 425c20 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W13, [SP, #180]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 425c20 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W14, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W13, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X11, X10, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X15, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425be0 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X16, X15, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z4.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z5.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W18, W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X16, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z6.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X18, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z2.D, X12, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X12, X18, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z3.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
ORR X12, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 425c20 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #172	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #172]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 425d38 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 425d38 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425d1c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SUB X17, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X15, X15, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 425d38 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #156	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #148	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 425ec0 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W13, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 425ec0 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W14, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W13, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X11, X10, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X15, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425e80 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X16, X15, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z4.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z5.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W18, W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X16, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z6.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X18, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z2.D, X12, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X12, X18, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z3.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ORR X12, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 425ec0 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #140	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #132	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 425fd8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 425fd8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425fbc <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SUB X17, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X15, X15, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 425fd8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #124	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #124]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #116	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W13, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42614c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42614c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W14, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 426110 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x680>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X16, X15, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
UBFM X18, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X1, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X2, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X16, X16, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X15, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 42614c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X12, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #100	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 426270 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 426270 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X10, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 426244 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SUB X17, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X15, X15, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 426270 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X13, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W13, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4263e4 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4263e4 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W14, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4263a8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X16, X15, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
UBFM X18, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X1, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X2, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X16, X16, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X15, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 4263e4 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X12, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #76	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #68	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4264f8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4264f8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X10, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 4264dc <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xa4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SUB X17, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X15, X15, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 4264f8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42665c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xbcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42665c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xbcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4265b4 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4267bc <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xd2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4267bc <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xd2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426714 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xc84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W21, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W21, W8, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 426958 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xec8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 426958 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xec8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W12, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X13, X13, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42688c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xdfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X30, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	initialise_chunk_kernel.f90-pp.f90:58-133
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 113.25 to 16.50 cycles (6.86x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 836 bytes. The binary function is storing 268 bytes.

General properties

nb instructions	692
loop length	2768
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

83.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	37.50	37.50	113.25	113.25	113.25	113.25	5.00	5.00	1.00	1.00	52.50	52.17	52.33	23.50	23.50
cycles	37.50	37.50	113.25	113.25	113.25	113.25	5.00	5.00	1.00	1.00	52.50	52.17	52.33	23.50	23.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

8.00-4.00

Cycles summary

Front-end	83.00
Overall L1	113.25

Vectorization ratios

all	2%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 113.25 cycles. At this rate:

7% of peak load performance is reached (7.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425a90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X30, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #188]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #180	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W22, W8, [SP, #180]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 425c20 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W13, [SP, #180]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 425c20 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W14, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W13, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X11, X10, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X15, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425be0 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X16, X15, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z4.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z5.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W18, W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X16, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z6.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X18, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z2.D, X12, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X12, X18, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z3.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
ORR X12, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 425c20 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #172	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #172]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 425d38 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 425d38 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425d1c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SUB X17, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X15, X15, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 425d38 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #156	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #148	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 425ec0 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W13, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 425ec0 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W14, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W13, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X11, X10, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X15, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425e80 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X16, X15, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z4.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z5.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W18, W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X16, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z6.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X18, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z2.D, X12, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X12, X18, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z3.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ORR X12, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 425ec0 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #140	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #132	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 425fd8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 425fd8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425fbc <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SUB X17, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X15, X15, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 425fd8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #124	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #124]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #116	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W13, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42614c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42614c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W14, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 426110 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x680>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X16, X15, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
UBFM X18, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X1, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X2, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X16, X16, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X15, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 42614c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X12, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #100	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 426270 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 426270 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X10, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 426244 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SUB X17, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X15, X15, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 426270 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X13, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W13, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4263e4 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4263e4 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W14, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4263a8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X16, X15, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
UBFM X18, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X1, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X2, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X16, X16, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X15, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 4263e4 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X12, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #76	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #68	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4264f8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W8, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4264f8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X10, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 4264dc <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xa4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SUB X17, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X15, X15, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X17, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 4264f8 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42665c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xbcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 42665c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xbcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4265b4 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W22, W8, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4267bc <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xd2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4267bc <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xd2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426714 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xc84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W21, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W21, W8, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 426958 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xec8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 426958 <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xec8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W12, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X13, X13, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42688c <__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_+0xdfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X30, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼__nv_initialise_chunk_kernel_module_initialise_chunk_kernel__F1L58_1_–	0.02	0.02
○Loop 553 - initialise_chunk_kernel.f90-pp.f90:97-97 - exec	0	0
○Loop 561 - initialise_chunk_kernel.f90-pp.f90:73-73 - exec	0	0
○Loop 550 - initialise_chunk_kernel.f90-pp.f90:103-104 - exec	0	0
▼Loop 541 - initialise_chunk_kernel.f90-pp.f90:128-131 - exec–	0	0
○Loop 543 - initialise_chunk_kernel.f90-pp.f90:129-129 - exec	0.01	0.01
○Loop 542 - initialise_chunk_kernel.f90-pp.f90:129-130 - exec	0	0
○Loop 560 - initialise_chunk_kernel.f90-pp.f90:73-74 - exec	0	0
○Loop 564 - initialise_chunk_kernel.f90-pp.f90:61-62 - exec	0	0
○Loop 551 - initialise_chunk_kernel.f90-pp.f90:103-103 - exec	0	0
○Loop 559 - initialise_chunk_kernel.f90-pp.f90:79-79 - exec	0	0
○Loop 552 - initialise_chunk_kernel.f90-pp.f90:97-98 - exec	0	0
○Loop 557 - initialise_chunk_kernel.f90-pp.f90:85-85 - exec	0	0
○Loop 556 - initialise_chunk_kernel.f90-pp.f90:85-86 - exec	0	0
▼Loop 544 - initialise_chunk_kernel.f90-pp.f90:119-122 - exec–	0	0
○Loop 545 - initialise_chunk_kernel.f90-pp.f90:120-121 - exec	0	0
○Loop 546 - initialise_chunk_kernel.f90-pp.f90:120-120 - exec	0	0.01
○Loop 563 - initialise_chunk_kernel.f90-pp.f90:67-67 - exec	0	0
○Loop 558 - initialise_chunk_kernel.f90-pp.f90:79-80 - exec	0	0
○Loop 554 - initialise_chunk_kernel.f90-pp.f90:91-92 - exec	0	0
○Loop 555 - initialise_chunk_kernel.f90-pp.f90:91-91 - exec	0	0
○Loop 565 - initialise_chunk_kernel.f90-pp.f90:61-61 - exec	0	0
▼Loop 547 - initialise_chunk_kernel.f90-pp.f90:110-113 - exec–	0	0
○Loop 549 - initialise_chunk_kernel.f90-pp.f90:111-111 - exec	0.01	0.01
○Loop 548 - initialise_chunk_kernel.f90-pp.f90:111-112 - exec	0	0
○Loop 562 - initialise_chunk_kernel.f90-pp.f90:67-68 - exec	0	0

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Vectorization

Details

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code