OV - exec - Function __nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1

	Function: __nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_	Module: exec	Source: ideal_gas_kernel.f90-pp.f90:45-59	Coverage: 4.33%

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/ideal_gas_kernel.f90-pp.f90: 45 - 59

--------------------------------------------------------------------------------

45: # 45 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90"

46:     !$OMP PARALLEL

47:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

48:     DO k=y_min,y_max

49:     !$OMP SIMD

50:       DO j=x_min,x_max

51:         v=1.0_8/density(j,k)

52:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

53:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

54:         pressurebyvolume=-density(j,k)*pressure(j,k)

55:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

56:         soundspeed(j,k)=SQRT(sound_speed_squared)

57:       ENDDO

58:     ENDDO

59:   !$OMP END DO

0x4253d0 SUB	SP, SP, #80

0x4253d4 STP	X30, X23, [SP, #32]

0x4253d8 STP	X22, X21, [SP, #48]

0x4253dc STP	X20, X19, [SP, #64]

0x4253e0 LDP	X8, X9, [X2]

0x4253e4 LDR	W19, [X0]

0x4253e8 ORR	X0, XZR, XZR

0x4253ec ORR	X20, XZR, X2

0x4253f0 ADD	X3, SP, #28

0x4253f4 ADD	X4, SP, #24

0x4253f8 ADD	X5, SP, #20

0x4253fc STR	WZR, [SP, #28]

0x425400 ADD	X6, SP, #16

0x425404 MOVZ	W2, #34

0x425408 MOVZ	W7, #1

0x42540c LDR	W21, [X9]

0x425410 LDR	W8, [X8]

0x425414 ORR	W1, WZR, W19

0x425418 STP	W21, W8, [SP, #20]

0x42541c MOVZ	W8, #1

0x425420 STR	W8, [SP, #16]

0x425424 STR	W8, [SP]

0x425428 BL	404c10

0x42542c LDRSW	X8, [SP, #24]

0x425430 CMP	W8, W21

0x425434 B.GT	4255c0

0x425438 LDR	W9, [SP, #20]

0x42543c SUBS	W9, W9, W8

0x425440 B.MI	4255c0

0x425444 LDP	X11, X10, [X20, #16]

0x425448 ADRP	X15,

0x42544c PTRUE	P0.D, ALL

0x425450 CNTD	X14, ALL

0x425454 FMOV	D0, #1.0000000

0x425458 FDUP	Z2.D, #112

0x42545c ADD	W9, W9, #1

0x425460 LDR	D1, [X15, #3784]

0x425464 ADRP	X15,

0x425468 ADD	X15, X15, #3784

0x42546c LD1RD	{Z3.D}, P0/Z, [X15]

0x425470 LDR	W12, [X10]

0x425474 LDRSW	X10, [X11]

0x425478 SUB	W11, W12, W10

0x42547c ADDS	W12, W11, #1

0x425480 CSINC	W13, WZR, WZR, #0

0x425484 SUB	W13, W12, W13

0x425488 ADD	X13, X13, #1

0x42548c B	4254ac

0x425490 HINT	#0

0x425494 HINT	#0

0x425498 HINT	#0

0x42549c HINT	#0

(539) 0x4254a0 ADD	X8, X8, #1

(539) 0x4254a4 SUBS	W9, W9, #1

(539) 0x4254a8 B.LE	4255c0

(539) 0x4254ac TBNZ	W11, #31, 4254a0

0x4254b0 LDR	X15, [X20, #56]

0x4254b4 LDP	X16, X0, [X20, #112]

0x4254b8 ORR	X3, XZR, X10

0x4254bc ORR	W2, WZR, W12

0x4254c0 LDR	X17, [X15]

0x4254c4 LDP	X15, X18, [X20, #96]

0x4254c8 CMP	X13, X14

0x4254cc LDR	X1, [X15]

0x4254d0 LDR	X15, [X20, #32]

0x4254d4 B.CC	425550

0x4254d8 UDIV	X2, X13, X14

0x4254dc MADD	X7, X17, X8, X10

0x4254e0 ORR	X5, XZR, XZR

0x4254e4 SUB	X7, X7, X1

0x4254e8 UBFM	X23, X7, #61, #60

0x4254ec ADD	X7, X0, X23

0x4254f0 ADD	X21, X18, X23

0x4254f4 ADD	X22, X16, X23

0x4254f8 ADD	X23, X15, X23

0x4254fc MADD	X6, X2, X14, XZR

0x425500 SUB	X4, X13, X6

0x425504 ADD	X3, X6, X10

0x425508 SUB	W2, W12, W6

(540) 0x42550c LD1D	{Z4.D}, P0/Z, [X23, X5,LSL #3]

(540) 0x425510 LD1D	{Z5.D}, P0/Z, [X22, X5,LSL #3]

(540) 0x425514 MOVPRFX	Z7, Z2

(540) 0x425518 FDIV	Z7.D, P0/M, Z7.D, Z4.D

(540) 0x42551c FMUL	Z6.D, Z4.D, Z3.D

(540) 0x425520 FMUL	Z5.D, Z6.D, Z5.D

(540) 0x425524 FMUL	Z4.D, Z4.D, Z5.D

(540) 0x425528 ST1D	{Z5.D}, P0, [X21, X5,LSL #3]

(540) 0x42552c FMLA	Z4.D, P0/M, Z6.D, Z5.D

(540) 0x425530 FMUL	Z5.D, Z7.D, Z7.D

(540) 0x425534 FMUL	Z4.D, Z5.D, Z4.D

(540) 0x425538 FSQRT	Z4.D, P0/M, Z4.D

(540) 0x42553c ST1D	{Z4.D}, P0, [X7, X5,LSL #3]

(540) 0x425540 ADD	X5, X5, X14

(540) 0x425544 CMP	X6, X5

(540) 0x425548 B.NE	42550c

0x42554c CBZ	X4, 4254a0

0x425550 MADD	X17, X17, X8, X3

0x425554 SUB	X17, X17, X1

0x425558 UBFM	X1, X17, #61, #60

0x42555c ADD	X17, X0, X1

0x425560 ADD	X18, X18, X1

0x425564 ADD	X16, X16, X1

0x425568 ADD	X15, X15, X1

0x42556c ADD	W0, W2, #1

0x425570 HINT	#0

0x425574 HINT	#0

0x425578 HINT	#0

0x42557c HINT	#0

(538) 0x425580 LDR	D4, [X15], #8

(538) 0x425584 LDR	D6, [X16], #8

(538) 0x425588 FDIV	D5, D0, D4

(538) 0x42558c FMUL	D7, D4, D1

(538) 0x425590 SUB	W0, W0, #1

(538) 0x425594 CMP	W0, #1

(538) 0x425598 FMUL	D6, D7, D6

(538) 0x42559c FMUL	D4, D4, D6

(538) 0x4255a0 STR	D6, [X18], #8

(538) 0x4255a4 FMADD	D4, D7, D6, D4

(538) 0x4255a8 FMUL	D5, D5, D5

(538) 0x4255ac FMUL	D4, D5, D4

(538) 0x4255b0 FSQRT	D4, D4

(538) 0x4255b4 STR	D4, [X17], #8

(538) 0x4255b8 B.HI	425580

0x4255bc B	4254a0

0x4255c0 ORR	X0, XZR, XZR

0x4255c4 ORR	W1, WZR, W19

0x4255c8 BL	404d30

0x4255cc ORR	X0, XZR, XZR

0x4255d0 ORR	W1, WZR, W19

0x4255d4 BL	404900

0x4255d8 LDP	X20, X19, [SP, #64]

0x4255dc LDP	X22, X21, [SP, #48]

0x4255e0 LDP	X30, X23, [SP, #32]

0x4255e4 ADD	SP, SP, #80

0x4255e8 RET

0x4255ec HINT	#0

0x4255f0 HINT	#0

0x4255f4 HINT	#0

0x4255f8 HINT	#0

0x4255fc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ideal_gas_kernel.f90-pp.f90:45-59
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/ideal_gas_kernel.f90-pp.f90:45-59.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 1.00 cycles (14.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 14.00 to 8.77 cycles (1.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.00 to 1.50 cycles (9.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 188 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	105
loop length	420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	14.00	14.00	14.00	14.00	0.50	0.50	0.50	0.50	9.00	9.00	9.00	3.50	3.50
cycles	5.00	5.00	14.00	14.00	14.00	14.00	0.50	0.50	0.50	0.50	9.00	9.00	9.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	11.50
Overall L1	14.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

13% of peak load performance is reached (13.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4253d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X30, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W21, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W21, W8, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4255c0 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4255c0 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADRP X15, <456448>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDUP Z2.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X15, #3784]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADRP X15, <456464>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #3784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z3.D}, P0/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W11, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDS W12, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4254ac <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
LDR X15, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X16, X0, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X3, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X18, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X1, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425550 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X2, X13, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X7, X17, X8, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X5, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X23, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X16, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X15, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X6, X2, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X4, X13, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X6, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W12, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X4, 4254a0 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X17, X17, X8, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X17, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X1, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W0, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 4254a0 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X30, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	ideal_gas_kernel.f90-pp.f90:45-59
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.00 to 1.50 cycles (9.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 188 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	105
loop length	420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	14.00	14.00	14.00	14.00	0.50	0.50	0.50	0.50	9.00	9.00	9.00	3.50	3.50
cycles	5.00	5.00	14.00	14.00	14.00	14.00	0.50	0.50	0.50	0.50	9.00	9.00	9.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	11.50
Overall L1	14.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

13% of peak load performance is reached (13.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4253d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X30, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W21, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W21, W8, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404c10 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4255c0 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.MI 4255c0 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADRP X15, <456448>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDUP Z2.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X15, #3784]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADRP X15, <456464>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #3784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z3.D}, P0/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W11, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDS W12, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W13, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4254ac <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
LDR X15, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X16, X0, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X3, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X18, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X1, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 425550 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X2, X13, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X7, X17, X8, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X5, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X23, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X16, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X15, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X6, X2, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X4, X13, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X6, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W12, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X4, 4254a0 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X17, X17, X8, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X17, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X1, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W0, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 4254a0 <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404d30 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404900 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X30, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_–	4.33	5.87
○Loop 540 - ideal_gas_kernel.f90-pp.f90:50-55 - exec	4.33	5.85
○Loop 539 - ideal_gas_kernel.f90-pp.f90:49-57 - exec	0	0.01
○Loop 538 - ideal_gas_kernel.f90-pp.f90:50-56 - exec	0	0

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