	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/run/oneview_runs/compilers/gcc_2/oneview_results_1786617427 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/run/oneview_runs/compilers/gcc_2/oneview_results_1786617427


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/run/binaries/gcc_2/exec
  Timestamp:			2026-08-13 12:37:07
  Universal Timestamp:		1786617427
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			isix06.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		GRANITE_RAPIDS
  Model Name:			Intel(R) Xeon(R) 6972P
  Cache Size:			491520 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.31.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Sat Aug 1 05:38:01 EDT 2026
  Compilation Options:		
		exec: GNU Fortran2008 15.1.0 -march=graniterapids -mprefer-vector-width=512 -g -O3 -O3 -ffast-math -fno-omit-frame-pointer -fcf-protection=none -fopenmp -funroll-loops -fintrinsic-modules-path /cluster/comp/gcc/15.1.0/lib/gcc/x86_64-pc-linux-gnu/15.1.0/finclude -fpre-include=/usr/include/finclude/math-vector-fortran.h 
  Number of processes observed:	6
  Number of threads observed:	192
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				36.36 s
  Max (Thread Active Time):		36.01 s
  Average Active Time:			35.80 s
  Activity Ratio:			99.6 %
  Average number of active threads:	189.017
  Affinity Stability:			99.7 %
  Time spent in analyzed loops:		95.5 %
  Time spent in analyzed innermost loops: 95.3 %
  Time spent in user code:		95.5 %
  Compilation Options Score:		100
  Array Access Efficiency:		96.8 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.09
  Perfect OpenMP/MPI/Pthread/TBB:	1.03
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.05
  If No Scalar Integer:
      Potential Speedup:		1.02
      Nb Loops to get 80%:		3
  If FP Vectorized:
      Potential Speedup:		1.10
      Nb Loops to get 80%:		4
  If Fully Vectorized:
      Potential Speedup:		1.12
      Nb Loops to get 80%:		5
  If Only FP Arithmetic:
      Potential Speedup:		1.13
      Nb Loops to get 80%:		8




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 9      | 19     | 27     | 37     | 
      Cumulated Speedup | 1.0046 | 1.0160 | 1.0160 | 1.0160 | 1.0160 | 
  Top 5 loops:
    exec - 82:	1.0046
    exec - 68:	1.009
    exec - 117:	1.0129
    exec - 108:	1.0153
    exec - 74:	1.0157

  If FP Vectorized:
      Number of loops   | 1      | 9      | 19     | 27     | 37     | 
      Cumulated Speedup | 1.0243 | 1.1044 | 1.1044 | 1.1044 | 1.1044 | 
  Top 5 loops:
    exec - 82:	1.0243
    exec - 74:	1.0488
    exec - 164:	1.0677
    exec - 108:	1.0851
    exec - 117:	1.1027

  If Fully Vectorized:
      Number of loops   | 1      | 9      | 19     | 27     | 37     | 
      Cumulated Speedup | 1.0258 | 1.1221 | 1.1222 | 1.1222 | 1.1222 | 
  Top 5 loops:
    exec - 82:	1.0258
    exec - 74:	1.0515
    exec - 117:	1.072
    exec - 108:	1.0929
    exec - 164:	1.1135

  If Only FP Arithmetic:
      Number of loops   | 1      | 9      | 19     | 27     | 37     | 
      Cumulated Speedup | 1.0237 | 1.1151 | 1.1315 | 1.1315 | 1.1315 | 
  Top 5 loops:
    exec - 353:	1.0237
    exec - 371:	1.0453
    exec - 356:	1.0679
    exec - 82:	1.0822
    exec - 74:	1.0932



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (36.01 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9990261011727 / 3] Most of time spent in analyzed modules (99.97%) comes from functions compiled with architecture specialization option
-march=graniterapids


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.00 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (95.45%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 98.45% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.59% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (6.42%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (95.33%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.69%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [3 / 3] Functions mostly use all threads
Functions running on a reduced number of threads (typically sequential code) cover less than 10% of application
walltime (2.45%)

  [3 / 3] Cumulative Outermost/In between loops coverage (0.12%) lower than cumulative innermost loop coverage (95.33%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 54  :
     analysis: Execution Time: 6 % - Vectorization Ratio: 95.00 % - Vector Length Use: 95.63 %
     Loop Computation Issues: 12
        [12] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 3
            issues (= instructions) costing 4 points each.
     Data Access Issues: 5
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [1] [SA] Presence of special instructions executing on a single port (BROADCAST) - Simplify data access and
            try to get stride 1 access. There are 1 issues (= instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 2
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
     Inefficient Vectorization: 1
        [1] [SA] Presence of special instructions executing on a single port (BROADCAST) - Simplify data access and
            try to get stride 1 access. There are 1 issues (= instructions) costing 1 point each.

   + exec - 68  :
     analysis: Execution Time: 5 % - Vectorization Ratio: 100.00 % - Vector Length Use: 100.00 %
     Loop Computation Issues: 4
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
     Data Access Issues: 2
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.

   + exec - 56  :
     analysis: Execution Time: 5 % - Vectorization Ratio: 94.44 % - Vector Length Use: 95.14 %
     Loop Computation Issues: 12
        [12] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 3
            issues (= instructions) costing 4 points each.
     Data Access Issues: 5
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [1] [SA] Presence of special instructions executing on a single port (BROADCAST) - Simplify data access and
            try to get stride 1 access. There are 1 issues (= instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 2
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
     Inefficient Vectorization: 1
        [1] [SA] Presence of special instructions executing on a single port (BROADCAST) - Simplify data access and
            try to get stride 1 access. There are 1 issues (= instructions) costing 1 point each.

   + exec - 231 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 100.00 % - Vector Length Use: 100.00 %
     Loop Computation Issues: 36
        [32] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 8
            issues (= instructions) costing 4 points each.
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.

   + exec - 115 :
     analysis: Execution Time: 4 % - Vectorization Ratio: 100.00 % - Vector Length Use: 100.00 %
     Loop Computation Issues: 16
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 95.47  | 0.20    | 0.00    | 0.00   | 0.13   | 0.03  | 0.00  | 4.17  | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 3                         | 67.16                     | 67.16                     |
   4% to 8%                   | 4                         | 19.60                     | 86.76                     |
   2% to 4%                   | 4                         | 11.12                     | 97.88                     |
   1% to 2%                   | 1                         | 1.18                      | 99.06                     |
   0.5% to 1%                 | 0                         | 0.00                      | 99.06                     |
   0.25% to 0.5%              | 1                         | 0.30                      | 99.36                     |
   0.125% to 0.25%            | 2                         | 0.33                      | 99.69                     |
   < 0.125%                   | 63                        | 0.31                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 0                         | 0.00                      | 0.00                      |
   4% to 8%                   | 7                         | 35.70                     | 35.70                     |
   2% to 4%                   | 17                        | 51.61                     | 87.31                     |
   1% to 2%                   | 4                         | 5.69                      | 93.00                     |
   0.5% to 1%                 | 2                         | 1.96                      | 94.96                     |
   0.25% to 0.5%              | 1                         | 0.30                      | 95.25                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 95.25                     |
   < 0.125%                   | 17                        | 0.08                      | 95.33                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0  | exec                | 34.75          | 12.44          |
   __advec_cell_kernel_module_MOD_advec_cell_kernel._o... | exec                | 20.55          | 7.35           |
   __pdv_kernel_module_MOD_pdv_kernel._omp_fn.0           | exec                | 11.86          | 4.25           |
   __accelerate_kernel_module_MOD_accelerate_kernel._o... | exec                | 5.63           | 2.02           |
   __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp... | exec                | 5.01           | 1.79           |
   __reset_field_kernel_module_MOD_reset_field_kernel.... | exec                | 4.96           | 1.77           |
   __flux_calc_kernel_module_MOD_flux_calc_kernel._omp... | exec                | 4.01           | 1.43           |
   __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0   | exec                | 3.38           | 1.21           |
   gomp_team_barrier_wait_end                             | libgomp.so.1.0.0    | 2.88           | 1.03           |
   __viscosity_kernel_module_MOD_viscosity_kernel._omp... | exec                | 2.54           | 0.91           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   54             | exec                | PdV_kernel.f90:114-123,PdV_kernel.f90:129-135          | 6.42           |
   68             | exec                | accelerate_kernel.f90:67-76                            | 5.63           |
   56             | exec                | PdV_kernel.f90:78-87,PdV_kernel.f90:93-99              | 5.44           |
   231            | exec                | ideal_gas_kernel.f90:50-55                             | 5.01           |
   115            | exec                | advec_mom_kernel.f90:248-248                           | 4.61           |
   106            | exec                | advec_mom_kernel.f90:184-184                           | 4.59           |
   178            | exec                | flux_calc_kernel.f90:58-60                             | 4.00           |
   73             | exec                | advec_cell_kernel.f90:165-170                          | 3.75           |
   74             | exec                | advec_cell_kernel.f90:110-118,advec_cell_kernel.f90... | 3.71           |
   82             | exec                | advec_cell_kernel.f90:202-204,advec_cell_kernel.f90... | 3.70           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 54 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:114-123,129-135.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

15% of peak computational performance is used (4.85 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
95% of vector register length is used (average across all SSE/AVX instructions).


Details
95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 96% of SSE/AVX loads are used in vector version.
 - 83% of SSE/AVX multiply instructions are used in vector version.
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.1.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 48.00 to 16.50 cycles (2.91x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.1.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 14.33 cycles (3.35x speedup).


      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 24 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VDIVPD: 3 occurrences<<list_path_1_complex_1>>



      6.1.1.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
26 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.1.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 233 FP arithmetical operations:
 - 144: addition or subtraction (24 inside FMA instructions)
 - 65: multiply (24 inside FMA instructions)
 - 24: divide
The binary loop is loading 1808 bytes (226 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.1.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.







      6.1.2  -  Loop 68 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67-76.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

53% of peak computational performance is used (17.08 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 17.33 to 16.00 cycles (1.08x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
 - For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop



      6.1.2.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.2.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by reading data from caches/RAM (load units are a bottleneck).


Workaround
 - Read less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.2.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 80 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.2.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VDIVPD: 1 occurrences<<list_path_1_complex_1>>



      6.1.2.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

27 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.2.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 296 FP arithmetical operations:
 - 152: addition or subtraction (80 inside FMA instructions)
 - 136: multiply (80 inside FMA instructions)
 - 8: divide
The binary loop is loading 2432 bytes (304 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.2.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.







      6.1.3  -  Loop 56 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:78-87,93-99.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

13% of peak computational performance is used (4.19 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
95% of vector register length is used (average across all SSE/AVX instructions).


Details
94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 94% of SSE/AVX loads are used in vector version.
 - 83% of SSE/AVX multiply instructions are used in vector version.
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 48.00 to 14.50 cycles (3.31x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.3.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 11.50 cycles (4.17x speedup).


      6.1.3.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 24 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.3.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VDIVPD: 3 occurrences<<list_path_1_complex_1>>



      6.1.3.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.3.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
22 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.3.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 201 FP arithmetical operations:
 - 112: addition or subtraction (24 inside FMA instructions)
 - 65: multiply (24 inside FMA instructions)
 - 24: divide
The binary loop is loading 1232 bytes (154 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.3.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.







      6.1.4  -  Loop 231 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:50-55.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

5% of peak computational performance is used (1.88 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.4.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 136.00 to 24.00 cycles (5.67x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.4.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 136.00 to 16.00 cycles (8.50x speedup).




      6.1.4.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VDIVPD: 4 occurrences<<list_path_1_complex_1>>
 - VSQRTPD: 4 occurrences<<list_path_1_complex_2>>



      6.1.4.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

32 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.4.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 256 FP arithmetical operations:
 - 192: multiply
 - 32: divide
 - 32: square root
The binary loop is loading 768 bytes (96 double precision FP elements).
The binary loop is storing 512 bytes (64 double precision FP elements).


      6.1.4.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.







      6.1.5  -  Loop 115 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:248.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

6% of peak computational performance is used (2.00 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.5.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 64.00 to 10.00 cycles (6.40x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.5.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 64.00 to 6.00 cycles (10.67x speedup).


      6.1.5.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 32 FMA (fused multiply-add) operations.




      6.1.5.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VDIVPD: 4 occurrences<<list_path_1_complex_1>>



      6.1.5.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.5.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 128 FP arithmetical operations:
 - 64: addition or subtraction (32 inside FMA instructions)
 - 32: multiply (all inside FMA instructions)
 - 32: divide
The binary loop is loading 1280 bytes (160 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.5.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.6  -  Loop 106 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

6% of peak computational performance is used (2.00 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 64.00 to 10.00 cycles (6.40x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.6.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 64.00 to 6.00 cycles (10.67x speedup).


      6.1.6.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 32 FMA (fused multiply-add) operations.




      6.1.6.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VDIVPD: 4 occurrences<<list_path_1_complex_1>>



      6.1.6.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.6.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 128 FP arithmetical operations:
 - 64: addition or subtraction (32 inside FMA instructions)
 - 32: multiply (all inside FMA instructions)
 - 32: divide
The binary loop is loading 1280 bytes (160 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.6.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.7  -  Loop 178 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:58-60.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

41% of peak computational performance is used (13.12 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
82% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 12.50 to 10.50 cycles (1.19x speedup).

Details
80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 83% of SSE/AVX loads are used in vector version.
 - 66% of SSE/AVX multiply instructions are used in vector version.
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
Use vector aligned instructions:
 1) The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
 2) Use another compiler or locally use C code (for instance via libraries)



      6.1.7.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.7.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.44x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.7.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant non-unit stride: 12 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.7.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
20 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.7.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 164 FP arithmetical operations:
 - 96: addition or subtraction
 - 68: multiply
The binary loop is loading 1328 bytes (166 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.7.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.


      6.1.7.1.8  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N







      6.1.8  -  Loop 73 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:165-170.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

7% of peak computational performance is used (2.50 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.8.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 64.00 to 13.00 cycles (4.92x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.8.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 64.00 to 9.00 cycles (7.11x speedup).


      6.1.8.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 16 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.8.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VDIVPD: 4 occurrences<<list_path_1_complex_1>>



      6.1.8.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

18 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.8.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 160 FP arithmetical operations:
 - 96: addition or subtraction (16 inside FMA instructions)
 - 32: multiply (16 inside FMA instructions)
 - 32: divide
The binary loop is loading 1160 bytes (145 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.8.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.







      6.1.9  -  Loop 74 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110-118,124-155.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=8
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)


      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

6% of peak computational performance is used (1.92 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 14% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 16.67 to 6.00 cycles (2.78x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)<<image_col_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)



      6.1.9.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.9.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.09x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VBLENDVPD: 2 occurrences<<list_path_1_complex_1>>



      6.1.9.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

37 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.9.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 32 FP arithmetical operations:
 - 12: addition or subtraction (4 inside FMA instructions)
 - 17: multiply (4 inside FMA instructions)
 - 3: divide
The binary loop is loading 248 bytes (31 double precision FP elements).
The binary loop is storing 24 bytes (3 double precision FP elements).


      6.1.9.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.


      6.1.9.1.8  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N







      6.1.10  -  Loop 82 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202-204,216-246.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=8
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)


      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

5% of peak computational performance is used (1.70 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 18.83 to 16.50 cycles (1.14x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
 - For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop



      6.1.10.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 14% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 18.83 to 6.00 cycles (3.14x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)<<image_col_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)



      6.1.10.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.10.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.05x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.10.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VBLENDVPD: 2 occurrences<<list_path_1_complex_1>>



      6.1.10.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

37 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.10.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 32 FP arithmetical operations:
 - 12: addition or subtraction (4 inside FMA instructions)
 - 17: multiply (4 inside FMA instructions)
 - 3: divide
The binary loop is loading 328 bytes (41 double precision FP elements).
The binary loop is storing 24 bytes (3 double precision FP elements).


      6.1.10.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.


      6.1.10.1.9  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N





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