OV - exec - Loop 969

	Loop Id: 969	Module: exec	Source: viscosity_kernel.f90:53-89	Coverage: 2.22%

0x451fb0 VCMPPD	$0x1,%YMM13,%YMM18,%K2

0x451fb7 VBROADCASTSD	0xaffa0(%RIP),%YMM7    [10]

0x451fc0 VBLENDMPD	%YMM7,%YMM20,%YMM4{%K2}

0x451fc6 VBROADCASTSD	0x930e0(%RIP),%YMM19    [10]

0x451fd0 VANDPD	%YMM19,%YMM18,%YMM5

0x451fd6 VMAXPD	%YMM1,%YMM5,%YMM5

0x451fda VMULPD	%YMM5,%YMM4,%YMM5

0x451fde VCMPPD	$0x1,%YMM13,%YMM5,%K2

0x451fe5 VBLENDMPD	%YMM7,%YMM20,%YMM7{%K2}

0x451feb VANDPD	%YMM19,%YMM17,%YMM8

0x451ff1 VMAXPD	%YMM1,%YMM8,%YMM8

0x451ff5 VMULPD	%YMM7,%YMM8,%YMM8

0x451ff9 VMULPD	%YMM5,%YMM5,%YMM10

0x451ffd VFMADD231PD	%YMM8,%YMM8,%YMM10

0x452002 VSQRTPD	%YMM10,%YMM10

0x452007 VMULPD	%YMM21,%YMM10,%YMM15

0x45200d VDIVPD	%YMM5,%YMM15,%YMM5

0x452011 VANDPD	%YMM19,%YMM5,%YMM5

0x452017 VMULPD	%YMM26,%YMM10,%YMM15

0x45201d VDIVPD	%YMM8,%YMM15,%YMM8

0x452022 VANDPD	%YMM19,%YMM8,%YMM8

0x452028 VMINPD	%YMM8,%YMM5,%YMM15

0x45202d VMULPD	%YMM15,%YMM15,%YMM17

0x452033 VMULPD	%YMM16,%YMM16,%YMM16

0x452039 VADDPD	%YMM17,%YMM17,%YMM18

0x45203f VMULPD	%YMM18,%YMM16,%YMM16

0x452045 IMUL	%R8,%RDI

0x452049 ADD	0x158(%RSP),%RDI    [13]

0x452051 VMOVUPD	(%RDI,%R12,8),%YMM18{%K1}{z}    [5]

0x452058 VPBROADCASTQ	%R12,%YMM19

0x45205e VPADDQ	0x931f8(%RIP),%YMM19,%YMM19    [10]

0x452068 VMOVDQA64	%YMM19,%YMM0{%K1}

0x45206e VMOVAPD	%YMM4,%YMM31{%K1}

0x452074 VMOVDQA64	%YMM19,%YMM2{%K1}

0x45207a VMOVAPD	%YMM7,%YMM29{%K1}

0x452080 VMOVDQA64	%YMM19,%YMM9{%K1}

0x452086 VMOVAPD	%YMM10,%YMM27{%K1}

0x45208c VMOVDQA64	%YMM19,%YMM6{%K1}

0x452092 VMOVAPD	%YMM5,%YMM25{%K1}

0x452098 VMOVDQA64	%YMM19,%YMM3{%K1}

0x45209e VMOVAPD	%YMM8,%YMM24{%K1}

0x4520a4 VMOVDQA64	%YMM19,%YMM11{%K1}

0x4520aa VMOVAPD	%YMM15,%YMM23{%K1}

0x4520b0 VMOVDQA64	%YMM19,%YMM12{%K1}

0x4520b6 VMOVAPD	%YMM17,%YMM22{%K1}

0x4520bc VMULPD	%YMM18,%YMM16,%YMM4{%K1}{z}

0x4520c2 VMOVUPD	%YMM4,(%R10,%R12,8)    [1]

0x4520c8 ADD	$0x4,%R12

0x4520cc CMP	0x20(%RSP),%R12    [13]

0x4520d1 JAE	452250

0x4520d7 VMOVUPD	-0x8(%RAX,%R12,8),%YMM16    [7]

0x4520e2 VMOVUPD	(%RAX,%R12,8),%YMM17    [7]

0x4520e9 VMOVUPD	-0x8(%RCX,%R12,8),%YMM18    [2]

0x4520f4 VMOVUPD	(%RCX,%R12,8),%YMM19    [2]

0x4520fb VADDPD	%YMM17,%YMM19,%YMM21

0x452101 VADDPD	%YMM18,%YMM16,%YMM5

0x452107 VSUBPD	%YMM5,%YMM21,%YMM5

0x45210d VMOVUPD	-0x8(%R9,%R12,8),%YMM7    [12]

0x452114 VMOVAPD	%YMM20,%YMM13

0x45211a VMOVUPD	(%R9,%R12,8),%YMM20    [12]

0x452121 VMOVUPD	-0x8(%R15,%R12,8),%YMM15    [11]

0x452128 VMOVUPD	(%R15,%R12,8),%YMM4    [11]

0x45212e VADDPD	%YMM7,%YMM20,%YMM8

0x452134 VADDPD	%YMM4,%YMM15,%YMM10

0x452138 VMOVUPD	-0x8(%R11,%R12,8),%YMM21    [8]

0x452143 VSUBPD	%YMM10,%YMM8,%YMM8

0x452148 VMULPD	%YMM5,%YMM21,%YMM10

0x45214e VFMADD231PD	%YMM8,%YMM26,%YMM10

0x452154 VADDPD	%YMM16,%YMM17,%YMM16

0x45215a VSUBPD	%YMM16,%YMM19,%YMM16

0x452160 VADDPD	%YMM18,%YMM16,%YMM16

0x452166 VBROADCASTSD	0x93dc0(%RIP),%YMM19    [10]

0x452170 VMULPD	%YMM19,%YMM16,%YMM16

0x452176 VADDPD	%YMM7,%YMM15,%YMM7

0x45217a VSUBPD	%YMM7,%YMM20,%YMM7

0x452180 VMOVAPD	%YMM13,%YMM20

0x452186 VXORPD	%XMM13,%XMM13,%XMM13

0x45218b VADDPD	%YMM4,%YMM7,%YMM4

0x45218f VMULPD	%YMM19,%YMM4,%YMM4

0x452195 VDIVPD	%YMM21,%YMM20,%YMM7

0x45219b VMULPD	%YMM7,%YMM4,%YMM4

0x45219f VFMADD231PD	%YMM16,%YMM28,%YMM4

0x4521a5 VMOVUPD	(%RSI,%R12,8),%YMM15    [4]

0x4521ab VSUBPD	-0x10(%RSI,%R12,8),%YMM15,%YMM15    [4]

0x4521b2 VADDPD	(%R11,%R12,8),%YMM21,%YMM16    [8]

0x4521b9 VMOVUPD	(%R14,%R12,8),%YMM17    [3]

0x4521c0 VSUBPD	(%RDX,%R12,8),%YMM17,%YMM17    [14]

0x4521c7 VDIVPD	%YMM16,%YMM15,%YMM18

0x4521cd VMULPD	%YMM30,%YMM17,%YMM17

0x4521d3 VMULPD	%YMM18,%YMM18,%YMM15

0x4521d9 VMULPD	%YMM17,%YMM17,%YMM16

0x4521df VMULPD	%YMM19,%YMM5,%YMM5

0x4521e5 VMULPD	%YMM7,%YMM5,%YMM5

0x4521e9 VMULPD	%YMM5,%YMM15,%YMM5

0x4521ed VMULPD	%YMM19,%YMM8,%YMM7

0x4521f3 VMULPD	%YMM16,%YMM7,%YMM7

0x4521f9 VMULPD	%YMM4,%YMM18,%YMM4

0x4521ff VFMADD213PD	%YMM5,%YMM17,%YMM4

0x452205 VFMADD231PD	%YMM7,%YMM28,%YMM4

0x45220b VADDPD	%YMM15,%YMM16,%YMM5

0x452211 VMAXPD	%YMM1,%YMM5,%YMM5

0x452215 VDIVPD	%YMM5,%YMM4,%YMM16

0x45221b VCMPPD	$0x6,%YMM10,%YMM13,%K1

0x452222 VCMPPD	$0x5,%YMM16,%YMM13,%K1{%K1}

0x452229 KORTESTB	%K1,%K1

0x45222d JE	451fb0

0x452233 MOV	0x88(%RBP),%RDI    [9]

0x45223a MOV	(%RDI),%RDI    [6]

0x45223d JMP	451fb0

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 53 - 89

--------------------------------------------------------------------------------

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.16
Bottlenecks
Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source	viscosity_kernel.f90:53-89
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	49.00
CQA cycles if no scalar integer	49.00
CQA cycles if FP arith vectorized	49.00
CQA cycles if fully vectorized	49.00
Front-end cycles	18.42
P0 cycles	22.67
P1 cycles	22.67
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	0.50
P5 cycles	22.67
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	7.33
DIV/SQRT cycles	49.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	107.50
Nb uops	107.50
Nb loads	22.00
Nb stores	1.00
Nb stack references	2.50
FLOP/cycle	4.49
Nb FLOP add-sub	68.00
Nb FLOP mul	88.00
Nb FLOP fma	20.00
Nb FLOP div	20.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.08
Bytes prefetched	0.00
Bytes loaded	560.00
Bytes stored	32.00
Stride 0	2.50
Stride 1	4.00
Stride n	0.00
Stride unknown	0.50
Stride indirect	0.00
Vectorization ratio all	95.96
Vectorization ratio load	84.21
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	88.57
Vector-efficiency ratio all	48.23
Vector-efficiency ratio load	44.08
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.16
Bottlenecks	P0,
Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source	viscosity_kernel.f90:53-89
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	49.00
CQA cycles if no scalar integer	49.00
CQA cycles if FP arith vectorized	49.00
CQA cycles if fully vectorized	49.00
Front-end cycles	18.67
P0 cycles	22.67
P1 cycles	22.67
P2 cycles	7.67
P3 cycles	7.67
P4 cycles	0.50
P5 cycles	22.67
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	7.67
DIV/SQRT cycles	49.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	109.00
Nb uops	109.00
Nb loads	23.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	4.49
Nb FLOP add-sub	68.00
Nb FLOP mul	88.00
Nb FLOP fma	20.00
Nb FLOP div	20.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.24
Bytes prefetched	0.00
Bytes loaded	568.00
Bytes stored	32.00
Stride 0	3.00
Stride 1	4.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	95.96
Vectorization ratio load	84.21
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	88.57
Vector-efficiency ratio all	48.23
Vector-efficiency ratio load	44.08
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.16
Bottlenecks	P0,
Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source	viscosity_kernel.f90:53-89
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	49.00
CQA cycles if no scalar integer	49.00
CQA cycles if FP arith vectorized	49.00
CQA cycles if fully vectorized	49.00
Front-end cycles	18.17
P0 cycles	22.67
P1 cycles	22.67
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	0.50
P5 cycles	22.67
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	7.00
DIV/SQRT cycles	49.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	106.00
Nb uops	106.00
Nb loads	21.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	4.49
Nb FLOP add-sub	68.00
Nb FLOP mul	88.00
Nb FLOP fma	20.00
Nb FLOP div	20.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.92
Bytes prefetched	0.00
Bytes loaded	552.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	95.96
Vectorization ratio load	84.21
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	88.57
Vector-efficiency ratio all	48.23
Vector-efficiency ratio load	44.08
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	viscosity_kernel.f90:53-89
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:53-89.

It is main loop of related source loop which is unrolled by 4 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

84% of SSE/AVX loads are used in vector version.
88% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 49.00 to 25.00 cycles (1.96x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 0 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

58 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 220 FP arithmetical operations:

88: addition or subtraction (20 inside FMA instructions)
108: multiply (20 inside FMA instructions)
20: divide
4: square root

The binary loop is loading 560 bytes (70 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	107.50
nb uops	107.50
loop length	650.50
used x86 registers	13.50
used mmx registers	0
used xmm registers	1
used ymm registers	31
used zmm registers	0
nb stack references	2.50
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	18.42 cycles
front end	18.42 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	22.67	22.67	7.33	7.33	0.50	22.67	2.00	0.50	0.50	0.50	2.00	7.33
cycles	22.67	22.67	7.33	7.33	0.50	22.67	2.00	0.50	0.50	0.50	2.00	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	49.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	18.42
Dispatch	22.67
DIV/SQRT	49.00
Data deps.	4.00
Overall L1	49.00

Vectorization ratios

INT

all	88%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	87%

all	96%
load	83%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	95%
load	84%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

Vector efficiency ratios

INT

all	45%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	45%

all	48%
load	43%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	44%

INT+FP

all	48%
load	44%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	45%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 49.00 cycles. At this rate:

5% of peak load performance is reached (11.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	viscosity_kernel.f90:53-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

84% of SSE/AVX loads are used in vector version.
88% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 49.00 to 22.67 cycles (2.16x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 49.00 to 25.00 cycles (1.96x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 13 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 13 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:89
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:53
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:60
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:65
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:66

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

58 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 220 FP arithmetical operations:

88: addition or subtraction (20 inside FMA instructions)
108: multiply (20 inside FMA instructions)
20: divide
4: square root

The binary loop is loading 568 bytes (71 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	109
nb uops	109
loop length	658
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	31
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.67 cycles
front end	18.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	22.67	22.67	7.67	7.67	0.50	22.67	2.00	0.50	0.50	0.50	2.00	7.67
cycles	22.67	22.67	7.67	7.67	0.50	22.67	2.00	0.50	0.50	0.50	2.00	7.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	49.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	18.67
Dispatch	22.67
DIV/SQRT	49.00
Data deps.	4.00
Overall L1	49.00

Vectorization ratios

INT

all	88%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	87%

all	96%
load	83%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	95%
load	84%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

Vector efficiency ratios

INT

all	45%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	45%

all	48%
load	43%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	44%

INT+FP

all	48%
load	44%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	45%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 49.00 cycles. At this rate:

6% of peak load performance is reached (11.59 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4520d7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCMPPD $0x1,%YMM13,%YMM18,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD 0xaffa0(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBLENDMPD %YMM7,%YMM20,%YMM4{%K2}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VBROADCASTSD 0x930e0(%RIP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VANDPD %YMM19,%YMM18,%YMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMAXPD %YMM1,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM5,%YMM4,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM13,%YMM5,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBLENDMPD %YMM7,%YMM20,%YMM7{%K2}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM19,%YMM17,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMAXPD %YMM1,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM5,%YMM5,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM10,%YMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMULPD %YMM21,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM5,%YMM15,%YMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VANDPD %YMM19,%YMM5,%YMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMULPD %YMM26,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM15,%YMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VANDPD %YMM19,%YMM8,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMINPD %YMM8,%YMM5,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM15,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM16,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM17,%YMM17,%YMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM18,%YMM16,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD 0x158(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMOVUPD (%RDI,%R12,8),%YMM18{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPBROADCASTQ %R12,%YMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ 0x931f8(%RIP),%YMM19,%YMM19	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VMOVDQA64 %YMM19,%YMM0{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM4,%YMM31{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM7,%YMM29{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM9{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM10,%YMM27{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM6{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM5,%YMM25{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM3{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM8,%YMM24{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM15,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM17,%YMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMULPD %YMM18,%YMM16,%YMM4{%K1}{z}	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM4,(%R10,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x4,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x20(%RSP),%R12	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JAE 452250 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x760>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD -0x8(%RAX,%R12,8),%YMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RAX,%R12,8),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD -0x8(%RCX,%R12,8),%YMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RCX,%R12,8),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM17,%YMM19,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM18,%YMM16,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM21,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x8(%R9,%R12,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM20,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD (%R9,%R12,8),%YMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD -0x8(%R15,%R12,8),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R15,%R12,8),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM7,%YMM20,%YMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM4,%YMM15,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x8(%R11,%R12,8),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM10,%YMM8,%YMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM5,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM26,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM16,%YMM17,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM16,%YMM19,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM18,%YMM16,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x93dc0(%RIP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM19,%YMM16,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM7,%YMM15,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM7,%YMM20,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM13,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDPD %YMM4,%YMM7,%YMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM19,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM21,%YMM20,%YMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM7,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM16,%YMM28,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD (%RSI,%R12,8),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD -0x10(%RSI,%R12,8),%YMM15,%YMM15	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VADDPD (%R11,%R12,8),%YMM21,%YMM16	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVUPD (%R14,%R12,8),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD (%RDX,%R12,8),%YMM17,%YMM17	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VDIVPD %YMM16,%YMM15,%YMM18	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM30,%YMM17,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM18,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM17,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM5,%YMM15,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM8,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM18,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM5,%YMM17,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM7,%YMM28,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM15,%YMM16,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMAXPD %YMM1,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM5,%YMM4,%YMM16	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VCMPPD $0x6,%YMM10,%YMM13,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x5,%YMM16,%YMM13,%K1{%K1}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KORTESTB %K1,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JE 451fb0 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x4c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x88(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 451fb0 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x4c0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	viscosity_kernel.f90:53-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

84% of SSE/AVX loads are used in vector version.
88% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 49.00 to 25.00 cycles (1.96x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Vector unaligned load/store instructions

Detected 13 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 13 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:89
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:53
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:60
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:65
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:66

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

58 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 220 FP arithmetical operations:

88: addition or subtraction (20 inside FMA instructions)
108: multiply (20 inside FMA instructions)
20: divide
4: square root

The binary loop is loading 552 bytes (69 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.38 FP operations per loaded or stored byte.

General properties

nb instructions	106
nb uops	106
loop length	643
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	31
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.17 cycles
front end	18.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	22.67	22.67	7.00	7.00	0.50	22.67	2.00	0.50	0.50	0.50	2.00	7.00
cycles	22.67	22.67	7.00	7.00	0.50	22.67	2.00	0.50	0.50	0.50	2.00	7.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	49.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	18.17
Dispatch	22.67
DIV/SQRT	49.00
Data deps.	4.00
Overall L1	49.00

Vectorization ratios

INT

all	88%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	87%

all	96%
load	83%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	95%
load	84%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

Vector efficiency ratios

INT

all	45%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	45%

all	48%
load	43%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	44%

INT+FP

all	48%
load	44%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	45%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 49.00 cycles. At this rate:

5% of peak load performance is reached (11.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4520d7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCMPPD $0x1,%YMM13,%YMM18,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD 0xaffa0(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBLENDMPD %YMM7,%YMM20,%YMM4{%K2}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VBROADCASTSD 0x930e0(%RIP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VANDPD %YMM19,%YMM18,%YMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMAXPD %YMM1,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM5,%YMM4,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM13,%YMM5,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBLENDMPD %YMM7,%YMM20,%YMM7{%K2}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM19,%YMM17,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMAXPD %YMM1,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM5,%YMM5,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM10,%YMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMULPD %YMM21,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM5,%YMM15,%YMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VANDPD %YMM19,%YMM5,%YMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMULPD %YMM26,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM15,%YMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VANDPD %YMM19,%YMM8,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMINPD %YMM8,%YMM5,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM15,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM16,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM17,%YMM17,%YMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM18,%YMM16,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD 0x158(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMOVUPD (%RDI,%R12,8),%YMM18{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPBROADCASTQ %R12,%YMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ 0x931f8(%RIP),%YMM19,%YMM19	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VMOVDQA64 %YMM19,%YMM0{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM4,%YMM31{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM7,%YMM29{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM9{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM10,%YMM27{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM6{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM5,%YMM25{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM3{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM8,%YMM24{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM15,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVDQA64 %YMM19,%YMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM17,%YMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMULPD %YMM18,%YMM16,%YMM4{%K1}{z}	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM4,(%R10,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x4,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x20(%RSP),%R12	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JAE 452250 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x760>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD -0x8(%RAX,%R12,8),%YMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RAX,%R12,8),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD -0x8(%RCX,%R12,8),%YMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RCX,%R12,8),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM17,%YMM19,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM18,%YMM16,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM21,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x8(%R9,%R12,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM20,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD (%R9,%R12,8),%YMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD -0x8(%R15,%R12,8),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R15,%R12,8),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM7,%YMM20,%YMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM4,%YMM15,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x8(%R11,%R12,8),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM10,%YMM8,%YMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM5,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM26,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM16,%YMM17,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM16,%YMM19,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM18,%YMM16,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x93dc0(%RIP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM19,%YMM16,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM7,%YMM15,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM7,%YMM20,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM13,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDPD %YMM4,%YMM7,%YMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM19,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM21,%YMM20,%YMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM7,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM16,%YMM28,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD (%RSI,%R12,8),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD -0x10(%RSI,%R12,8),%YMM15,%YMM15	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VADDPD (%R11,%R12,8),%YMM21,%YMM16	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVUPD (%R14,%R12,8),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD (%RDX,%R12,8),%YMM17,%YMM17	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VDIVPD %YMM16,%YMM15,%YMM18	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM30,%YMM17,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM18,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM17,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM5,%YMM15,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM8,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM18,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM5,%YMM17,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM7,%YMM28,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM15,%YMM16,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMAXPD %YMM1,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM5,%YMM4,%YMM16	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VCMPPD $0x6,%YMM10,%YMM13,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x5,%YMM16,%YMM13,%K1{%K1}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KORTESTB %K1,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JE 451fb0 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x4c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks