OV - exec - Loop 81

0x4164f0 VMOVUPD	(%RSI,%R12,8),%YMM0    [6]

0x4164f6 VMULPD	(%R13,%R12,8),%YMM0,%YMM1    [1]

0x4164fd VADDPD	(%R9,%R12,8),%YMM1,%YMM2    [5]

0x416503 VSUBPD	(%R10,%R12,8),%YMM2,%YMM2    [7]

0x416509 VMOVUPD	(%R15,%R12,8),%YMM3    [2]

0x41650f VFMADD213PD	(%RCX,%R12,8),%YMM1,%YMM3    [3]

0x416515 VSUBPD	(%R8,%R12,8),%YMM3,%YMM1    [4]

0x41651b VDIVPD	%YMM2,%YMM1,%YMM1

0x41651f VADDPD	(%R14,%R12,8),%YMM0,%YMM0    [8]

0x416525 VSUBPD	(%RBX,%R12,8),%YMM0,%YMM0    [9]

0x41652b VDIVPD	%YMM0,%YMM2,%YMM0

0x41652f VMOVUPD	%YMM0,(%R13,%R12,8)    [1]

0x416536 VMOVUPD	%YMM1,(%R15,%R12,8)    [2]

0x41653c ADD	$0x4,%R12

0x416540 CMP	%RDI,%R12

0x416543 JB	4164f0

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 255 - 261

--------------------------------------------------------------------------------

255:         DO j=x_min,x_max

256:           pre_mass_s=density1(j,k)*pre_vol(j,k)

257:           post_mass_s=pre_mass_s+mass_flux_y(j,k)-mass_flux_y(j,k+1)

258:           post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j,k+1))/post_mass_s

259:           advec_vol_s=pre_vol(j,k)+vol_flux_y(j,k)-vol_flux_y(j,k+1)

260:           density1(j,k)=post_mass_s/advec_vol_s

261:           energy1(j,k)=post_ener_s

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.36
Bottlenecks	P0,
Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source	advec_cell_kernel.f90:255-261
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	3.67
P0 cycles	2.50
P1 cycles	3.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	1.00
P5 cycles	3.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	3.00
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	15.00
Nb loads	9.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.00
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.36
Bottlenecks	P0,
Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source	advec_cell_kernel.f90:255-261
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	3.67
P0 cycles	2.50
P1 cycles	3.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	1.00
P5 cycles	3.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	3.00
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	15.00
Nb loads	9.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.00
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	advec_cell_kernel.f90:255-261
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:255-261.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.00 to 3.67 cycles (4.36x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 4.50 cycles (3.56x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:256
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:258
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:260
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:261

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

9 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes (36 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	16
nb uops	15
loop length	85
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	3.50	3.00	3.00	1.00	3.00	1.00	1.00	1.00	1.00	0.00	3.00
cycles	2.50	3.50	3.00	3.00	1.00	3.00	1.00	1.00	1.00	1.00	0.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.67
Dispatch	3.50
DIV/SQRT	16.00
Data deps.	1.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

9% of peak load performance is reached (18.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4164f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RSI,%R12,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD (%R13,%R12,8),%YMM0,%YMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD (%R9,%R12,8),%YMM1,%YMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VSUBPD (%R10,%R12,8),%YMM2,%YMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVUPD (%R15,%R12,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%RCX,%R12,8),%YMM1,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VSUBPD (%R8,%R12,8),%YMM3,%YMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VDIVPD %YMM2,%YMM1,%YMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VADDPD (%R14,%R12,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VSUBPD (%RBX,%R12,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VDIVPD %YMM0,%YMM2,%YMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMOVUPD %YMM0,(%R13,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM1,(%R15,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x4,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 4164f0 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x9f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	advec_cell_kernel.f90:255-261
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:255-261.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.00 to 3.67 cycles (4.36x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 4.50 cycles (3.56x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:256
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:258
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:260
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:261

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

9 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes (36 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	16
nb uops	15
loop length	85
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	3.50	3.00	3.00	1.00	3.00	1.00	1.00	1.00	1.00	0.00	3.00
cycles	2.50	3.50	3.00	3.00	1.00	3.00	1.00	1.00	1.00	1.00	0.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.67
Dispatch	3.50
DIV/SQRT	16.00
Data deps.	1.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

9% of peak load performance is reached (18.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4164f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RSI,%R12,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD (%R13,%R12,8),%YMM0,%YMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD (%R9,%R12,8),%YMM1,%YMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VSUBPD (%R10,%R12,8),%YMM2,%YMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVUPD (%R15,%R12,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%RCX,%R12,8),%YMM1,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VSUBPD (%R8,%R12,8),%YMM3,%YMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VDIVPD %YMM2,%YMM1,%YMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VADDPD (%R14,%R12,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VSUBPD (%RBX,%R12,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VDIVPD %YMM0,%YMM2,%YMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMOVUPD %YMM0,(%R13,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM1,(%R15,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x4,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 4164f0 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x9f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code