| Loop Id: 67 | Module: exec | Source: accelerate_kernel.f90:62-76 | Coverage: 5.40% |
|---|
| Loop Id: 67 | Module: exec | Source: accelerate_kernel.f90:62-76 | Coverage: 5.40% |
|---|
0x415110 VMOVUPD -0x8(%RDI,%RCX,8),%YMM5 [9] |
0x415116 VMOVUPD (%RDI,%RCX,8),%YMM6 [9] |
0x41511b VMULPD -0x8(%R14,%RCX,8),%YMM5,%YMM5 [8] |
0x415122 VFMADD231PD (%R14,%RCX,8),%YMM6,%YMM5 [8] |
0x415128 VMOVUPD -0x8(%R10,%RCX,8),%YMM6 [4] |
0x41512f VMOVUPD (%R10,%RCX,8),%YMM7 [4] |
0x415135 VFMADD132PD (%RSI,%RCX,8),%YMM5,%YMM7 [15] |
0x41513b VFMADD231PD -0x8(%RSI,%RCX,8),%YMM6,%YMM7 [15] |
0x415142 VMULPD %YMM4,%YMM7,%YMM5 |
0x415146 VDIVPD %YMM5,%YMM0,%YMM5 |
0x41514a VMOVUPD (%R12,%RCX,8),%YMM6 [6] |
0x415150 MOV -0x60(%RBP),%R15 [5] |
0x415154 VMOVUPD -0x8(%R15,%RCX,8),%YMM7 [12] |
0x41515b VMOVUPD (%R15,%RCX,8),%YMM8 [12] |
0x415161 VSUBPD %YMM8,%YMM7,%YMM9 |
0x415166 VMULPD %YMM6,%YMM9,%YMM9 |
0x41516a VMOVUPD (%R9,%RCX,8),%YMM10 [3] |
0x415170 VMOVUPD -0x8(%RAX,%RCX,8),%YMM11 [13] |
0x415176 VMOVUPD (%RAX,%RCX,8),%YMM12 [13] |
0x41517b VSUBPD %YMM12,%YMM11,%YMM13 |
0x415180 VFMADD213PD %YMM9,%YMM10,%YMM13 |
0x415185 MOV -0x30(%RBP),%R15 [5] |
0x415189 VMOVUPD -0x8(%R15,%RCX,8),%YMM9 [11] |
0x415190 VMOVUPD (%R15,%RCX,8),%YMM14 [11] |
0x415196 VSUBPD %YMM8,%YMM12,%YMM8 |
0x41519b VMULPD %YMM8,%YMM14,%YMM8 |
0x4151a0 VSUBPD %YMM7,%YMM11,%YMM7 |
0x4151a4 VFMADD213PD %YMM8,%YMM9,%YMM7 |
0x4151a9 MOV -0x50(%RBP),%R15 [5] |
0x4151ad VMOVUPD -0x8(%R15,%RCX,8),%YMM8 [10] |
0x4151b4 VMOVUPD (%R15,%RCX,8),%YMM11 [10] |
0x4151ba VMOVUPD -0x8(%RBX,%RCX,8),%YMM12 [14] |
0x4151c0 VMOVUPD (%RBX,%RCX,8),%YMM15 [14] |
0x4151c5 VSUBPD %YMM11,%YMM8,%YMM16 |
0x4151cb VSUBPD %YMM15,%YMM12,%YMM17 |
0x4151d1 VFMADD213PD %YMM13,%YMM6,%YMM16 |
0x4151d7 VFMADD231PD %YMM17,%YMM10,%YMM16 |
0x4151dd VFMADD213PD (%R13,%RCX,8),%YMM5,%YMM16 [7] |
0x4151e5 VMOVUPD %YMM16,(%R11,%RCX,8) [2] |
0x4151ec VSUBPD %YMM11,%YMM15,%YMM6 |
0x4151f1 VSUBPD %YMM8,%YMM12,%YMM8 |
0x4151f6 VFMADD213PD %YMM7,%YMM14,%YMM6 |
0x4151fb VFMADD231PD %YMM8,%YMM9,%YMM6 |
0x415200 VFMADD213PD (%RDX,%RCX,8),%YMM5,%YMM6 [16] |
0x415206 VMOVUPD %YMM6,(%R8,%RCX,8) [1] |
0x41520c ADD $0x4,%RCX |
0x415210 CMP -0x68(%RBP),%RCX [5] |
0x415214 JB 415110 |
/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 62 - 76 |
-------------------------------------------------------------------------------- |
62: DO j=x_min,x_max+1 |
63: stepbymass_s=halfdt/((density0(j-1,k-1)*volume(j-1,k-1) & |
64: +density0(j ,k-1)*volume(j ,k-1) & |
65: +density0(j ,k )*volume(j ,k ) & |
66: +density0(j-1,k )*volume(j-1,k )) & |
67: *0.25_8) |
68: |
69: xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j ,k )*(pressure(j ,k )-pressure(j-1,k )) & |
70: +xarea(j ,k-1)*(pressure(j ,k-1)-pressure(j-1,k-1))) |
71: yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j ,k )*(pressure(j ,k )-pressure(j ,k-1)) & |
72: +yarea(j-1,k )*(pressure(j-1,k )-pressure(j-1,k-1))) |
73: xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j ,k )*(viscosity(j ,k )-viscosity(j-1,k )) & |
74: +xarea(j ,k-1)*(viscosity(j ,k-1)-viscosity(j-1,k-1))) |
75: yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j ,k )*(viscosity(j ,k )-viscosity(j ,k-1)) & |
76: +yarea(j-1,k )*(viscosity(j-1,k )-viscosity(j-1,k-1))) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►99.96+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_invoke_task_func | libiomp5.so |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.44 |
| CQA speedup if fully vectorized | 1.44 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.30 |
| Bottlenecks | P1, |
| Function | accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2 |
| Source | accelerate_kernel.f90:62-76 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 11.50 |
| CQA cycles if no scalar integer | 11.50 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 8.00 |
| Front-end cycles | 8.83 |
| P0 cycles | 8.50 |
| P1 cycles | 11.50 |
| P2 cycles | 8.67 |
| P3 cycles | 8.67 |
| P4 cycles | 1.00 |
| P5 cycles | 7.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 0.00 |
| P11 cycles | 8.67 |
| DIV/SQRT cycles | 8.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 48.00 |
| Nb uops | 47.00 |
| Nb loads | 26.00 |
| Nb stores | 2.00 |
| Nb stack references | 4.00 |
| FLOP/cycle | 12.17 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 16.00 |
| Nb FLOP fma | 44.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 69.57 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 736.00 |
| Bytes stored | 64.00 |
| Stride 0 | 1.00 |
| Stride 1 | 6.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | 50.00 |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.44 |
| CQA speedup if fully vectorized | 1.44 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.30 |
| Bottlenecks | P1, |
| Function | accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2 |
| Source | accelerate_kernel.f90:62-76 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 11.50 |
| CQA cycles if no scalar integer | 11.50 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 8.00 |
| Front-end cycles | 8.83 |
| P0 cycles | 8.50 |
| P1 cycles | 11.50 |
| P2 cycles | 8.67 |
| P3 cycles | 8.67 |
| P4 cycles | 1.00 |
| P5 cycles | 7.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 0.00 |
| P11 cycles | 8.67 |
| DIV/SQRT cycles | 8.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 48.00 |
| Nb uops | 47.00 |
| Nb loads | 26.00 |
| Nb stores | 2.00 |
| Nb stack references | 4.00 |
| FLOP/cycle | 12.17 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 16.00 |
| Nb FLOP fma | 44.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 69.57 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 736.00 |
| Bytes stored | 64.00 |
| Stride 0 | 1.00 |
| Stride 1 | 6.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | 50.00 |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | accelerate_kernel.f90:62-76 |
| Module | exec |
 |
 |
| nb instructions | 48 |
| nb uops | 47 |
| loop length | 266 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 15 |
| used zmm registers | 0 |
| nb stack references | 4 |
| ADD-SUB / MUL ratio | 2.00 |
| micro-operation queue | 8.83 cycles |
| front end | 8.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.50 | 8.50 | 8.67 | 8.67 | 1.00 | 7.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 8.67 |
| cycles | 8.50 | 11.50 | 8.67 | 8.67 | 1.00 | 7.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 8.67 |
| Cycles executing div or sqrt instructions | 8.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 8.83 |
| Dispatch | 11.50 |
| DIV/SQRT | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 11.50 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | 50% |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | 50% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD -0x8(%RDI,%RCX,8),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%RDI,%RCX,8),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMULPD -0x8(%R14,%RCX,8),%YMM5,%YMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VFMADD231PD (%R14,%RCX,8),%YMM6,%YMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VMOVUPD -0x8(%R10,%RCX,8),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%R10,%RCX,8),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VFMADD132PD (%RSI,%RCX,8),%YMM5,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VFMADD231PD -0x8(%RSI,%RCX,8),%YMM6,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VMULPD %YMM4,%YMM7,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VDIVPD %YMM5,%YMM0,%YMM5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 | vect (50.0%) |
| VMOVUPD (%R12,%RCX,8),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| MOV -0x60(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVUPD -0x8(%R15,%RCX,8),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%R15,%RCX,8),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VSUBPD %YMM8,%YMM7,%YMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VMULPD %YMM6,%YMM9,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VMOVUPD (%R9,%RCX,8),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD -0x8(%RAX,%RCX,8),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%RAX,%RCX,8),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VSUBPD %YMM12,%YMM11,%YMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VFMADD213PD %YMM9,%YMM10,%YMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| MOV -0x30(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVUPD -0x8(%R15,%RCX,8),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%R15,%RCX,8),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VSUBPD %YMM8,%YMM12,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VMULPD %YMM8,%YMM14,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VSUBPD %YMM7,%YMM11,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VFMADD213PD %YMM8,%YMM9,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| MOV -0x50(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVUPD -0x8(%R15,%RCX,8),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%R15,%RCX,8),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD -0x8(%RBX,%RCX,8),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%RBX,%RCX,8),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VSUBPD %YMM11,%YMM8,%YMM16 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VSUBPD %YMM15,%YMM12,%YMM17 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VFMADD213PD %YMM13,%YMM6,%YMM16 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD231PD %YMM17,%YMM10,%YMM16 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PD (%R13,%RCX,8),%YMM5,%YMM16 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VMOVUPD %YMM16,(%R11,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| VSUBPD %YMM11,%YMM15,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VSUBPD %YMM8,%YMM12,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VFMADD213PD %YMM7,%YMM14,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD231PD %YMM8,%YMM9,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PD (%RDX,%RCX,8),%YMM5,%YMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VMOVUPD %YMM6,(%R8,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| ADD $0x4,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP -0x68(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| JB 415110 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x8d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| Function | accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | accelerate_kernel.f90:62-76 |
| Module | exec |
|
|
| nb instructions | 48 |
| nb uops | 47 |
| loop length | 266 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 15 |
| used zmm registers | 0 |
| nb stack references | 4 |
| ADD-SUB / MUL ratio | 2.00 |
| micro-operation queue | 8.83 cycles |
| front end | 8.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.50 | 8.50 | 8.67 | 8.67 | 1.00 | 7.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 8.67 |
| cycles | 8.50 | 11.50 | 8.67 | 8.67 | 1.00 | 7.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 8.67 |
| Cycles executing div or sqrt instructions | 8.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 8.83 |
| Dispatch | 11.50 |
| DIV/SQRT | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 11.50 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | 50% |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | 50% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD -0x8(%RDI,%RCX,8),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%RDI,%RCX,8),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMULPD -0x8(%R14,%RCX,8),%YMM5,%YMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VFMADD231PD (%R14,%RCX,8),%YMM6,%YMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VMOVUPD -0x8(%R10,%RCX,8),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%R10,%RCX,8),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VFMADD132PD (%RSI,%RCX,8),%YMM5,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VFMADD231PD -0x8(%RSI,%RCX,8),%YMM6,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VMULPD %YMM4,%YMM7,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VDIVPD %YMM5,%YMM0,%YMM5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 | vect (50.0%) |
| VMOVUPD (%R12,%RCX,8),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| MOV -0x60(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVUPD -0x8(%R15,%RCX,8),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%R15,%RCX,8),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VSUBPD %YMM8,%YMM7,%YMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VMULPD %YMM6,%YMM9,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VMOVUPD (%R9,%RCX,8),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD -0x8(%RAX,%RCX,8),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%RAX,%RCX,8),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VSUBPD %YMM12,%YMM11,%YMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VFMADD213PD %YMM9,%YMM10,%YMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| MOV -0x30(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVUPD -0x8(%R15,%RCX,8),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%R15,%RCX,8),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VSUBPD %YMM8,%YMM12,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VMULPD %YMM8,%YMM14,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VSUBPD %YMM7,%YMM11,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VFMADD213PD %YMM8,%YMM9,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| MOV -0x50(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVUPD -0x8(%R15,%RCX,8),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%R15,%RCX,8),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD -0x8(%RBX,%RCX,8),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVUPD (%RBX,%RCX,8),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VSUBPD %YMM11,%YMM8,%YMM16 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VSUBPD %YMM15,%YMM12,%YMM17 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VFMADD213PD %YMM13,%YMM6,%YMM16 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD231PD %YMM17,%YMM10,%YMM16 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PD (%R13,%RCX,8),%YMM5,%YMM16 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VMOVUPD %YMM16,(%R11,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| VSUBPD %YMM11,%YMM15,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VSUBPD %YMM8,%YMM12,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
| VFMADD213PD %YMM7,%YMM14,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD231PD %YMM8,%YMM9,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PD (%RDX,%RCX,8),%YMM5,%YMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
| VMOVUPD %YMM6,(%R8,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| ADD $0x4,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP -0x68(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| JB 415110 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x8d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |