OV - exec - Loop 202

	Loop Id: 202	Module: exec	Source: field_summary_kernel.f90:58-71	Coverage: 0.16%

0x424b70 VPCMPEQB	%XMM0,%XMM0,%K1

0x424b76 VMOVDQA64	%YMM19,%YMM22

0x424b7c VXORPD	%XMM21,%XMM21,%XMM21

0x424b82 NOPW	%CS:(%RAX,%RAX,1)

  (200) 0x424b90 VMOVQ	%XMM22,%R8

  (200) 0x424b96 VPSUBQ	%YMM12,%YMM22,%YMM22

  (200) 0x424b9c SUB	%R9,%R8

  (200) 0x424b9f VMOVUPD	(%RDX,%R8,8),%YMM23{%K1}{z}

  (200) 0x424ba6 VMOVUPD	(%RCX,%R8,8),%YMM24{%K1}{z}

  (200) 0x424bad VMULPD	%YMM24,%YMM24,%YMM24

  (200) 0x424bb3 VFMADD231PD	%YMM23,%YMM23,%YMM24

  (200) 0x424bb9 VFMADD231PD	%YMM9,%YMM24,%YMM21

  (200) 0x424bbf VMOVAPD	%YMM21,%YMM20{%K1}

  (200) 0x424bc5 VPCMPNEQQ	%YMM18,%YMM22,%K1{%K1}

  (200) 0x424bcc KORTESTB	%K1,%K1

  (200) 0x424bd0 JNE	424b90

0x424bd2 VPCMPEQB	%XMM0,%XMM0,%K1

0x424bd8 VMOVDQA64	%YMM19,%YMM22

0x424bde XCHG	%AX,%AX

  (201) 0x424be0 VMOVQ	%XMM22,%R8

  (201) 0x424be6 VPSUBQ	%YMM12,%YMM22,%YMM22

  (201) 0x424bec SUB	%R9,%R8

  (201) 0x424bef VMOVUPD	(%RAX,%R8,8),%YMM23{%K1}{z}

  (201) 0x424bf6 VMOVUPD	(%RSI,%R8,8),%YMM24{%K1}{z}

  (201) 0x424bfd VMULPD	%YMM24,%YMM24,%YMM24

  (201) 0x424c03 VFMADD231PD	%YMM23,%YMM23,%YMM24

  (201) 0x424c09 VFMADD231PD	%YMM9,%YMM24,%YMM20

  (201) 0x424c0f VMOVAPD	%YMM20,%YMM21{%K1}

  (201) 0x424c15 VPCMPNEQQ	%YMM18,%YMM22,%K1{%K1}

  (201) 0x424c1c KORTESTB	%K1,%K1

  (201) 0x424c20 JNE	424be0

0x424c22 MOV	-0x48(%RBP),%R8

0x424c26 ADD	%RDI,%R8

0x424c29 SUB	%R9,%R8

0x424c2c MOV	-0xd0(%RBP),%RBX

0x424c33 VMOVUPD	(%RBX,%R8,8),%YMM20

0x424c3a MOV	-0xc8(%RBP),%RBX

0x424c41 VMULPD	(%RBX,%R8,8),%YMM20,%YMM22

0x424c48 VADDPD	%YMM20,%YMM13,%YMM13

0x424c4e VADDPD	%YMM22,%YMM14,%YMM14

0x424c54 MOV	-0xc0(%RBP),%RBX

0x424c5b VFMADD231PD	(%RBX,%R8,8),%YMM22,%YMM15

0x424c62 VMULPD	%YMM10,%YMM22,%YMM22

0x424c68 VFMADD231PD	%YMM21,%YMM22,%YMM17

0x424c6e MOV	-0xb8(%RBP),%RBX

0x424c75 VFMADD231PD	(%RBX,%R8,8),%YMM20,%YMM16

0x424c7c ADD	$0x4,%RDI

0x424c80 VPADDQ	%YMM11,%YMM19,%YMM19

0x424c86 VPADDQ	%YMM11,%YMM18,%YMM18

0x424c8c CMP	%R11,%RDI

0x424c8f JB	424b70

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 58 - 71

--------------------------------------------------------------------------------

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.21
CQA speedup if FP arith vectorized	1.61
CQA speedup if fully vectorized	2.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	micro-operation queue,
Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source	field_summary_kernel.f90:58-58,field_summary_kernel.f90:62-62,field_summary_kernel.f90:65-71
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.83
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	1.75
Front-end cycles	4.83
P0 cycles	3.83
P1 cycles	3.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	0.00
P5 cycles	3.67
P6 cycles	1.60
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.40
P11 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	9.00
Nb stores	0.00
Nb stack references	5.00
FLOP/cycle	8.28
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.76
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	45.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	35.00

Metric	Value
CQA speedup if no scalar integer	1.21
CQA speedup if FP arith vectorized	1.61
CQA speedup if fully vectorized	2.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	micro-operation queue,
Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source	field_summary_kernel.f90:58-58,field_summary_kernel.f90:62-62,field_summary_kernel.f90:65-71
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.83
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	1.75
Front-end cycles	4.83
P0 cycles	3.83
P1 cycles	3.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	0.00
P5 cycles	3.67
P6 cycles	1.60
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.40
P11 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	9.00
Nb stores	0.00
Nb stack references	5.00
FLOP/cycle	8.28
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.76
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	45.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	35.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	field_summary_kernel.f90:58-71
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:58-71.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:58,62,65-71.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.83 to 4.00 cycles (1.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is vectorized, but using 45% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:65

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

7 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (12 inside FMA instructions)
20: multiply (12 inside FMA instructions)

The binary loop is loading 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	26
loop length	161
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	12
used zmm registers	0
nb stack references	5
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.83	3.50	3.00	3.00	0.00	3.67	1.60	0.00	0.00	0.00	1.40	3.00
cycles	3.83	3.50	3.00	3.00	0.00	3.67	1.60	0.00	0.00	0.00	1.40	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	4.83
Dispatch	3.83
Data deps.	4.00
Overall L1	4.83

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	41%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	47%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	45%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.83 cycles. At this rate:

18% of peak load performance is reached (34.76 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.83 to 3.83 cycles (1.26x speedup).

ASM code

In the binary file, the address of the loop is: 424b70

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VPCMPEQB %XMM0,%XMM0,%K1	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VMOVDQA64 %YMM19,%YMM22	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQB %XMM0,%XMM0,%K1	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VMOVDQA64 %YMM19,%YMM22	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
SUB %R9,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0xd0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RBX,%R8,8),%YMM20	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV -0xc8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMULPD (%RBX,%R8,8),%YMM20,%YMM22	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD %YMM20,%YMM13,%YMM13	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM22,%YMM14,%YMM14	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
MOV -0xc0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231PD (%RBX,%R8,8),%YMM22,%YMM15	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM22,%YMM22	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM22,%YMM17	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
MOV -0xb8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231PD (%RBX,%R8,8),%YMM20,%YMM16	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VPADDQ %YMM11,%YMM19,%YMM19	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM11,%YMM18,%YMM18	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
CMP %R11,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 424b70 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x400>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	field_summary_kernel.f90:58-71
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.83 to 4.00 cycles (1.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is vectorized, but using 45% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:65

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

7 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (12 inside FMA instructions)
20: multiply (12 inside FMA instructions)

The binary loop is loading 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	26
loop length	161
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	12
used zmm registers	0
nb stack references	5
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.83	3.50	3.00	3.00	0.00	3.67	1.60	0.00	0.00	0.00	1.40	3.00
cycles	3.83	3.50	3.00	3.00	0.00	3.67	1.60	0.00	0.00	0.00	1.40	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	4.83
Dispatch	3.83
Data deps.	4.00
Overall L1	4.83

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	41%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	47%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	45%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.83 cycles. At this rate:

18% of peak load performance is reached (34.76 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 424b70

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VPCMPEQB %XMM0,%XMM0,%K1	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VMOVDQA64 %YMM19,%YMM22	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQB %XMM0,%XMM0,%K1	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VMOVDQA64 %YMM19,%YMM22	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
SUB %R9,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0xd0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RBX,%R8,8),%YMM20	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV -0xc8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMULPD (%RBX,%R8,8),%YMM20,%YMM22	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD %YMM20,%YMM13,%YMM13	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM22,%YMM14,%YMM14	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
MOV -0xc0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231PD (%RBX,%R8,8),%YMM22,%YMM15	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM22,%YMM22	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM22,%YMM17	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
MOV -0xb8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231PD (%RBX,%R8,8),%YMM20,%YMM16	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VPADDQ %YMM11,%YMM19,%YMM19	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM11,%YMM18,%YMM18	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
CMP %R11,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 424b70 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x400>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code