OV - exec - Loop 193

	Loop Id: 193	Module: exec	Source: calc_dt_kernel.f90:94-129	Coverage: 3.27%

0x423270 MOV	-0x1b8(%RBP),%RBX    [8]

0x423277 VMOVUPD	(%RBX,%R10,8),%YMM4    [4]

0x42327d VMOVUPD	0x20(%RBX,%R10,8),%YMM6    [4]

0x423284 VMOVUPD	(%R12,%R10,8),%YMM7    [3]

0x42328a VMOVUPD	0x20(%R12,%R10,8),%YMM8    [3]

0x423291 VMOVUPD	(%R9,%R10,8),%YMM9    [15]

0x423297 VMOVUPD	0x20(%R9,%R10,8),%YMM5    [15]

0x42329e VADDPD	%YMM9,%YMM9,%YMM9

0x4232a3 VADDPD	%YMM5,%YMM5,%YMM5

0x4232a7 VDIVPD	0x20(%RAX,%R10,8),%YMM5,%YMM5    [1]

0x4232ae VDIVPD	(%RAX,%R10,8),%YMM9,%YMM9    [1]

0x4232b4 VFMADD231PD	%YMM7,%YMM7,%YMM9

0x4232b9 VFMADD231PD	%YMM8,%YMM8,%YMM5

0x4232be VSQRTPD	%YMM5,%YMM5

0x4232c2 VSQRTPD	%YMM9,%YMM7

0x4232c7 VMAXPD	%YMM11,%YMM7,%YMM7

0x4232cc VMAXPD	%YMM11,%YMM5,%YMM5

0x4232d1 VMINPD	%YMM12,%YMM6,%YMM6

0x4232d6 VMINPD	%YMM12,%YMM4,%YMM4

0x4232db VMULPD	%YMM4,%YMM13,%YMM4

0x4232df VDIVPD	%YMM7,%YMM4,%YMM4

0x4232e3 VMULPD	%YMM6,%YMM13,%YMM6

0x4232e7 VDIVPD	%YMM5,%YMM6,%YMM5

0x4232eb VMULPD	%YMM14,%YMM31,%YMM6

0x4232f1 VMULPD	%YMM14,%YMM18,%YMM7

0x4232f7 VANDPD	%YMM2,%YMM24,%YMM8

0x4232fd VANDPD	%YMM2,%YMM20,%YMM9

0x423303 VANDPD	%YMM2,%YMM28,%YMM20

0x423309 VANDPD	%YMM2,%YMM25,%YMM24

0x42330f VMULPD	%YMM11,%YMM26,%YMM25

0x423315 VMULPD	%YMM11,%YMM27,%YMM26

0x42331b VMAXPD	%YMM26,%YMM24,%YMM24

0x423321 VMAXPD	%YMM24,%YMM8,%YMM8

0x423327 VDIVPD	%YMM8,%YMM7,%YMM7

0x42332c VMAXPD	%YMM25,%YMM20,%YMM8

0x423332 VMAXPD	%YMM8,%YMM9,%YMM8

0x423337 VDIVPD	%YMM8,%YMM6,%YMM6

0x42333c VMULPD	%YMM15,%YMM31,%YMM8

0x423342 VMULPD	%YMM15,%YMM18,%YMM9

0x423348 VANDPD	%YMM2,%YMM21,%YMM18

0x42334e VANDPD	%YMM2,%YMM22,%YMM20

0x423354 VANDPD	%YMM2,%YMM30,%YMM21

0x42335a VANDPD	%YMM2,%YMM29,%YMM22

0x423360 VMAXPD	%YMM26,%YMM22,%YMM22

0x423366 VMAXPD	%YMM22,%YMM18,%YMM18

0x42336c VDIVPD	%YMM18,%YMM9,%YMM9

0x423372 VMAXPD	%YMM25,%YMM21,%YMM18

0x423378 VMAXPD	%YMM18,%YMM20,%YMM18

0x42337e VDIVPD	%YMM18,%YMM8,%YMM8

0x423384 VBROADCASTSD	%XMM3,%YMM3

0x423389 VXORPD	0xc3015(%RIP){1to4},%YMM3,%YMM3    [13]

0x423393 VBROADCASTSD	%XMM0,%YMM0

0x423398 VMOVAPD	%YMM0,%YMM18

0x42339e VDIVPD	%YMM23,%YMM3,%YMM18{%K2}

0x4233a4 VMINPD	%YMM18,%YMM9,%YMM9

0x4233aa VMINPD	%YMM9,%YMM7,%YMM7

0x4233af VMINPD	%YMM7,%YMM5,%YMM5

0x4233b3 VMINPD	%YMM5,%YMM17,%YMM17

0x4233b9 VDIVPD	%YMM19,%YMM3,%YMM0{%K1}

0x4233bf VMINPD	%YMM0,%YMM8,%YMM0

0x4233c3 VMINPD	%YMM0,%YMM6,%YMM0

0x4233c7 VMINPD	%YMM0,%YMM4,%YMM0

0x4233cb VMINPD	%YMM0,%YMM10,%YMM10

0x4233cf ADD	$0x8,%R10

0x4233d3 CMP	%RSI,%R10

0x4233d6 JAE	423530

0x4233dc VMOVUPD	-0x8(%RDX,%R10,8),%YMM0    [10]

0x4233e3 VMOVUPD	(%RDX,%R10,8),%YMM3    [10]

0x4233e9 VMOVUPD	0x18(%RDX,%R10,8),%YMM18    [10]

0x4233f4 VMOVUPD	0x20(%RDX,%R10,8),%YMM19    [10]

0x4233fc VADDPD	0x18(%RDI,%R10,8),%YMM18,%YMM18    [12]

0x423407 VADDPD	-0x8(%RDI,%R10,8),%YMM0,%YMM0    [12]

0x42340e VMULPD	-0x8(%RCX,%R10,8),%YMM0,%YMM20    [2]

0x423419 VMULPD	0x18(%RCX,%R10,8),%YMM18,%YMM24    [2]

0x423424 VADDPD	(%RDI,%R10,8),%YMM3,%YMM0    [12]

0x42342a VADDPD	0x20(%RDI,%R10,8),%YMM19,%YMM3    [12]

0x423432 VMULPD	0x20(%RCX,%R10,8),%YMM3,%YMM25    [2]

0x42343a VMULPD	(%RCX,%R10,8),%YMM0,%YMM28    [2]

0x423441 VMOVUPD	(%R14,%R10,8),%YMM26    [11]

0x423448 VMOVUPD	0x20(%R14,%R10,8),%YMM27    [11]

0x423450 VADDPD	%YMM27,%YMM27,%YMM18

0x423456 VMOVUPD	(%R11,%R10,8),%YMM0    [6]

0x42345c VMOVUPD	0x20(%R11,%R10,8),%YMM3    [6]

0x423463 VADDPD	-0x8(%R11,%R10,8),%YMM0,%YMM0    [6]

0x42346a VADDPD	0x18(%R11,%R10,8),%YMM3,%YMM3    [6]

0x423471 VMULPD	0x20(%R15,%R10,8),%YMM3,%YMM21    [14]

0x423479 VMULPD	(%R15,%R10,8),%YMM0,%YMM22    [14]

0x423480 VMOVUPD	(%R8,%R10,8),%YMM0    [7]

0x423486 VMOVUPD	0x20(%R8,%R10,8),%YMM3    [7]

0x42348d VADDPD	-0x8(%R8,%R10,8),%YMM0,%YMM0    [7]

0x423494 VADDPD	0x18(%R8,%R10,8),%YMM3,%YMM3    [7]

0x42349b VADDPD	%YMM26,%YMM26,%YMM31

0x4234a1 VMULPD	0x20(%R13,%R10,8),%YMM3,%YMM29    [9]

0x4234a9 VMULPD	(%R13,%R10,8),%YMM0,%YMM30    [9]

0x4234b1 VADDPD	%YMM22,%YMM20,%YMM0

0x4234b7 VADDPD	%YMM21,%YMM24,%YMM3

0x4234bd VSUBPD	%YMM3,%YMM25,%YMM3

0x4234c3 VSUBPD	%YMM0,%YMM28,%YMM0

0x4234c9 VADDPD	%YMM30,%YMM0,%YMM0

0x4234cf VADDPD	%YMM29,%YMM3,%YMM3

0x4234d5 VDIVPD	%YMM18,%YMM3,%YMM23

0x4234db VDIVPD	%YMM31,%YMM0,%YMM19

0x4234e1 VCMPPD	$0x1,%YMM16,%YMM19,%K1

0x4234e8 VCMPPD	$0x1,%YMM16,%YMM23,%K2

0x4234ef KSHIFTLB	$0x4,%K2,%K0

0x4234f5 KORB	%K0,%K1,%K0

0x4234f9 KORTESTB	%K0,%K0

0x4234fd JB	42350a

0x4234ff MOV	0x88(%RBP),%RBX    [8]

0x423506 VMOVSD	(%RBX),%XMM0    [16]

0x42350a KORTESTB	%K2,%K1

0x42350e JE	423270

0x423514 MOV	0x68(%RBP),%RBX    [8]

0x423518 VMOVSD	(%RBX),%XMM3    [5]

0x42351c JMP	423270

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 94 - 129

--------------------------------------------------------------------------------

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.91
Bottlenecks
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:94-129
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	114.00
CQA cycles if no scalar integer	114.00
CQA cycles if FP arith vectorized	114.00
CQA cycles if fully vectorized	114.00
Front-end cycles	21.75
P0 cycles	29.17
P1 cycles	28.83
P2 cycles	12.67
P3 cycles	12.67
P4 cycles	0.00
P5 cycles	29.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	12.67
DIV/SQRT cycles	114.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.50
Nb uops	112.50
Nb loads	38.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	1.82
Nb FLOP add-sub	72.00
Nb FLOP mul	64.00
Nb FLOP fma	8.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.82
Bytes prefetched	0.00
Bytes loaded	1120.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	97.03
Vectorization ratio load	97.26
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	94.12
Vector-efficiency ratio all	48.89
Vector-efficiency ratio load	48.97
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.79

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.91
Bottlenecks	P0,
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:94-129
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	114.00
CQA cycles if no scalar integer	114.00
CQA cycles if FP arith vectorized	114.00
CQA cycles if fully vectorized	114.00
Front-end cycles	22.17
P0 cycles	29.17
P1 cycles	28.83
P2 cycles	13.33
P3 cycles	13.33
P4 cycles	0.00
P5 cycles	29.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	13.33
DIV/SQRT cycles	114.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	115.00
Nb uops	115.00
Nb loads	40.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	1.82
Nb FLOP add-sub	72.00
Nb FLOP mul	64.00
Nb FLOP fma	8.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.96
Bytes prefetched	0.00
Bytes loaded	1136.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	96.08
Vectorization ratio load	94.59
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	94.12
Vector-efficiency ratio all	48.53
Vector-efficiency ratio load	47.97
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.79

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.91
Bottlenecks	P0,
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:94-129
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	114.00
CQA cycles if no scalar integer	114.00
CQA cycles if FP arith vectorized	114.00
CQA cycles if fully vectorized	114.00
Front-end cycles	21.67
P0 cycles	29.17
P1 cycles	28.83
P2 cycles	12.67
P3 cycles	12.67
P4 cycles	0.00
P5 cycles	29.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	12.67
DIV/SQRT cycles	114.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	112.00
Nb loads	38.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	1.82
Nb FLOP add-sub	72.00
Nb FLOP mul	64.00
Nb FLOP fma	8.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.82
Bytes prefetched	0.00
Bytes loaded	1120.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	97.03
Vectorization ratio load	97.22
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	94.12
Vector-efficiency ratio all	48.89
Vector-efficiency ratio load	48.96
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.79

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.91
Bottlenecks	P0,
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:94-129
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	114.00
CQA cycles if no scalar integer	114.00
CQA cycles if FP arith vectorized	114.00
CQA cycles if fully vectorized	114.00
Front-end cycles	21.83
P0 cycles	29.17
P1 cycles	28.83
P2 cycles	12.67
P3 cycles	12.67
P4 cycles	0.00
P5 cycles	29.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	12.67
DIV/SQRT cycles	114.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	113.00
Nb uops	113.00
Nb loads	38.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	1.82
Nb FLOP add-sub	72.00
Nb FLOP mul	64.00
Nb FLOP fma	8.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.82
Bytes prefetched	0.00
Bytes loaded	1120.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	97.03
Vectorization ratio load	97.22
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	94.12
Vector-efficiency ratio all	48.89
Vector-efficiency ratio load	48.96
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.79

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.91
Bottlenecks	P0,
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:94-129
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	114.00
CQA cycles if no scalar integer	114.00
CQA cycles if FP arith vectorized	114.00
CQA cycles if fully vectorized	114.00
Front-end cycles	21.33
P0 cycles	29.17
P1 cycles	28.83
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	0.00
P5 cycles	29.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	12.00
DIV/SQRT cycles	114.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	110.00
Nb uops	110.00
Nb loads	36.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	1.82
Nb FLOP add-sub	72.00
Nb FLOP mul	64.00
Nb FLOP fma	8.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.68
Bytes prefetched	0.00
Bytes loaded	1104.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	98.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	94.12
Vector-efficiency ratio all	49.25
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.79

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:94-129
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94-129.

It is main loop of related source loop which is unrolled by 8 (including vectorization).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

97% of SSE/AVX loads are used in vector version.
94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 114.00 to 29.00 cycles (3.93x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

72 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

80: addition or subtraction (8 inside FMA instructions)
72: multiply (8 inside FMA instructions)
48: divide
8: square root

The binary loop is loading 1120 bytes (140 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	112.50
nb uops	112.50
loop length	677
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	31
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	21.75 cycles
front end	21.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	29.17	28.83	12.67	12.67	0.00	29.00	3.00	0.00	0.00	0.00	1.00	12.67
cycles	29.17	28.83	12.67	12.67	0.00	29.00	3.00	0.00	0.00	0.00	1.00	12.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	114.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	21.75
Dispatch	29.17
DIV/SQRT	114.00
Data deps.	0.00
Overall L1	114.00

Vectorization ratios

all	97%
load	97%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

Vector efficiency ratios

all	48%
load	48%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 114.00 cycles. At this rate:

5% of peak load performance is reached (9.82 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:94-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

94% of SSE/AVX loads are used in vector version.
94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 114.00 to 29.17 cycles (3.91x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 114.00 to 29.00 cycles (3.93x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:96
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:96
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:99
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:99
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:100
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:100
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:108
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:108
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:114
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:114
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:115
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:115

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

72 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

80: addition or subtraction (8 inside FMA instructions)
72: multiply (8 inside FMA instructions)
48: divide
8: square root

The binary loop is loading 1136 bytes (142 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	115
loop length	689
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	31
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.17 cycles
front end	22.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	29.17	28.83	13.33	13.33	0.00	29.00	3.00	0.00	0.00	0.00	1.00	13.33
cycles	29.17	28.83	13.33	13.33	0.00	29.00	3.00	0.00	0.00	0.00	1.00	13.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	114.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	22.17
Dispatch	29.17
DIV/SQRT	114.00
Data deps.	0.00
Overall L1	114.00

Vectorization ratios

all	96%
load	94%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

Vector efficiency ratios

all	48%
load	47%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 114.00 cycles. At this rate:

5% of peak load performance is reached (9.96 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4233dc

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x1b8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RBX,%R10,8),%YMM4	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RBX,%R10,8),%YMM6	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R12,%R10,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R12,%R10,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R9,%R10,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R9,%R10,8),%YMM5	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM9,%YMM9,%YMM9	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM5,%YMM5,%YMM5	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VDIVPD 0x20(%RAX,%R10,8),%YMM5,%YMM5	1	1	0	0.33	0.33	0	0	0	0.33	13-15	8	vect (50.0%)
VDIVPD (%RAX,%R10,8),%YMM9,%YMM9	1	1	0	0.33	0.33	0	0	0	0.33	13-15	8	vect (50.0%)
VFMADD231PD %YMM7,%YMM7,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM5,%YMM5	1	1	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM9,%YMM7	1	1	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMAXPD %YMM11,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM11,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM12,%YMM6,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM12,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM13,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM7,%YMM4,%YMM4	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM6,%YMM13,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM5,%YMM6,%YMM5	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM14,%YMM31,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM18,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM2,%YMM24,%YMM8	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM20,%YMM9	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM28,%YMM20	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM25,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMULPD %YMM11,%YMM26,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM26,%YMM24,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM24,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM7,%YMM7	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMAXPD %YMM25,%YMM20,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM8,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM6,%YMM6	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM15,%YMM31,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM18,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM2,%YMM21,%YMM18	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM22,%YMM20	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM30,%YMM21	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM29,%YMM22	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMAXPD %YMM26,%YMM22,%YMM22	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM22,%YMM18,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM9,%YMM9	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMAXPD %YMM25,%YMM21,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM18,%YMM20,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM8,%YMM8	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VBROADCASTSD %XMM3,%YMM3	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VXORPD 0xc3015(%RIP){1to4},%YMM3,%YMM3	1	0.33	0.33	0.33	0.33	0.33	0	0	0.33	0-1	0.40	vect (50.0%)
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVAPD %YMM0,%YMM18	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VDIVPD %YMM23,%YMM3,%YMM18{%K2}	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMINPD %YMM18,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM9,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM7,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM5,%YMM17,%YMM17	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM19,%YMM3,%YMM0{%K1}	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMINPD %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM6,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM4,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM10,%YMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JAE 423530 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x840>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVUPD -0x8(%RDX,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RDX,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x18(%RDX,%R10,8),%YMM18	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX,%R10,8),%YMM19	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD 0x18(%RDI,%R10,8),%YMM18,%YMM18	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x8(%RDI,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD -0x8(%RCX,%R10,8),%YMM0,%YMM20	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD 0x18(%RCX,%R10,8),%YMM18,%YMM24	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD (%RDI,%R10,8),%YMM3,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x20(%RDI,%R10,8),%YMM19,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD 0x20(%RCX,%R10,8),%YMM3,%YMM25	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%RCX,%R10,8),%YMM0,%YMM28	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD (%R14,%R10,8),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R14,%R10,8),%YMM27	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM27,%YMM27,%YMM18	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R11,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R11,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD -0x8(%R11,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x18(%R11,%R10,8),%YMM3,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD 0x20(%R15,%R10,8),%YMM3,%YMM21	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%R15,%R10,8),%YMM0,%YMM22	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD (%R8,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R8,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD -0x8(%R8,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x18(%R8,%R10,8),%YMM3,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD %YMM26,%YMM26,%YMM31	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x20(%R13,%R10,8),%YMM3,%YMM29	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%R13,%R10,8),%YMM0,%YMM30	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD %YMM22,%YMM20,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM21,%YMM24,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM25,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM0,%YMM28,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM30,%YMM0,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM29,%YMM3,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM3,%YMM23	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VDIVPD %YMM31,%YMM0,%YMM19	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VCMPPD $0x1,%YMM16,%YMM19,%K1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM16,%YMM23,%K2	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
KSHIFTLB $0x4,%K2,%K0	1	0	0	0	0	1	0	0	0	4	1	N/A
KORB %K0,%K1,%K0	1	1	0	0	0	0	0	0	0	1	1	N/A
KORTESTB %K0,%K0	1	1	0	0	0	0	0	0	0	0	1	N/A
JB 42350a <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x81a>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x88(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RBX),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
KORTESTB %K2,%K1	1	1	0	0	0	0	0	0	0	0	1	N/A
JE 423270 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x580>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RBX),%XMM3	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 423270 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x580>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:94-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

97% of SSE/AVX loads are used in vector version.
94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 114.00 to 29.00 cycles (3.93x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:96
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:96
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:99
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:99
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:100
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:100
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:108
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:108
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:114
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:114
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:115
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:115

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

72 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

80: addition or subtraction (8 inside FMA instructions)
72: multiply (8 inside FMA instructions)
48: divide
8: square root

The binary loop is loading 1120 bytes (140 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	112
nb uops	112
loop length	676
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	31
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.67 cycles
front end	21.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	29.17	28.83	12.67	12.67	0.00	29.00	3.00	0.00	0.00	0.00	1.00	12.67
cycles	29.17	28.83	12.67	12.67	0.00	29.00	3.00	0.00	0.00	0.00	1.00	12.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	114.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	21.67
Dispatch	29.17
DIV/SQRT	114.00
Data deps.	0.00
Overall L1	114.00

Vectorization ratios

all	97%
load	97%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

Vector efficiency ratios

all	48%
load	48%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 114.00 cycles. At this rate:

5% of peak load performance is reached (9.82 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4233dc

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x1b8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RBX,%R10,8),%YMM4	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RBX,%R10,8),%YMM6	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R12,%R10,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R12,%R10,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R9,%R10,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R9,%R10,8),%YMM5	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM9,%YMM9,%YMM9	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM5,%YMM5,%YMM5	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VDIVPD 0x20(%RAX,%R10,8),%YMM5,%YMM5	1	1	0	0.33	0.33	0	0	0	0.33	13-15	8	vect (50.0%)
VDIVPD (%RAX,%R10,8),%YMM9,%YMM9	1	1	0	0.33	0.33	0	0	0	0.33	13-15	8	vect (50.0%)
VFMADD231PD %YMM7,%YMM7,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM5,%YMM5	1	1	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM9,%YMM7	1	1	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMAXPD %YMM11,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM11,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM12,%YMM6,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM12,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM13,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM7,%YMM4,%YMM4	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM6,%YMM13,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM5,%YMM6,%YMM5	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM14,%YMM31,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM18,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM2,%YMM24,%YMM8	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM20,%YMM9	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM28,%YMM20	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM25,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMULPD %YMM11,%YMM26,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM26,%YMM24,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM24,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM7,%YMM7	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMAXPD %YMM25,%YMM20,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM8,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM6,%YMM6	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM15,%YMM31,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM18,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM2,%YMM21,%YMM18	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM22,%YMM20	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM30,%YMM21	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM29,%YMM22	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMAXPD %YMM26,%YMM22,%YMM22	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM22,%YMM18,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM9,%YMM9	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMAXPD %YMM25,%YMM21,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM18,%YMM20,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM8,%YMM8	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VBROADCASTSD %XMM3,%YMM3	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VXORPD 0xc3015(%RIP){1to4},%YMM3,%YMM3	1	0.33	0.33	0.33	0.33	0.33	0	0	0.33	0-1	0.40	vect (50.0%)
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVAPD %YMM0,%YMM18	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VDIVPD %YMM23,%YMM3,%YMM18{%K2}	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMINPD %YMM18,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM9,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM7,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM5,%YMM17,%YMM17	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM19,%YMM3,%YMM0{%K1}	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMINPD %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM6,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM4,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM10,%YMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JAE 423530 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x840>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVUPD -0x8(%RDX,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RDX,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x18(%RDX,%R10,8),%YMM18	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX,%R10,8),%YMM19	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD 0x18(%RDI,%R10,8),%YMM18,%YMM18	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x8(%RDI,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD -0x8(%RCX,%R10,8),%YMM0,%YMM20	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD 0x18(%RCX,%R10,8),%YMM18,%YMM24	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD (%RDI,%R10,8),%YMM3,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x20(%RDI,%R10,8),%YMM19,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD 0x20(%RCX,%R10,8),%YMM3,%YMM25	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%RCX,%R10,8),%YMM0,%YMM28	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD (%R14,%R10,8),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R14,%R10,8),%YMM27	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM27,%YMM27,%YMM18	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R11,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R11,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD -0x8(%R11,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x18(%R11,%R10,8),%YMM3,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD 0x20(%R15,%R10,8),%YMM3,%YMM21	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%R15,%R10,8),%YMM0,%YMM22	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD (%R8,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R8,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD -0x8(%R8,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x18(%R8,%R10,8),%YMM3,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD %YMM26,%YMM26,%YMM31	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x20(%R13,%R10,8),%YMM3,%YMM29	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%R13,%R10,8),%YMM0,%YMM30	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD %YMM22,%YMM20,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM21,%YMM24,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM25,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM0,%YMM28,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM30,%YMM0,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM29,%YMM3,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM3,%YMM23	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VDIVPD %YMM31,%YMM0,%YMM19	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VCMPPD $0x1,%YMM16,%YMM19,%K1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM16,%YMM23,%K2	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
KSHIFTLB $0x4,%K2,%K0	1	0	0	0	0	1	0	0	0	4	1	N/A
KORB %K0,%K1,%K0	1	1	0	0	0	0	0	0	0	1	1	N/A
KORTESTB %K0,%K0	1	1	0	0	0	0	0	0	0	0	1	N/A
JB 42350a <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x81a>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x88(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RBX),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
KORTESTB %K2,%K1	1	1	0	0	0	0	0	0	0	0	1	N/A
JE 423270 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x580>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:94-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

97% of SSE/AVX loads are used in vector version.
94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 114.00 to 29.00 cycles (3.93x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:96
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:96
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:99
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:99
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:100
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:100
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:108
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:108
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:114
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:114
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:115
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:115

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

72 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

80: addition or subtraction (8 inside FMA instructions)
72: multiply (8 inside FMA instructions)
48: divide
8: square root

The binary loop is loading 1120 bytes (140 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	113
nb uops	113
loop length	678
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	31
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.83 cycles
front end	21.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	29.17	28.83	12.67	12.67	0.00	29.00	3.00	0.00	0.00	0.00	1.00	12.67
cycles	29.17	28.83	12.67	12.67	0.00	29.00	3.00	0.00	0.00	0.00	1.00	12.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	114.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	21.83
Dispatch	29.17
DIV/SQRT	114.00
Data deps.	0.00
Overall L1	114.00

Vectorization ratios

all	97%
load	97%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

Vector efficiency ratios

all	48%
load	48%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 114.00 cycles. At this rate:

5% of peak load performance is reached (9.82 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4233dc

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x1b8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RBX,%R10,8),%YMM4	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RBX,%R10,8),%YMM6	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R12,%R10,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R12,%R10,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R9,%R10,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R9,%R10,8),%YMM5	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM9,%YMM9,%YMM9	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM5,%YMM5,%YMM5	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VDIVPD 0x20(%RAX,%R10,8),%YMM5,%YMM5	1	1	0	0.33	0.33	0	0	0	0.33	13-15	8	vect (50.0%)
VDIVPD (%RAX,%R10,8),%YMM9,%YMM9	1	1	0	0.33	0.33	0	0	0	0.33	13-15	8	vect (50.0%)
VFMADD231PD %YMM7,%YMM7,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM5,%YMM5	1	1	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM9,%YMM7	1	1	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMAXPD %YMM11,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM11,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM12,%YMM6,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM12,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM13,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM7,%YMM4,%YMM4	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM6,%YMM13,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM5,%YMM6,%YMM5	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM14,%YMM31,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM18,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM2,%YMM24,%YMM8	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM20,%YMM9	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM28,%YMM20	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM25,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMULPD %YMM11,%YMM26,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM26,%YMM24,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM24,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM7,%YMM7	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMAXPD %YMM25,%YMM20,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM8,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM6,%YMM6	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM15,%YMM31,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM18,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM2,%YMM21,%YMM18	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM22,%YMM20	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM30,%YMM21	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM29,%YMM22	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMAXPD %YMM26,%YMM22,%YMM22	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM22,%YMM18,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM9,%YMM9	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMAXPD %YMM25,%YMM21,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM18,%YMM20,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM8,%YMM8	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VBROADCASTSD %XMM3,%YMM3	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VXORPD 0xc3015(%RIP){1to4},%YMM3,%YMM3	1	0.33	0.33	0.33	0.33	0.33	0	0	0.33	0-1	0.40	vect (50.0%)
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVAPD %YMM0,%YMM18	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VDIVPD %YMM23,%YMM3,%YMM18{%K2}	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMINPD %YMM18,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM9,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM7,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM5,%YMM17,%YMM17	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM19,%YMM3,%YMM0{%K1}	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMINPD %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM6,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM4,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM10,%YMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JAE 423530 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x840>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVUPD -0x8(%RDX,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RDX,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x18(%RDX,%R10,8),%YMM18	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX,%R10,8),%YMM19	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD 0x18(%RDI,%R10,8),%YMM18,%YMM18	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x8(%RDI,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD -0x8(%RCX,%R10,8),%YMM0,%YMM20	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD 0x18(%RCX,%R10,8),%YMM18,%YMM24	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD (%RDI,%R10,8),%YMM3,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x20(%RDI,%R10,8),%YMM19,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD 0x20(%RCX,%R10,8),%YMM3,%YMM25	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%RCX,%R10,8),%YMM0,%YMM28	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD (%R14,%R10,8),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R14,%R10,8),%YMM27	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM27,%YMM27,%YMM18	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R11,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R11,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD -0x8(%R11,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x18(%R11,%R10,8),%YMM3,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD 0x20(%R15,%R10,8),%YMM3,%YMM21	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%R15,%R10,8),%YMM0,%YMM22	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD (%R8,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R8,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD -0x8(%R8,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x18(%R8,%R10,8),%YMM3,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD %YMM26,%YMM26,%YMM31	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x20(%R13,%R10,8),%YMM3,%YMM29	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%R13,%R10,8),%YMM0,%YMM30	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD %YMM22,%YMM20,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM21,%YMM24,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM25,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM0,%YMM28,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM30,%YMM0,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM29,%YMM3,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM3,%YMM23	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VDIVPD %YMM31,%YMM0,%YMM19	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VCMPPD $0x1,%YMM16,%YMM19,%K1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM16,%YMM23,%K2	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
KSHIFTLB $0x4,%K2,%K0	1	0	0	0	0	1	0	0	0	4	1	N/A
KORB %K0,%K1,%K0	1	1	0	0	0	0	0	0	0	1	1	N/A
KORTESTB %K0,%K0	1	1	0	0	0	0	0	0	0	0	1	N/A
JB 42350a <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x81a>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
KORTESTB %K2,%K1	1	1	0	0	0	0	0	0	0	0	1	N/A
JE 423270 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x580>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RBX),%XMM3	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 423270 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x580>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:94-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 49% of vector register length is used (average across all SSE/AVX instructions).

Details

98% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 114.00 to 29.00 cycles (3.93x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:96
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:96
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:99
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:99
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:100
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:100
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:108
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:108
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:114
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:114
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:115
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:115

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.

Type of elements and instruction set

72 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

80: addition or subtraction (8 inside FMA instructions)
72: multiply (8 inside FMA instructions)
48: divide
8: square root

The binary loop is loading 1104 bytes (138 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	110
nb uops	110
loop length	665
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	31
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.33 cycles
front end	21.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	29.17	28.83	12.00	12.00	0.00	29.00	3.00	0.00	0.00	0.00	1.00	12.00
cycles	29.17	28.83	12.00	12.00	0.00	29.00	3.00	0.00	0.00	0.00	1.00	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	114.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	21.33
Dispatch	29.17
DIV/SQRT	114.00
Data deps.	0.00
Overall L1	114.00

Vectorization ratios

all	98%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

Vector efficiency ratios

all	49%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 114.00 cycles. At this rate:

5% of peak load performance is reached (9.68 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4233dc

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x1b8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RBX,%R10,8),%YMM4	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RBX,%R10,8),%YMM6	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R12,%R10,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R12,%R10,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R9,%R10,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R9,%R10,8),%YMM5	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM9,%YMM9,%YMM9	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM5,%YMM5,%YMM5	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VDIVPD 0x20(%RAX,%R10,8),%YMM5,%YMM5	1	1	0	0.33	0.33	0	0	0	0.33	13-15	8	vect (50.0%)
VDIVPD (%RAX,%R10,8),%YMM9,%YMM9	1	1	0	0.33	0.33	0	0	0	0.33	13-15	8	vect (50.0%)
VFMADD231PD %YMM7,%YMM7,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM5,%YMM5	1	1	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM9,%YMM7	1	1	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMAXPD %YMM11,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM11,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM12,%YMM6,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM12,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM13,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM7,%YMM4,%YMM4	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM6,%YMM13,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM5,%YMM6,%YMM5	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM14,%YMM31,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM18,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM2,%YMM24,%YMM8	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM20,%YMM9	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM28,%YMM20	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM25,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMULPD %YMM11,%YMM26,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM26,%YMM24,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM24,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM7,%YMM7	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMAXPD %YMM25,%YMM20,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM8,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM8,%YMM6,%YMM6	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMULPD %YMM15,%YMM31,%YMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM18,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM2,%YMM21,%YMM18	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM22,%YMM20	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM30,%YMM21	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VANDPD %YMM2,%YMM29,%YMM22	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMAXPD %YMM26,%YMM22,%YMM22	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM22,%YMM18,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM9,%YMM9	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMAXPD %YMM25,%YMM21,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPD %YMM18,%YMM20,%YMM18	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM8,%YMM8	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VBROADCASTSD %XMM3,%YMM3	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VXORPD 0xc3015(%RIP){1to4},%YMM3,%YMM3	1	0.33	0.33	0.33	0.33	0.33	0	0	0.33	0-1	0.40	vect (50.0%)
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVAPD %YMM0,%YMM18	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VDIVPD %YMM23,%YMM3,%YMM18{%K2}	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMINPD %YMM18,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM9,%YMM7,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM7,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM5,%YMM17,%YMM17	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM19,%YMM3,%YMM0{%K1}	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMINPD %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM6,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM4,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMINPD %YMM0,%YMM10,%YMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JAE 423530 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x840>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVUPD -0x8(%RDX,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RDX,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x18(%RDX,%R10,8),%YMM18	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX,%R10,8),%YMM19	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD 0x18(%RDI,%R10,8),%YMM18,%YMM18	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x8(%RDI,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD -0x8(%RCX,%R10,8),%YMM0,%YMM20	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD 0x18(%RCX,%R10,8),%YMM18,%YMM24	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD (%RDI,%R10,8),%YMM3,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x20(%RDI,%R10,8),%YMM19,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD 0x20(%RCX,%R10,8),%YMM3,%YMM25	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%RCX,%R10,8),%YMM0,%YMM28	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD (%R14,%R10,8),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R14,%R10,8),%YMM27	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM27,%YMM27,%YMM18	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R11,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R11,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD -0x8(%R11,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x18(%R11,%R10,8),%YMM3,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VMULPD 0x20(%R15,%R10,8),%YMM3,%YMM21	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%R15,%R10,8),%YMM0,%YMM22	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD (%R8,%R10,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R8,%R10,8),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD -0x8(%R8,%R10,8),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD 0x18(%R8,%R10,8),%YMM3,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD %YMM26,%YMM26,%YMM31	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x20(%R13,%R10,8),%YMM3,%YMM29	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD (%R13,%R10,8),%YMM0,%YMM30	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VADDPD %YMM22,%YMM20,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM21,%YMM24,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM25,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM0,%YMM28,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM30,%YMM0,%YMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM29,%YMM3,%YMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM3,%YMM23	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VDIVPD %YMM31,%YMM0,%YMM19	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VCMPPD $0x1,%YMM16,%YMM19,%K1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM16,%YMM23,%K2	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
KSHIFTLB $0x4,%K2,%K0	1	0	0	0	0	1	0	0	0	4	1	N/A
KORB %K0,%K1,%K0	1	1	0	0	0	0	0	0	0	1	1	N/A
KORTESTB %K0,%K0	1	1	0	0	0	0	0	0	0	0	1	N/A
JB 42350a <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x81a>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
KORTESTB %K2,%K1	1	1	0	0	0	0	0	0	0	0	1	N/A
JE 423270 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x580>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios