OV - exec - Function field_summary_kernel_module_mp_field_summary_kernel

	Function: field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2	Module: exec	Source: field_summary_kernel.f90:54-74	Coverage (incl. loops): 0.29% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 54 - 74

--------------------------------------------------------------------------------

54:     !$OMP PARALLEL

55:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

56:     DO k=y_min,y_max

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

72:       ENDDO

73:     ENDDO

74:   !$OMP END DO

0x424770 PUSH	%RBP

0x424771 MOV	%RSP,%RBP

0x424774 PUSH	%R15

0x424776 PUSH	%R14

0x424778 PUSH	%R13

0x42477a PUSH	%R12

0x42477c PUSH	%RBX

0x42477d SUB	$0x118,%RSP

0x424784 MOV	%RCX,%R15

0x424787 MOV	0x70(%RBP),%ECX

0x42478a MOV	0x68(%RBP),%EAX

0x42478d SUB	%ECX,%EAX

0x42478f MOVL	$0,-0x64(%RBP)

0x424796 JS	42511a

0x42479c MOV	%R9,%R14

0x42479f MOV	%RDI,-0x30(%RBP)

0x4247a3 MOV	(%RDI),%ESI

0x4247a5 MOVL	$0,-0x3c(%RBP)

0x4247ac MOV	%EAX,-0x38(%RBP)

0x4247af MOVL	$0x1,-0x60(%RBP)

0x4247b6 SUB	$0x8,%RSP

0x4247ba LEA	-0x60(%RBP),%RAX

0x4247be LEA	-0x64(%RBP),%RCX

0x4247c2 LEA	-0x3c(%RBP),%R8

0x4247c6 LEA	-0x38(%RBP),%R9

0x4247ca MOV	$0x5275b0,%EDI

0x4247cf MOV	%ESI,-0x54(%RBP)

0x4247d2 MOV	$0x22,%EDX

0x4247d7 PUSH	$0x1

0x4247d9 PUSH	$0x1

0x4247db PUSH	%RAX

0x4247dc CALL	404850 <__kmpc_for_static_init_4@plt>

0x4247e1 ADD	$0x20,%RSP

0x4247e5 MOV	-0x3c(%RBP),%EDX

0x4247e8 MOV	-0x38(%RBP),%EAX

0x4247eb VXORPD	%XMM3,%XMM3,%XMM3

0x4247ef VXORPD	%XMM4,%XMM4,%XMM4

0x4247f3 VXORPD	%XMM2,%XMM2,%XMM2

0x4247f7 VXORPD	%XMM5,%XMM5,%XMM5

0x4247fb VXORPD	%XMM6,%XMM6,%XMM6

0x4247ff MOV	%EAX,-0x5c(%RBP)

0x424802 CMP	%EAX,%EDX

0x424804 JBE	424900

0x42480a MOV	0x30(%RBP),%R15

0x42480e MOV	0x28(%RBP),%R14

0x424812 MOV	0x20(%RBP),%R12

0x424816 MOV	0x18(%RBP),%RBX

0x42481a MOV	0x10(%RBP),%R13

0x42481e VMOVSD	%XMM6,-0x90(%RBP)

0x424826 VMOVSD	%XMM5,-0x88(%RBP)

0x42482e VMOVSD	%XMM2,-0x80(%RBP)

0x424833 VMOVSD	%XMM4,-0x78(%RBP)

0x424838 VMOVSD	%XMM3,-0x70(%RBP)

0x42483d MOV	$0x5275d0,%EDI

0x424842 MOV	-0x54(%RBP),%ESI

0x424845 VZEROUPPER

0x424848 CALL	404070 <__kmpc_for_static_fini@plt>

0x42484d MOV	-0x30(%RBP),%RAX

0x424851 MOV	(%RAX),%ESI

0x424853 SUB	$0x8,%RSP

0x424857 MOV	$0x580220,%RAX

0x42485e LEA	-0x90(%RBP),%R8

0x424865 MOV	$0x527690,%EDI

0x42486a MOV	$0x424720,%R9D

0x424870 MOV	$0x5,%EDX

0x424875 MOV	$0x28,%ECX

0x42487a PUSH	%RAX

0x42487b CALL	4045b0 <__kmpc_reduce@plt>

0x424880 ADD	$0x10,%RSP

0x424884 CMP	$0x2,%EAX

0x424887 JGE	42507b

0x42488d CMP	$0x1,%EAX

0x424890 MOV	-0x30(%RBP),%RDI

0x424894 JNE	42511a

0x42489a VMOVSD	-0x90(%RBP),%XMM0

0x4248a2 VADDSD	(%R15),%XMM0,%XMM0

0x4248a7 VMOVSD	%XMM0,(%R15)

0x4248ac VMOVSD	-0x88(%RBP),%XMM0

0x4248b4 VADDSD	(%R14),%XMM0,%XMM0

0x4248b9 VMOVSD	%XMM0,(%R14)

0x4248be VMOVSD	-0x80(%RBP),%XMM0

0x4248c3 VADDSD	(%R13),%XMM0,%XMM0

0x4248c9 VMOVSD	%XMM0,(%R13)

0x4248cf VMOVSD	-0x78(%RBP),%XMM0

0x4248d4 VADDSD	(%R12),%XMM0,%XMM0

0x4248da VMOVSD	%XMM0,(%R12)

0x4248e0 VMOVSD	-0x70(%RBP),%XMM0

0x4248e5 VADDSD	(%RBX),%XMM0,%XMM0

0x4248e9 VMOVSD	%XMM0,(%RBX)

0x4248ed MOV	(%RDI),%ESI

0x4248ef MOV	$0x580220,%RDX

0x4248f6 MOV	$0x5276b0,%EDI

0x4248fb JMP	425111

0x424900 MOV	0x80(%RBP),%RAX

0x424907 MOV	0x78(%RBP),%RCX

0x42490b MOV	0x40(%RBP),%RSI

0x42490f MOV	0x38(%RBP),%RDI

0x424913 MOVSXD	(%RAX),%R8

0x424916 MOV	(%RCX),%EAX

0x424918 SUB	%R8D,%EAX

0x42491b ADD	$-0x2,%R14D

0x42491f MOVSXD	%R14D,%R9

0x424922 ADD	$-0x2,%R15D

0x424926 MOVSXD	%R15D,%RCX

0x424929 MOV	%RAX,-0x120(%RBP)

0x424930 INC	%EAX

0x424932 LEA	0x2(%R8),%R10

0x424936 CMP	$0x2,%EAX

0x424939 MOV	$0x1,%R11D

0x42493f MOV	%EAX,-0x58(%RBP)

0x424942 CMOVGE	%EAX,%R11D

0x424946 MOV	%R10,-0xf0(%RBP)

0x42494d VPBROADCASTQ	%R10,%YMM0

0x424953 VPMOVSXBQ	0xc13e4(%RIP),%YMM1

0x42495c VPADDQ	%YMM1,%YMM0,%YMM0

0x424960 VPBROADCASTQ	%R8,%YMM2

0x424966 VPADDQ	%YMM1,%YMM2,%YMM1

0x42496a LEA	(,%R9,8),%RAX

0x424972 MOV	%RDI,%R10

0x424975 SUB	%RAX,%R10

0x424978 MOV	%R10,-0x108(%RBP)

0x42497f MOV	%RSI,%R10

0x424982 SUB	%RAX,%R10

0x424985 MOV	%R10,-0xa8(%RBP)

0x42498c MOV	$0x18,%R10D

0x424992 SUB	%RAX,%R10

0x424995 MOV	%R11,-0xb0(%RBP)

0x42499c AND	$0x7ffffffc,%R11D

0x4249a3 MOV	%RCX,%RAX

0x4249a6 NEG	%RAX

0x4249a9 MOV	%RAX,-0x100(%RBP)

0x4249b0 LEA	(%RDI,%R10,1),%RAX

0x4249b4 MOV	%RAX,-0x98(%RBP)

0x4249bb ADD	%RSI,%R10

0x4249be MOV	%R10,-0xa0(%RBP)

0x4249c5 MOV	$0x1,%EAX

0x4249ca MOV	%RCX,-0x110(%RBP)

0x4249d1 SUB	%RCX,%RAX

0x4249d4 MOV	%RAX,-0xf8(%RBP)

0x4249db VPXOR	%XMM2,%XMM2,%XMM2

0x4249df VMOVSD	0xc1549(%RIP),%XMM7

0x4249e7 VMOVSD	0xc0f89(%RIP),%XMM8

0x4249ef VBROADCASTSD	0xc0f80(%RIP),%YMM9

0x4249f8 VBROADCASTSD	0xc152f(%RIP),%YMM10

0x424a01 VPBROADCASTQ	0xc537e(%RIP),%YMM11

0x424a0a VPCMPEQD	%YMM12,%YMM12,%YMM12

0x424a0f LEA	0x2(%R8,%R11,1),%RAX

0x424a14 MOV	%RAX,-0xe8(%RBP)

0x424a1b MOV	%R8,-0x48(%RBP)

0x424a1f LEA	(%R11,%R8,1),%RAX

0x424a23 MOV	%RAX,-0xe0(%RBP)

0x424a2a MOV	0x70(%RBP),%EAX

0x424a2d ADD	%EDX,%EAX

0x424a2f MOV	%EAX,-0x34(%RBP)

0x424a32 MOV	%R11,-0x118(%RBP)

0x424a39 JMP	424a5f

0x424a3b NOPL	(%RAX,%RAX,1)

(199) 0x424a40 MOV	-0x128(%RBP),%RCX

(199) 0x424a47 LEA	0x1(%RCX),%EAX

(199) 0x424a4a INCL	-0x34(%RBP)

(199) 0x424a4d CMP	-0x5c(%RBP),%ECX

(199) 0x424a50 MOV	%EAX,%EDX

(199) 0x424a52 MOV	-0x118(%RBP),%R11

(199) 0x424a59 JE	42480a

(199) 0x424a5f CMPL	$0,-0x120(%RBP)

(199) 0x424a66 MOV	%RDX,-0x128(%RBP)

(199) 0x424a6d JS	424a40

(199) 0x424a6f MOV	0x70(%RBP),%EAX

(199) 0x424a72 ADD	%EDX,%EAX

(199) 0x424a74 CLTQ

(199) 0x424a76 SUB	-0x110(%RBP),%RAX

(199) 0x424a7d MOV	0x98(%RBP),%RCX

(199) 0x424a84 MOV	(%RCX),%RCX

(199) 0x424a87 IMUL	%RAX,%RCX

(199) 0x424a8b ADD	0x60(%RBP),%RCX

(199) 0x424a8f MOV	%RCX,-0xd0(%RBP)

(199) 0x424a96 MOV	0xa0(%RBP),%RCX

(199) 0x424a9d MOV	(%RCX),%RCX

(199) 0x424aa0 IMUL	%RAX,%RCX

(199) 0x424aa4 ADD	0x58(%RBP),%RCX

(199) 0x424aa8 MOV	%RCX,-0xc8(%RBP)

(199) 0x424aaf MOV	0xa8(%RBP),%RCX

(199) 0x424ab6 MOV	(%RCX),%RCX

(199) 0x424ab9 IMUL	%RAX,%RCX

(199) 0x424abd ADD	0x50(%RBP),%RCX

(199) 0x424ac1 MOV	%RCX,-0xc0(%RBP)

(199) 0x424ac8 MOV	0xb0(%RBP),%RCX

(199) 0x424acf MOV	(%RCX),%RCX

(199) 0x424ad2 IMUL	%RAX,%RCX

(199) 0x424ad6 ADD	0x48(%RBP),%RCX

(199) 0x424ada MOV	%RCX,-0xb8(%RBP)

(199) 0x424ae1 MOV	0x88(%RBP),%RCX

(199) 0x424ae8 MOV	(%RCX),%R13

(199) 0x424aeb MOV	0x90(%RBP),%RCX

(199) 0x424af2 MOV	(%RCX),%R10

(199) 0x424af5 CMPL	$0x4,-0x58(%RBP)

(199) 0x424af9 JGE	424b10

(199) 0x424afb XOR	%ESI,%ESI

(199) 0x424afd MOV	-0xf0(%RBP),%RBX

(199) 0x424b04 MOV	-0x48(%RBP),%RDI

(199) 0x424b08 JMP	424d45

0x424b0d NOPL	(%RAX)

(199) 0x424b10 MOV	%R13,%RCX

(199) 0x424b13 IMUL	%RAX,%RCX

(199) 0x424b17 MOV	0x40(%RBP),%RDI

(199) 0x424b1b ADD	%RDI,%RCX

(199) 0x424b1e MOV	%R10,%RDX

(199) 0x424b21 IMUL	%RAX,%RDX

(199) 0x424b25 MOV	0x38(%RBP),%R8

(199) 0x424b29 ADD	%R8,%RDX

(199) 0x424b2c INC	%RAX

(199) 0x424b2f MOV	%R13,%RSI

(199) 0x424b32 IMUL	%RAX,%RSI

(199) 0x424b36 ADD	%RDI,%RSI

(199) 0x424b39 IMUL	%R10,%RAX

(199) 0x424b3d ADD	%R8,%RAX

(199) 0x424b40 VXORPD	%XMM16,%XMM16,%XMM16

(199) 0x424b46 XOR	%EDI,%EDI

(199) 0x424b48 VMOVDQA64	%YMM0,%YMM18

(199) 0x424b4e VMOVDQA64	%YMM1,%YMM19

(199) 0x424b54 VXORPD	%XMM17,%XMM17,%XMM17

(199) 0x424b5a VXORPD	%XMM15,%XMM15,%XMM15

(199) 0x424b5f VXORPD	%XMM14,%XMM14,%XMM14

(199) 0x424b64 VXORPD	%XMM13,%XMM13,%XMM13

(199) 0x424b69 NOPL	(%RAX)

  (202) 0x424b70 VPCMPEQB	%XMM0,%XMM0,%K1

  (202) 0x424b76 VMOVDQA64	%YMM19,%YMM22

  (202) 0x424b7c VXORPD	%XMM21,%XMM21,%XMM21

  (202) 0x424b82 NOPW	%CS:(%RAX,%RAX,1)

    (200) 0x424b90 VMOVQ	%XMM22,%R8

    (200) 0x424b96 VPSUBQ	%YMM12,%YMM22,%YMM22

    (200) 0x424b9c SUB	%R9,%R8

    (200) 0x424b9f VMOVUPD	(%RDX,%R8,8),%YMM23{%K1}{z}

    (200) 0x424ba6 VMOVUPD	(%RCX,%R8,8),%YMM24{%K1}{z}

    (200) 0x424bad VMULPD	%YMM24,%YMM24,%YMM24

    (200) 0x424bb3 VFMADD231PD	%YMM23,%YMM23,%YMM24

    (200) 0x424bb9 VFMADD231PD	%YMM9,%YMM24,%YMM21

    (200) 0x424bbf VMOVAPD	%YMM21,%YMM20{%K1}

    (200) 0x424bc5 VPCMPNEQQ	%YMM18,%YMM22,%K1{%K1}

    (200) 0x424bcc KORTESTB	%K1,%K1

    (200) 0x424bd0 JNE	424b90

  (202) 0x424bd2 VPCMPEQB	%XMM0,%XMM0,%K1

  (202) 0x424bd8 VMOVDQA64	%YMM19,%YMM22

  (202) 0x424bde XCHG	%AX,%AX

    (201) 0x424be0 VMOVQ	%XMM22,%R8

    (201) 0x424be6 VPSUBQ	%YMM12,%YMM22,%YMM22

    (201) 0x424bec SUB	%R9,%R8

    (201) 0x424bef VMOVUPD	(%RAX,%R8,8),%YMM23{%K1}{z}

    (201) 0x424bf6 VMOVUPD	(%RSI,%R8,8),%YMM24{%K1}{z}

    (201) 0x424bfd VMULPD	%YMM24,%YMM24,%YMM24

    (201) 0x424c03 VFMADD231PD	%YMM23,%YMM23,%YMM24

    (201) 0x424c09 VFMADD231PD	%YMM9,%YMM24,%YMM20

    (201) 0x424c0f VMOVAPD	%YMM20,%YMM21{%K1}

    (201) 0x424c15 VPCMPNEQQ	%YMM18,%YMM22,%K1{%K1}

    (201) 0x424c1c KORTESTB	%K1,%K1

    (201) 0x424c20 JNE	424be0

  (202) 0x424c22 MOV	-0x48(%RBP),%R8

  (202) 0x424c26 ADD	%RDI,%R8

  (202) 0x424c29 SUB	%R9,%R8

  (202) 0x424c2c MOV	-0xd0(%RBP),%RBX

  (202) 0x424c33 VMOVUPD	(%RBX,%R8,8),%YMM20

  (202) 0x424c3a MOV	-0xc8(%RBP),%RBX

  (202) 0x424c41 VMULPD	(%RBX,%R8,8),%YMM20,%YMM22

  (202) 0x424c48 VADDPD	%YMM20,%YMM13,%YMM13

  (202) 0x424c4e VADDPD	%YMM22,%YMM14,%YMM14

  (202) 0x424c54 MOV	-0xc0(%RBP),%RBX

  (202) 0x424c5b VFMADD231PD	(%RBX,%R8,8),%YMM22,%YMM15

  (202) 0x424c62 VMULPD	%YMM10,%YMM22,%YMM22

  (202) 0x424c68 VFMADD231PD	%YMM21,%YMM22,%YMM17

  (202) 0x424c6e MOV	-0xb8(%RBP),%RBX

  (202) 0x424c75 VFMADD231PD	(%RBX,%R8,8),%YMM20,%YMM16

  (202) 0x424c7c ADD	$0x4,%RDI

  (202) 0x424c80 VPADDQ	%YMM11,%YMM19,%YMM19

  (202) 0x424c86 VPADDQ	%YMM11,%YMM18,%YMM18

  (202) 0x424c8c CMP	%R11,%RDI

  (202) 0x424c8f JB	424b70

(199) 0x424c95 VEXTRACTF32X4	$0x1,%YMM16,%XMM18

(199) 0x424c9c VADDPD	%XMM18,%XMM16,%XMM16

(199) 0x424ca2 VSHUFPD	$0x1,%XMM16,%XMM16,%XMM18

(199) 0x424ca9 VADDSD	%XMM18,%XMM16,%XMM16

(199) 0x424caf VADDSD	%XMM16,%XMM2,%XMM2

(199) 0x424cb5 VEXTRACTF32X4	$0x1,%YMM17,%XMM16

(199) 0x424cbc VADDPD	%XMM16,%XMM17,%XMM16

(199) 0x424cc2 VSHUFPD	$0x1,%XMM16,%XMM16,%XMM17

(199) 0x424cc9 VADDSD	%XMM17,%XMM16,%XMM16

(199) 0x424ccf VADDSD	%XMM16,%XMM3,%XMM3

(199) 0x424cd5 VEXTRACTF32X4	$0x1,%YMM15,%XMM16

(199) 0x424cdc VADDPD	%XMM16,%XMM15,%XMM15

(199) 0x424ce2 VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

(199) 0x424ce9 VADDSD	%XMM16,%XMM15,%XMM15

(199) 0x424cef VADDSD	%XMM4,%XMM15,%XMM4

(199) 0x424cf3 VEXTRACTF128	$0x1,%YMM14,%XMM15

(199) 0x424cf9 VADDPD	%XMM15,%XMM14,%XMM14

(199) 0x424cfe VSHUFPD	$0x1,%XMM14,%XMM14,%XMM15

(199) 0x424d04 VADDSD	%XMM15,%XMM14,%XMM14

(199) 0x424d09 VADDSD	%XMM5,%XMM14,%XMM5

(199) 0x424d0d VEXTRACTF128	$0x1,%YMM13,%XMM14

(199) 0x424d13 VADDPD	%XMM14,%XMM13,%XMM13

(199) 0x424d18 VSHUFPD	$0x1,%XMM13,%XMM13,%XMM14

(199) 0x424d1e VADDSD	%XMM14,%XMM13,%XMM13

(199) 0x424d23 VADDSD	%XMM6,%XMM13,%XMM6

(199) 0x424d27 MOV	%R11,%RSI

(199) 0x424d2a MOV	-0xe8(%RBP),%RBX

(199) 0x424d31 MOV	-0xe0(%RBP),%RDI

(199) 0x424d38 CMP	-0xb0(%RBP),%R11D

(199) 0x424d3f JE	424a40

(199) 0x424d45 MOVSXD	-0x34(%RBP),%R14

(199) 0x424d49 MOV	-0xf8(%RBP),%RAX

(199) 0x424d50 LEA	(%RAX,%R14,1),%R11

(199) 0x424d54 ADD	-0x100(%RBP),%R14

(199) 0x424d5b MOV	%RBX,%R8

(199) 0x424d5e SUB	%RDI,%R8

(199) 0x424d61 MOV	%RDI,%RAX

(199) 0x424d64 NOT	%RAX

(199) 0x424d67 ADD	%RBX,%RAX

(199) 0x424d6a MOV	%RAX,-0xd8(%RBP)

(199) 0x424d71 MOV	%R8,-0x130(%RBP)

(199) 0x424d78 AND	$0x3,%R8D

(199) 0x424d7c MOV	%RDI,%RAX

(199) 0x424d7f NEG	%RAX

(199) 0x424d82 MOV	%RAX,-0x50(%RBP)

(199) 0x424d86 MOV	%R10,%RDX

(199) 0x424d89 IMUL	%R14,%RDX

(199) 0x424d8d LEA	(%RDX,%RDI,8),%R12

(199) 0x424d91 MOV	-0x108(%RBP),%R15

(199) 0x424d98 ADD	%R15,%R12

(199) 0x424d9b IMUL	%R13,%R14

(199) 0x424d9f LEA	(%R14,%RDI,8),%RAX

(199) 0x424da3 ADD	-0xa8(%RBP),%RAX

(199) 0x424daa ADD	-0x98(%RBP),%RDX

(199) 0x424db1 ADD	-0xa0(%RBP),%R14

(199) 0x424db8 IMUL	%R11,%R10

(199) 0x424dbc LEA	(%R10,%RDI,8),%RCX

(199) 0x424dc0 ADD	%R15,%RCX

(199) 0x424dc3 IMUL	%R11,%R13

(199) 0x424dc7 LEA	(,%RDI,8),%R11

(199) 0x424dcf ADD	%R13,%R11

(199) 0x424dd2 ADD	-0xa8(%RBP),%R11

(199) 0x424dd9 ADD	-0x98(%RBP),%R10

(199) 0x424de0 ADD	-0xa0(%RBP),%R13

(199) 0x424de7 JMP	424e76

0x424dec NOPL	(%RAX)

  (204) 0x424df0 MOV	-0x48(%RBP),%R15

  (204) 0x424df4 ADD	%RSI,%R15

  (204) 0x424df7 SUB	%R9,%R15

  (204) 0x424dfa MOV	%RSI,%RDI

  (204) 0x424dfd MOV	-0xd0(%RBP),%RSI

  (204) 0x424e04 VMOVSD	(%RSI,%R15,8),%XMM14

  (204) 0x424e0a MOV	-0xc8(%RBP),%RSI

  (204) 0x424e11 VMULSD	(%RSI,%R15,8),%XMM14,%XMM15

  (204) 0x424e17 MOV	-0xc0(%RBP),%RSI

  (204) 0x424e1e VFMADD231SD	(%RSI,%R15,8),%XMM15,%XMM4

  (204) 0x424e24 MOV	-0xb8(%RBP),%RSI

  (204) 0x424e2b VFMADD231SD	(%RSI,%R15,8),%XMM14,%XMM2

  (204) 0x424e31 MOV	%RDI,%RSI

  (204) 0x424e34 VADDSD	%XMM6,%XMM14,%XMM6

  (204) 0x424e38 VADDSD	%XMM5,%XMM15,%XMM5

  (204) 0x424e3c VMULSD	%XMM7,%XMM15,%XMM14

  (204) 0x424e40 VFMADD231SD	%XMM14,%XMM13,%XMM3

  (204) 0x424e45 INC	%RSI

  (204) 0x424e48 MOV	-0x138(%RBP),%RDI

  (204) 0x424e4f INC	%RDI

  (204) 0x424e52 INC	%RBX

  (204) 0x424e55 DECQ	-0x50(%RBP)

  (204) 0x424e59 ADD	$0x8,%R12

  (204) 0x424e5d ADD	$0x8,%RAX

  (204) 0x424e61 ADD	$0x8,%RCX

  (204) 0x424e65 ADD	$0x8,%R11

  (204) 0x424e69 CMP	-0xb0(%RBP),%RSI

  (204) 0x424e70 JE	424a40

  (204) 0x424e76 VXORPD	%XMM13,%XMM13,%XMM13

  (204) 0x424e7b TEST	%R8,%R8

  (204) 0x424e7e JE	424fb0

  (204) 0x424e84 XOR	%R15D,%R15D

  (204) 0x424e87 NOPW	(%RAX,%RAX,1)

    (207) 0x424e90 VMOVSD	(%RAX,%R15,8),%XMM14

    (207) 0x424e96 VMULSD	%XMM14,%XMM14,%XMM14

    (207) 0x424e9b VMOVSD	(%R12,%R15,8),%XMM15

    (207) 0x424ea1 VFMADD213SD	%XMM14,%XMM15,%XMM15

    (207) 0x424ea6 VFMADD231SD	%XMM8,%XMM15,%XMM13

    (207) 0x424eab INC	%R15

    (207) 0x424eae CMP	%R15,%R8

    (207) 0x424eb1 JNE	424e90

  (204) 0x424eb3 SUB	-0x50(%RBP),%R15

  (204) 0x424eb7 CMPQ	$0x3,-0xd8(%RBP)

  (204) 0x424ebf JB	424f55

  (204) 0x424ec5 NOPW	%CS:(%RAX,%RAX,1)

    (203) 0x424ed0 VMOVSD	-0x18(%R14,%R15,8),%XMM14

    (203) 0x424ed7 VMOVSD	-0x10(%R14,%R15,8),%XMM15

    (203) 0x424ede VMOVSD	-0x18(%RDX,%R15,8),%XMM16

    (203) 0x424ee6 VMULSD	%XMM14,%XMM14,%XMM14

    (203) 0x424eeb VMOVSD	-0x10(%RDX,%R15,8),%XMM17

    (203) 0x424ef3 VFMADD213SD	%XMM14,%XMM16,%XMM16

    (203) 0x424ef9 VFMADD213SD	%XMM13,%XMM8,%XMM16

    (203) 0x424eff VMULSD	%XMM15,%XMM15,%XMM13

    (203) 0x424f04 VFMADD231SD	%XMM17,%XMM17,%XMM13

    (203) 0x424f0a VFMADD213SD	%XMM16,%XMM8,%XMM13

    (203) 0x424f10 VMOVSD	-0x8(%R14,%R15,8),%XMM14

    (203) 0x424f17 VMOVSD	-0x8(%RDX,%R15,8),%XMM15

    (203) 0x424f1e VMULSD	%XMM14,%XMM14,%XMM14

    (203) 0x424f23 VFMADD213SD	%XMM14,%XMM15,%XMM15

    (203) 0x424f28 VFMADD213SD	%XMM13,%XMM8,%XMM15

    (203) 0x424f2d VMOVSD	(%R14,%R15,8),%XMM13

    (203) 0x424f33 VMULSD	%XMM13,%XMM13,%XMM14

    (203) 0x424f38 VMOVSD	(%RDX,%R15,8),%XMM13

    (203) 0x424f3e VFMADD213SD	%XMM14,%XMM13,%XMM13

    (203) 0x424f43 VFMADD213SD	%XMM15,%XMM8,%XMM13

    (203) 0x424f48 ADD	$0x4,%R15

    (203) 0x424f4c CMP	%R15,%RBX

    (203) 0x424f4f JNE	424ed0

  (204) 0x424f55 TESTB	$0x3,-0x130(%RBP)

  (204) 0x424f5c JE	424fd0

  (204) 0x424f5e XOR	%R15D,%R15D

  (204) 0x424f61 NOPW	%CS:(%RAX,%RAX,1)

    (206) 0x424f70 VMOVSD	(%R11,%R15,8),%XMM14

    (206) 0x424f76 VMULSD	%XMM14,%XMM14,%XMM14

    (206) 0x424f7b VMOVSD	(%RCX,%R15,8),%XMM15

    (206) 0x424f81 VFMADD213SD	%XMM14,%XMM15,%XMM15

    (206) 0x424f86 VFMADD231SD	%XMM8,%XMM15,%XMM13

    (206) 0x424f8b INC	%R15

    (206) 0x424f8e CMP	%R15,%R8

    (206) 0x424f91 JNE	424f70

  (204) 0x424f93 SUB	-0x50(%RBP),%R15

  (204) 0x424f97 MOV	%RDI,-0x138(%RBP)

  (204) 0x424f9e CMPQ	$0x3,-0xd8(%RBP)

  (204) 0x424fa6 JAE	424ff0

  (204) 0x424fa8 JMP	424df0

0x424fad NOPL	(%RAX)

  (204) 0x424fb0 MOV	%RDI,%R15

  (204) 0x424fb3 CMPQ	$0x3,-0xd8(%RBP)

  (204) 0x424fbb JAE	424ed0

  (204) 0x424fc1 JMP	424f55

0x424fc3 NOPW	%CS:(%RAX,%RAX,1)

  (204) 0x424fd0 MOV	%RDI,%R15

  (204) 0x424fd3 MOV	%RDI,-0x138(%RBP)

  (204) 0x424fda CMPQ	$0x3,-0xd8(%RBP)

  (204) 0x424fe2 JB	424df0

  (204) 0x424fe8 NOPL	(%RAX,%RAX,1)

    (205) 0x424ff0 VMOVSD	-0x18(%R13,%R15,8),%XMM14

    (205) 0x424ff7 VMOVSD	-0x10(%R13,%R15,8),%XMM15

    (205) 0x424ffe VMOVSD	-0x18(%R10,%R15,8),%XMM16

    (205) 0x425006 VMULSD	%XMM14,%XMM14,%XMM14

    (205) 0x42500b VMOVSD	-0x10(%R10,%R15,8),%XMM17

    (205) 0x425013 VFMADD213SD	%XMM14,%XMM16,%XMM16

    (205) 0x425019 VFMADD213SD	%XMM13,%XMM8,%XMM16

    (205) 0x42501f VMULSD	%XMM15,%XMM15,%XMM13

    (205) 0x425024 VFMADD231SD	%XMM17,%XMM17,%XMM13

    (205) 0x42502a VFMADD213SD	%XMM16,%XMM8,%XMM13

    (205) 0x425030 VMOVSD	-0x8(%R13,%R15,8),%XMM14

    (205) 0x425037 VMOVSD	-0x8(%R10,%R15,8),%XMM15

    (205) 0x42503e VMULSD	%XMM14,%XMM14,%XMM14

    (205) 0x425043 VFMADD213SD	%XMM14,%XMM15,%XMM15

    (205) 0x425048 VFMADD213SD	%XMM13,%XMM8,%XMM15

    (205) 0x42504d VMOVSD	(%R13,%R15,8),%XMM13

    (205) 0x425054 VMULSD	%XMM13,%XMM13,%XMM14

    (205) 0x425059 VMOVSD	(%R10,%R15,8),%XMM13

    (205) 0x42505f VFMADD213SD	%XMM14,%XMM13,%XMM13

    (205) 0x425064 VFMADD213SD	%XMM15,%XMM8,%XMM13

    (205) 0x425069 ADD	$0x4,%R15

    (205) 0x42506d CMP	%R15,%RBX

    (205) 0x425070 JNE	424ff0

  (204) 0x425076 JMP	424df0

0x42507b MOV	-0x30(%RBP),%RDI

0x42507f JNE	42511a

0x425085 VMOVSD	-0x90(%RBP),%XMM0

0x42508d MOV	(%RDI),%ESI

0x42508f MOV	$0x5275f0,%EDI

0x425094 MOV	%R15,%RDX

0x425097 CALL	404150 <__kmpc_atomic_float8_add@plt>

0x42509c VMOVSD	-0x88(%RBP),%XMM0

0x4250a4 MOV	-0x30(%RBP),%RAX

0x4250a8 MOV	(%RAX),%ESI

0x4250aa MOV	$0x527610,%EDI

0x4250af MOV	%R14,%RDX

0x4250b2 CALL	404150 <__kmpc_atomic_float8_add@plt>

0x4250b7 VMOVSD	-0x80(%RBP),%XMM0

0x4250bc MOV	-0x30(%RBP),%RAX

0x4250c0 MOV	(%RAX),%ESI

0x4250c2 MOV	$0x527630,%EDI

0x4250c7 MOV	%R13,%RDX

0x4250ca CALL	404150 <__kmpc_atomic_float8_add@plt>

0x4250cf VMOVSD	-0x78(%RBP),%XMM0

0x4250d4 MOV	-0x30(%RBP),%RAX

0x4250d8 MOV	(%RAX),%ESI

0x4250da MOV	$0x527650,%EDI

0x4250df MOV	%R12,%RDX

0x4250e2 CALL	404150 <__kmpc_atomic_float8_add@plt>

0x4250e7 VMOVSD	-0x70(%RBP),%XMM0

0x4250ec MOV	-0x30(%RBP),%RAX

0x4250f0 MOV	(%RAX),%ESI

0x4250f2 MOV	$0x527670,%EDI

0x4250f7 MOV	%RBX,%RDX

0x4250fa CALL	404150 <__kmpc_atomic_float8_add@plt>

0x4250ff MOV	-0x30(%RBP),%RAX

0x425103 MOV	(%RAX),%ESI

0x425105 MOV	$0x580220,%RDX

0x42510c MOV	$0x5276d0,%EDI

0x425111 CALL	404170 <__kmpc_end_reduce@plt>

0x425116 MOV	-0x30(%RBP),%RDI

0x42511a MOV	(%RDI),%ESI

0x42511c MOV	$0x5276f0,%EDI

0x425121 CALL	4047c0 <__kmpc_barrier@plt>

0x425126 ADD	$0x118,%RSP

0x42512d POP	%RBX

0x42512e POP	%R12

0x425130 POP	%R13

0x425132 POP	%R14

0x425134 POP	%R15

0x425136 POP	%RBP

0x425137 RET

0x425138 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	field_summary_kernel.f90:54-74
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-74.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.00 to 9.83 cycles (3.76x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

2% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
28% of SSE/AVX addition or subtraction instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_atomic_float8_add@plt: 5 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:57
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:60
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 380 bytes (47 double precision FP elements). The binary function is storing 232 bytes (29 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	210
nb uops	222
loop length	940
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	7
used zmm registers	0
nb stack references	39

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	37.00 cycles
front end	37.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.20	12.17	21.33	21.33	26.50	12.23	12.20	26.50	26.50	26.50	12.20	21.33
cycles	12.20	12.17	21.33	21.33	26.50	12.23	12.20	26.50	26.50	26.50	12.20	21.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	37.00
Dispatch	26.50
Overall L1	37.00

Vectorization ratios

INT

all	10%
load	6%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	14%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	11%
load	2%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	11%
load	7%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	12%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.00 cycles. At this rate:

5% of peak load performance is reached (10.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 37.00 to 26.50 cycles (1.40x speedup).

ASM code

In the binary file, the address of the function is: 424770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x70(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,-0x64(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 42511a <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9aa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x64(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5275b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x54(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x3c(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x38(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %EAX,-0x5c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 424900 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM6,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM5,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x5275d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x54(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x580220,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x90(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x527690,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x424720,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x5,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x28,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4045b0 <__kmpc_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42507b <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x90b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 42511a <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9aa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x90(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R15),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R14),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x80(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R13),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x78(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R12),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%RBX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x580220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5276b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 425111 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9a1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R8D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $-0x2,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R14D,%R9	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD $-0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R15D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RAX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%R8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMOVGE %EAX,%R11D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %R10,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R10,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPMOVSXBQ 0xc13e4(%RIP),%YMM1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
VPADDQ %YMM1,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBROADCASTQ %R8,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %YMM1,%YMM2,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
LEA (,%R9,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x18,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffffc,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NEG %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%R10,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0xc1549(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc0f89(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VBROADCASTSD 0xc0f80(%RIP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0xc152f(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xc537e(%RIP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPCMPEQD %YMM12,%YMM12,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (50.0%)
LEA 0x2(%R8,%R11,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R11,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 424a5f <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x2ef>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 42511a <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9aa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x90(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x5275f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527610,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x80(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527630,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x78(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527650,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527670,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x580220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5276d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404170 <__kmpc_end_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x5276f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4047c0 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	field_summary_kernel.f90:54-74
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.00 to 9.83 cycles (3.76x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

2% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
28% of SSE/AVX addition or subtraction instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

__kmpc_atomic_float8_add@plt: 5 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:57
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:60
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 380 bytes (47 double precision FP elements). The binary function is storing 232 bytes (29 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	210
nb uops	222
loop length	940
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	7
used zmm registers	0
nb stack references	39

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	37.00 cycles
front end	37.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.20	12.17	21.33	21.33	26.50	12.23	12.20	26.50	26.50	26.50	12.20	21.33
cycles	12.20	12.17	21.33	21.33	26.50	12.23	12.20	26.50	26.50	26.50	12.20	21.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	37.00
Dispatch	26.50
Overall L1	37.00

Vectorization ratios

INT

all	10%
load	6%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	14%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	11%
load	2%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	11%
load	7%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	12%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.00 cycles. At this rate:

5% of peak load performance is reached (10.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 424770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x70(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,-0x64(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 42511a <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9aa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x64(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5275b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x54(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x3c(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x38(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %EAX,-0x5c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 424900 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM6,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM5,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x5275d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x54(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x580220,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x90(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x527690,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x424720,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x5,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x28,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4045b0 <__kmpc_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42507b <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x90b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 42511a <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9aa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x90(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R15),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R14),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x80(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R13),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x78(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R12),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%RBX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x580220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5276b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 425111 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9a1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R8D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $-0x2,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R14D,%R9	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD $-0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R15D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RAX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%R8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMOVGE %EAX,%R11D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %R10,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R10,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPMOVSXBQ 0xc13e4(%RIP),%YMM1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
VPADDQ %YMM1,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBROADCASTQ %R8,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %YMM1,%YMM2,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
LEA (,%R9,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x18,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffffc,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NEG %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%R10,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0xc1549(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc0f89(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VBROADCASTSD 0xc0f80(%RIP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0xc152f(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xc537e(%RIP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPCMPEQD %YMM12,%YMM12,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (50.0%)
LEA 0x2(%R8,%R11,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R11,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 424a5f <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x2ef>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 42511a <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9aa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x90(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x5275f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527610,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x80(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527630,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x78(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527650,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527670,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x580220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5276d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404170 <__kmpc_end_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x5276f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4047c0 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2–	0.29	0.11
▼Loop 199 - field_summary_kernel.f90:56-71 - exec–	0.00	0.00
▼Loop 202 - field_summary_kernel.f90:58-71 - exec–	0.16	0.06
○Loop 201 - field_summary_kernel.f90:62-63 - exec	0.11	0.04
○Loop 200 - field_summary_kernel.f90:62-63 - exec	0.01	0.01
▼Loop 204 - field_summary_kernel.f90:58-71 - exec–	0.00	0.00
○Loop 205 - field_summary_kernel.f90:62-63 - exec	0.00	0.00
○Loop 203 - field_summary_kernel.f90:62-63 - exec	0.00	0.00
○Loop 207 - field_summary_kernel.f90:62-63 - exec	0.00	0.00
○Loop 206 - field_summary_kernel.f90:62-63 - exec	0.00	0.00

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512-bits vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

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