OV - exec - Function calc_dt_kernel_module_mp_calc_dt_kernel

	Function: calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2	Module: exec	Source: calc_dt_kernel.f90:89-133	Coverage (incl. loops): 3.27% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 133

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89:     !$OMP PARALLEL

90:

91:     !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val)

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

130:

131:       ENDDO

132:     ENDDO

133:     !$OMP END DO

0x422cf0 PUSH	%RBP

0x422cf1 MOV	%RSP,%RBP

0x422cf4 PUSH	%R15

0x422cf6 PUSH	%R14

0x422cf8 PUSH	%R13

0x422cfa PUSH	%R12

0x422cfc PUSH	%RBX

0x422cfd SUB	$0x1f8,%RSP

0x422d04 MOV	0xa0(%RBP),%EBX

0x422d0a MOV	0x98(%RBP),%EAX

0x422d10 SUB	%EBX,%EAX

0x422d12 MOVL	$0,-0x54(%RBP)

0x422d19 JS	422e06

0x422d1f MOV	%R9,%R12

0x422d22 MOV	%RCX,%R15

0x422d25 MOV	%RDI,-0x60(%RBP)

0x422d29 MOV	(%RDI),%ESI

0x422d2b MOVL	$0,-0x30(%RBP)

0x422d32 MOV	%EAX,-0x2c(%RBP)

0x422d35 MOVL	$0x1,-0x50(%RBP)

0x422d3c SUB	$0x8,%RSP

0x422d40 LEA	-0x50(%RBP),%RAX

0x422d44 LEA	-0x54(%RBP),%RCX

0x422d48 LEA	-0x30(%RBP),%R8

0x422d4c LEA	-0x2c(%RBP),%R9

0x422d50 MOV	$0x5273d0,%EDI

0x422d55 MOV	%ESI,-0x44(%RBP)

0x422d58 MOV	$0x22,%EDX

0x422d5d PUSH	$0x1

0x422d5f PUSH	$0x1

0x422d61 PUSH	%RAX

0x422d62 CALL	404850 <__kmpc_for_static_init_4@plt>

0x422d67 ADD	$0x20,%RSP

0x422d6b MOV	-0x30(%RBP),%ESI

0x422d6e MOV	-0x2c(%RBP),%EAX

0x422d71 SUB	%ESI,%EAX

0x422d73 MOV	%EAX,-0x48(%RBP)

0x422d76 JAE	422e24

0x422d7c VMOVSD	0xc69bc(%RIP),%XMM10

0x422d84 VMOVSD	%XMM10,-0x90(%RBP)

0x422d8c MOV	$0x5273f0,%EDI

0x422d91 MOV	-0x44(%RBP),%ESI

0x422d94 VZEROUPPER

0x422d97 CALL	404070 <__kmpc_for_static_fini@plt>

0x422d9c MOV	-0x60(%RBP),%RBX

0x422da0 MOV	(%RBX),%ESI

0x422da2 SUB	$0x8,%RSP

0x422da6 MOV	$0x580220,%RAX

0x422dad LEA	-0x90(%RBP),%R8

0x422db4 MOV	$0x527410,%EDI

0x422db9 MOV	$0x422ce0,%R9D

0x422dbf MOV	$0x1,%EDX

0x422dc4 MOV	$0x8,%ECX

0x422dc9 PUSH	%RAX

0x422dca CALL	4045b0 <__kmpc_reduce@plt>

0x422dcf MOV	%RBX,%RDI

0x422dd2 ADD	$0x10,%RSP

0x422dd6 CMP	$0x1,%EAX

0x422dd9 JNE	422e06

0x422ddb VMOVSD	-0x90(%RBP),%XMM0

0x422de3 MOV	0x10(%RBP),%RAX

0x422de7 VMINSD	(%RAX),%XMM0,%XMM0

0x422deb VMOVSD	%XMM0,(%RAX)

0x422def MOV	(%RDI),%ESI

0x422df1 MOV	$0x580220,%RDX

0x422df8 MOV	$0x527430,%EDI

0x422dfd CALL	404170 <__kmpc_end_reduce@plt>

0x422e02 MOV	-0x60(%RBP),%RDI

0x422e06 MOV	(%RDI),%ESI

0x422e08 MOV	$0x527450,%EDI

0x422e0d CALL	4047c0 <__kmpc_barrier@plt>

0x422e12 ADD	$0x1f8,%RSP

0x422e19 POP	%RBX

0x422e1a POP	%R12

0x422e1c POP	%R13

0x422e1e POP	%R14

0x422e20 POP	%R15

0x422e22 POP	%RBP

0x422e23 RET

0x422e24 MOV	0xb0(%RBP),%RAX

0x422e2b MOV	0xa8(%RBP),%RCX

0x422e32 MOV	0x58(%RBP),%RDI

0x422e36 MOVSXD	(%RAX),%R8

0x422e39 MOV	(%RCX),%ECX

0x422e3b SUB	%R8D,%ECX

0x422e3e ADD	%EBX,%ESI

0x422e40 LEA	-0x2(%R15),%EAX

0x422e44 CLTQ

0x422e46 MOV	%RAX,-0x148(%RBP)

0x422e4d MOV	%RCX,-0x198(%RBP)

0x422e54 LEA	0x1(%RCX),%EAX

0x422e57 CMP	$0x2,%EAX

0x422e5a MOV	$0x1,%ECX

0x422e5f CMOVGE	%EAX,%ECX

0x422e62 MOV	%RCX,-0x70(%RBP)

0x422e66 AND	$0x7ffffff8,%ECX

0x422e6c MOV	%RCX,-0x140(%RBP)

0x422e73 MOVSXD	%R12D,%RDX

0x422e76 LEA	-0x2(%RDX),%RAX

0x422e7a MOV	%RAX,-0x118(%RBP)

0x422e81 MOVSXD	%R15D,%RCX

0x422e84 MOV	%R8,-0x120(%RBP)

0x422e8b LEA	(,%R8,8),%RAX

0x422e93 SAL	$0x3,%RDX

0x422e97 SUB	%RDX,%RAX

0x422e9a MOV	$0x3,%R8D

0x422ea0 SUB	%RCX,%R8

0x422ea3 MOV	%R8,-0x138(%RBP)

0x422eaa MOV	$0x18,%R8D

0x422eb0 SUB	%RDX,%R8

0x422eb3 MOV	$0x10,%R9D

0x422eb9 SUB	%RDX,%R9

0x422ebc MOV	$0x2,%EDX

0x422ec1 SUB	%RCX,%RDX

0x422ec4 MOV	%RDX,-0x130(%RBP)

0x422ecb ADD	$-0x2,%RCX

0x422ecf MOV	%RCX,-0x68(%RBP)

0x422ed3 LEA	(%RDI,%RAX,1),%RCX

0x422ed7 ADD	$0x10,%RCX

0x422edb MOV	%RCX,-0xd0(%RBP)

0x422ee2 ADD	%R9,%RDI

0x422ee5 MOV	%RDI,-0x128(%RBP)

0x422eec MOV	0x40(%RBP),%RCX

0x422ef0 LEA	(%RCX,%RAX,1),%RDX

0x422ef4 ADD	$0x10,%RDX

0x422ef8 MOV	%RDX,-0xc8(%RBP)

0x422eff ADD	%R9,%RCX

0x422f02 MOV	%RCX,-0x100(%RBP)

0x422f09 MOV	0x38(%RBP),%RCX

0x422f0d LEA	(%RCX,%RAX,1),%RDX

0x422f11 ADD	$0x10,%RDX

0x422f15 MOV	%RDX,-0xc0(%RBP)

0x422f1c ADD	%R9,%RCX

0x422f1f MOV	%RCX,-0xf8(%RBP)

0x422f26 MOV	0x30(%RBP),%RCX

0x422f2a LEA	(%RCX,%RAX,1),%RDX

0x422f2e ADD	$0x10,%RDX

0x422f32 MOV	%RDX,-0xb8(%RBP)

0x422f39 ADD	%R9,%RCX

0x422f3c MOV	%RCX,-0xf0(%RBP)

0x422f43 MOV	0x28(%RBP),%RCX

0x422f47 LEA	(%RCX,%RAX,1),%RDX

0x422f4b ADD	$0x10,%RDX

0x422f4f MOV	%RDX,-0xb0(%RBP)

0x422f56 ADD	%R9,%RCX

0x422f59 MOV	%RCX,-0xe8(%RBP)

0x422f60 MOV	0x50(%RBP),%RCX

0x422f64 ADD	%RCX,%R9

0x422f67 MOV	%R9,-0x108(%RBP)

0x422f6e ADD	%RAX,%RCX

0x422f71 ADD	$0x10,%RCX

0x422f75 MOV	%RCX,-0x1b8(%RBP)

0x422f7c MOV	0x60(%RBP),%RCX

0x422f80 MOV	0x20(%RBP),%RDX

0x422f84 MOV	0x18(%RBP),%RDI

0x422f88 LEA	0x18(%RDI,%RAX,1),%R9

0x422f8d MOV	%R9,-0xa8(%RBP)

0x422f94 LEA	0x18(%RCX,%RAX,1),%R9

0x422f99 MOV	%R9,-0xa0(%RBP)

0x422fa0 LEA	0x18(%RDX,%RAX,1),%RAX

0x422fa5 MOV	%RAX,-0x98(%RBP)

0x422fac LEA	(%RDI,%R8,1),%RAX

0x422fb0 MOV	%RAX,-0xe0(%RBP)

0x422fb7 LEA	(%RCX,%R8,1),%RAX

0x422fbb MOV	%RAX,-0xd8(%RBP)

0x422fc2 ADD	%RDX,%R8

0x422fc5 MOV	%R8,-0x110(%RBP)

0x422fcc VMOVSD	0xc676c(%RIP),%XMM10

0x422fd4 VMOVDDUP	0xc33cc(%RIP),%XMM9

0x422fdc VMOVDDUP	0xc20cc(%RIP),%XMM1

0x422fe4 VBROADCASTSD	0xc20c3(%RIP),%YMM2

0x422fed XOR	%EDX,%EDX

0x422fef MOV	%ESI,%ECX

0x422ff1 MOV	%RSI,-0x1a0(%RBP)

0x422ff8 JMP	423021

0x422ffa NOPW	(%RAX,%RAX,1)

(191) 0x423000 MOV	-0x1b0(%RBP),%RDX

(191) 0x423007 LEA	0x1(%RDX),%EAX

(191) 0x42300a MOV	-0x4c(%RBP),%ECX

(191) 0x42300d INC	%ECX

(191) 0x42300f CMP	-0x48(%RBP),%EDX

(191) 0x423012 MOV	%EAX,%EDX

(191) 0x423014 MOV	-0x1a0(%RBP),%RSI

(191) 0x42301b JE	422d84

(191) 0x423021 CMPL	$0,-0x198(%RBP)

(191) 0x423028 MOV	%ECX,-0x4c(%RBP)

(191) 0x42302b MOV	%RDX,-0x1b0(%RBP)

(191) 0x423032 JS	423000

(191) 0x423034 MOVSXD	%ECX,%RBX

(191) 0x423037 MOV	-0x138(%RBP),%RAX

(191) 0x42303e LEA	(%RAX,%RBX,1),%R10

(191) 0x423042 ADD	-0x130(%RBP),%RBX

(191) 0x423049 LEA	(%RSI,%RDX,1),%EAX

(191) 0x42304c MOVSXD	%EAX,%R8

(191) 0x42304f MOV	%R8,%RAX

(191) 0x423052 SUB	-0x148(%RBP),%RAX

(191) 0x423059 MOV	0x48(%RBP),%RCX

(191) 0x42305d VMOVSD	(%RCX,%RAX,8),%XMM18

(191) 0x423064 MOV	0xb8(%RBP),%RAX

(191) 0x42306b MOV	(%RAX),%R12

(191) 0x42306e MOV	0xc0(%RBP),%RAX

(191) 0x423075 MOV	(%RAX),%RDX

(191) 0x423078 MOV	0x90(%RBP),%RAX

(191) 0x42307f VMOVSD	(%RAX),%XMM19

(191) 0x423085 MOV	0x80(%RBP),%RAX

(191) 0x42308c VMOVSD	(%RAX),%XMM20

(191) 0x423092 MOV	0xc8(%RBP),%RAX

(191) 0x423099 MOV	(%RAX),%R9

(191) 0x42309c MOV	0xd0(%RBP),%RAX

(191) 0x4230a3 MOV	(%RAX),%R15

(191) 0x4230a6 MOV	0xd8(%RBP),%RAX

(191) 0x4230ad MOV	(%RAX),%RDI

(191) 0x4230b0 MOV	0x78(%RBP),%RAX

(191) 0x4230b4 VMOVSD	(%RAX),%XMM21

(191) 0x4230ba MOV	0xe0(%RBP),%RAX

(191) 0x4230c1 MOV	(%RAX),%R14

(191) 0x4230c4 MOV	0xe8(%RBP),%RAX

(191) 0x4230cb MOV	(%RAX),%R11

(191) 0x4230ce MOV	0xf0(%RBP),%RAX

(191) 0x4230d5 MOV	(%RAX),%R13

(191) 0x4230d8 MOV	0x70(%RBP),%RAX

(191) 0x4230dc VMOVSD	(%RAX),%XMM22

(191) 0x4230e2 VXORPD	%XMM9,%XMM19,%XMM23

(191) 0x4230e8 MOV	-0x140(%RBP),%RSI

(191) 0x4230ef TEST	%RSI,%RSI

(191) 0x4230f2 MOV	%R12,-0x1a8(%RBP)

(191) 0x4230f9 MOV	%R9,-0x88(%RBP)

(191) 0x423100 JE	423610

(191) 0x423106 VBROADCASTSD	%XMM10,%YMM10

(191) 0x42310b SUB	-0x68(%RBP),%R8

(191) 0x42310f VMOVAPD	%XMM19,-0x210(%RBP)

(191) 0x423116 VBROADCASTSD	%XMM19,%YMM11

(191) 0x42311c VMOVAPD	%XMM18,-0x220(%RBP)

(191) 0x423123 VBROADCASTSD	%XMM18,%YMM12

(191) 0x423129 VMOVAPD	%XMM20,-0x200(%RBP)

(191) 0x423130 VBROADCASTSD	%XMM20,%YMM13

(191) 0x423136 LEA	0x1(%R8),%RCX

(191) 0x42313a MOV	%R15,%RAX

(191) 0x42313d IMUL	%RCX,%RAX

(191) 0x423141 MOV	%RAX,-0x38(%RBP)

(191) 0x423145 MOV	%R15,%RAX

(191) 0x423148 IMUL	%R8,%RAX

(191) 0x42314c MOV	%RAX,-0x80(%RBP)

(191) 0x423150 MOV	%RDI,%RAX

(191) 0x423153 IMUL	%R8,%RAX

(191) 0x423157 MOV	%RAX,-0x158(%RBP)

(191) 0x42315e VMOVAPD	%XMM21,-0x1f0(%RBP)

(191) 0x423165 VBROADCASTSD	%XMM21,%YMM14

(191) 0x42316b IMUL	%R11,%R8

(191) 0x42316f MOV	%R8,-0x150(%RBP)

(191) 0x423176 IMUL	%R11,%RCX

(191) 0x42317a MOV	%RCX,-0x78(%RBP)

(191) 0x42317e VMOVAPD	%XMM22,-0x1e0(%RBP)

(191) 0x423185 VBROADCASTSD	%XMM22,%YMM15

(191) 0x42318b VMOVAPD	%XMM23,-0x1d0(%RBP)

(191) 0x423192 VBROADCASTSD	%XMM23,%YMM16

(191) 0x423198 MOV	%R11,%R8

(191) 0x42319b IMUL	%R10,%R8

(191) 0x42319f MOV	-0xa8(%RBP),%RAX

(191) 0x4231a6 ADD	%RAX,%R8

(191) 0x4231a9 MOV	%R11,-0x160(%RBP)

(191) 0x4231b0 IMUL	%RBX,%R11

(191) 0x4231b4 ADD	%RAX,%R11

(191) 0x4231b7 MOV	%RDI,-0x170(%RBP)

(191) 0x4231be MOV	%RDI,%RCX

(191) 0x4231c1 IMUL	%RBX,%RCX

(191) 0x4231c5 ADD	-0xa0(%RBP),%RCX

(191) 0x4231cc MOV	%R15,%RDI

(191) 0x4231cf IMUL	%RBX,%RDI

(191) 0x4231d3 MOV	-0x98(%RBP),%RAX

(191) 0x4231da ADD	%RAX,%RDI

(191) 0x4231dd MOV	%R15,-0x178(%RBP)

(191) 0x4231e4 MOV	%RDX,%R9

(191) 0x4231e7 MOV	%R15,%RDX

(191) 0x4231ea IMUL	%R10,%RDX

(191) 0x4231ee ADD	%RAX,%RDX

(191) 0x4231f1 MOV	%R13,%R15

(191) 0x4231f4 MOV	%R10,-0x190(%RBP)

(191) 0x4231fb IMUL	%R10,%R13

(191) 0x4231ff MOV	-0xd0(%RBP),%RAX

(191) 0x423206 ADD	%RAX,%R13

(191) 0x423209 MOV	%R15,-0x168(%RBP)

(191) 0x423210 IMUL	%RBX,%R15

(191) 0x423214 ADD	%RAX,%R15

(191) 0x423217 MOV	%R14,-0x40(%RBP)

(191) 0x42321b IMUL	%RBX,%R14

(191) 0x42321f ADD	-0xc8(%RBP),%R14

(191) 0x423226 MOV	-0x88(%RBP),%RAX

(191) 0x42322d IMUL	%RBX,%RAX

(191) 0x423231 ADD	-0xc0(%RBP),%RAX

(191) 0x423238 MOV	%R9,-0x180(%RBP)

(191) 0x42323f IMUL	%RBX,%R9

(191) 0x423243 ADD	-0xb8(%RBP),%R9

(191) 0x42324a MOV	%RBX,-0x188(%RBP)

(191) 0x423251 IMUL	%RBX,%R12

(191) 0x423255 ADD	-0xb0(%RBP),%R12

(191) 0x42325c VMOVAPD	%YMM10,%YMM17

(191) 0x423262 XOR	%R10D,%R10D

(191) 0x423265 JMP	4233dc

0x42326a NOPW	(%RAX,%RAX,1)

  (193) 0x423270 MOV	-0x1b8(%RBP),%RBX

  (193) 0x423277 VMOVUPD	(%RBX,%R10,8),%YMM4

  (193) 0x42327d VMOVUPD	0x20(%RBX,%R10,8),%YMM6

  (193) 0x423284 VMOVUPD	(%R12,%R10,8),%YMM7

  (193) 0x42328a VMOVUPD	0x20(%R12,%R10,8),%YMM8

  (193) 0x423291 VMOVUPD	(%R9,%R10,8),%YMM9

  (193) 0x423297 VMOVUPD	0x20(%R9,%R10,8),%YMM5

  (193) 0x42329e VADDPD	%YMM9,%YMM9,%YMM9

  (193) 0x4232a3 VADDPD	%YMM5,%YMM5,%YMM5

  (193) 0x4232a7 VDIVPD	0x20(%RAX,%R10,8),%YMM5,%YMM5

  (193) 0x4232ae VDIVPD	(%RAX,%R10,8),%YMM9,%YMM9

  (193) 0x4232b4 VFMADD231PD	%YMM7,%YMM7,%YMM9

  (193) 0x4232b9 VFMADD231PD	%YMM8,%YMM8,%YMM5

  (193) 0x4232be VSQRTPD	%YMM5,%YMM5

  (193) 0x4232c2 VSQRTPD	%YMM9,%YMM7

  (193) 0x4232c7 VMAXPD	%YMM11,%YMM7,%YMM7

  (193) 0x4232cc VMAXPD	%YMM11,%YMM5,%YMM5

  (193) 0x4232d1 VMINPD	%YMM12,%YMM6,%YMM6

  (193) 0x4232d6 VMINPD	%YMM12,%YMM4,%YMM4

  (193) 0x4232db VMULPD	%YMM4,%YMM13,%YMM4

  (193) 0x4232df VDIVPD	%YMM7,%YMM4,%YMM4

  (193) 0x4232e3 VMULPD	%YMM6,%YMM13,%YMM6

  (193) 0x4232e7 VDIVPD	%YMM5,%YMM6,%YMM5

  (193) 0x4232eb VMULPD	%YMM14,%YMM31,%YMM6

  (193) 0x4232f1 VMULPD	%YMM14,%YMM18,%YMM7

  (193) 0x4232f7 VANDPD	%YMM2,%YMM24,%YMM8

  (193) 0x4232fd VANDPD	%YMM2,%YMM20,%YMM9

  (193) 0x423303 VANDPD	%YMM2,%YMM28,%YMM20

  (193) 0x423309 VANDPD	%YMM2,%YMM25,%YMM24

  (193) 0x42330f VMULPD	%YMM11,%YMM26,%YMM25

  (193) 0x423315 VMULPD	%YMM11,%YMM27,%YMM26

  (193) 0x42331b VMAXPD	%YMM26,%YMM24,%YMM24

  (193) 0x423321 VMAXPD	%YMM24,%YMM8,%YMM8

  (193) 0x423327 VDIVPD	%YMM8,%YMM7,%YMM7

  (193) 0x42332c VMAXPD	%YMM25,%YMM20,%YMM8

  (193) 0x423332 VMAXPD	%YMM8,%YMM9,%YMM8

  (193) 0x423337 VDIVPD	%YMM8,%YMM6,%YMM6

  (193) 0x42333c VMULPD	%YMM15,%YMM31,%YMM8

  (193) 0x423342 VMULPD	%YMM15,%YMM18,%YMM9

  (193) 0x423348 VANDPD	%YMM2,%YMM21,%YMM18

  (193) 0x42334e VANDPD	%YMM2,%YMM22,%YMM20

  (193) 0x423354 VANDPD	%YMM2,%YMM30,%YMM21

  (193) 0x42335a VANDPD	%YMM2,%YMM29,%YMM22

  (193) 0x423360 VMAXPD	%YMM26,%YMM22,%YMM22

  (193) 0x423366 VMAXPD	%YMM22,%YMM18,%YMM18

  (193) 0x42336c VDIVPD	%YMM18,%YMM9,%YMM9

  (193) 0x423372 VMAXPD	%YMM25,%YMM21,%YMM18

  (193) 0x423378 VMAXPD	%YMM18,%YMM20,%YMM18

  (193) 0x42337e VDIVPD	%YMM18,%YMM8,%YMM8

  (193) 0x423384 VBROADCASTSD	%XMM3,%YMM3

  (193) 0x423389 VXORPD	0xc3015(%RIP){1to4},%YMM3,%YMM3

  (193) 0x423393 VBROADCASTSD	%XMM0,%YMM0

  (193) 0x423398 VMOVAPD	%YMM0,%YMM18

  (193) 0x42339e VDIVPD	%YMM23,%YMM3,%YMM18{%K2}

  (193) 0x4233a4 VMINPD	%YMM18,%YMM9,%YMM9

  (193) 0x4233aa VMINPD	%YMM9,%YMM7,%YMM7

  (193) 0x4233af VMINPD	%YMM7,%YMM5,%YMM5

  (193) 0x4233b3 VMINPD	%YMM5,%YMM17,%YMM17

  (193) 0x4233b9 VDIVPD	%YMM19,%YMM3,%YMM0{%K1}

  (193) 0x4233bf VMINPD	%YMM0,%YMM8,%YMM0

  (193) 0x4233c3 VMINPD	%YMM0,%YMM6,%YMM0

  (193) 0x4233c7 VMINPD	%YMM0,%YMM4,%YMM0

  (193) 0x4233cb VMINPD	%YMM0,%YMM10,%YMM10

  (193) 0x4233cf ADD	$0x8,%R10

  (193) 0x4233d3 CMP	%RSI,%R10

  (193) 0x4233d6 JAE	423530

  (193) 0x4233dc VMOVUPD	-0x8(%RDX,%R10,8),%YMM0

  (193) 0x4233e3 VMOVUPD	(%RDX,%R10,8),%YMM3

  (193) 0x4233e9 VMOVUPD	0x18(%RDX,%R10,8),%YMM18

  (193) 0x4233f4 VMOVUPD	0x20(%RDX,%R10,8),%YMM19

  (193) 0x4233fc VADDPD	0x18(%RDI,%R10,8),%YMM18,%YMM18

  (193) 0x423407 VADDPD	-0x8(%RDI,%R10,8),%YMM0,%YMM0

  (193) 0x42340e VMULPD	-0x8(%RCX,%R10,8),%YMM0,%YMM20

  (193) 0x423419 VMULPD	0x18(%RCX,%R10,8),%YMM18,%YMM24

  (193) 0x423424 VADDPD	(%RDI,%R10,8),%YMM3,%YMM0

  (193) 0x42342a VADDPD	0x20(%RDI,%R10,8),%YMM19,%YMM3

  (193) 0x423432 VMULPD	0x20(%RCX,%R10,8),%YMM3,%YMM25

  (193) 0x42343a VMULPD	(%RCX,%R10,8),%YMM0,%YMM28

  (193) 0x423441 VMOVUPD	(%R14,%R10,8),%YMM26

  (193) 0x423448 VMOVUPD	0x20(%R14,%R10,8),%YMM27

  (193) 0x423450 VADDPD	%YMM27,%YMM27,%YMM18

  (193) 0x423456 VMOVUPD	(%R11,%R10,8),%YMM0

  (193) 0x42345c VMOVUPD	0x20(%R11,%R10,8),%YMM3

  (193) 0x423463 VADDPD	-0x8(%R11,%R10,8),%YMM0,%YMM0

  (193) 0x42346a VADDPD	0x18(%R11,%R10,8),%YMM3,%YMM3

  (193) 0x423471 VMULPD	0x20(%R15,%R10,8),%YMM3,%YMM21

  (193) 0x423479 VMULPD	(%R15,%R10,8),%YMM0,%YMM22

  (193) 0x423480 VMOVUPD	(%R8,%R10,8),%YMM0

  (193) 0x423486 VMOVUPD	0x20(%R8,%R10,8),%YMM3

  (193) 0x42348d VADDPD	-0x8(%R8,%R10,8),%YMM0,%YMM0

  (193) 0x423494 VADDPD	0x18(%R8,%R10,8),%YMM3,%YMM3

  (193) 0x42349b VADDPD	%YMM26,%YMM26,%YMM31

  (193) 0x4234a1 VMULPD	0x20(%R13,%R10,8),%YMM3,%YMM29

  (193) 0x4234a9 VMULPD	(%R13,%R10,8),%YMM0,%YMM30

  (193) 0x4234b1 VADDPD	%YMM22,%YMM20,%YMM0

  (193) 0x4234b7 VADDPD	%YMM21,%YMM24,%YMM3

  (193) 0x4234bd VSUBPD	%YMM3,%YMM25,%YMM3

  (193) 0x4234c3 VSUBPD	%YMM0,%YMM28,%YMM0

  (193) 0x4234c9 VADDPD	%YMM30,%YMM0,%YMM0

  (193) 0x4234cf VADDPD	%YMM29,%YMM3,%YMM3

  (193) 0x4234d5 VDIVPD	%YMM18,%YMM3,%YMM23

  (193) 0x4234db VDIVPD	%YMM31,%YMM0,%YMM19

  (193) 0x4234e1 VCMPPD	$0x1,%YMM16,%YMM19,%K1

  (193) 0x4234e8 VCMPPD	$0x1,%YMM16,%YMM23,%K2

  (193) 0x4234ef KSHIFTLB	$0x4,%K2,%K0

  (193) 0x4234f5 KORB	%K0,%K1,%K0

  (193) 0x4234f9 KORTESTB	%K0,%K0

  (193) 0x4234fd JB	42350a

  (193) 0x4234ff MOV	0x88(%RBP),%RBX

  (193) 0x423506 VMOVSD	(%RBX),%XMM0

  (193) 0x42350a KORTESTB	%K2,%K1

  (193) 0x42350e JE	423270

  (193) 0x423514 MOV	0x68(%RBP),%RBX

  (193) 0x423518 VMOVSD	(%RBX),%XMM3

  (193) 0x42351c JMP	423270

0x423521 NOPW	%CS:(%RAX,%RAX,1)

(191) 0x423530 VMINPD	%YMM10,%YMM17,%YMM0

(191) 0x423536 VCMPPD	$0x3,%YMM10,%YMM10,%K1

(191) 0x42353d VMOVAPD	%YMM17,%YMM0{%K1}

(191) 0x423543 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM3

(191) 0x423548 VMINSD	%XMM0,%XMM3,%XMM4

(191) 0x42354c VCMPSD	$0x3,%XMM0,%XMM0,%K1

(191) 0x423553 VMOVSD	%XMM3,%XMM4,%XMM4{%K1}

(191) 0x423559 VCMPSD	$0x3,%XMM4,%XMM4,%K1

(191) 0x423560 VEXTRACTF128	$0x1,%YMM0,%XMM0

(191) 0x423566 VMINSD	%XMM4,%XMM0,%XMM3

(191) 0x42356a VMOVSD	%XMM0,%XMM3,%XMM3{%K1}

(191) 0x423570 VCMPSD	$0x3,%XMM3,%XMM3,%K1

(191) 0x423577 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM0

(191) 0x42357c VMINSD	%XMM3,%XMM0,%XMM10

(191) 0x423580 VMOVSD	%XMM0,%XMM10,%XMM10{%K1}

(191) 0x423586 MOV	%RSI,%RAX

(191) 0x423589 CMP	-0x70(%RBP),%ESI

(191) 0x42358c VMOVDDUP	0xc2e14(%RIP),%XMM9

(191) 0x423594 VMOVAPD	-0x220(%RBP),%XMM18

(191) 0x42359b VMOVAPD	-0x210(%RBP),%XMM19

(191) 0x4235a2 VMOVAPD	-0x200(%RBP),%XMM20

(191) 0x4235a9 VMOVAPD	-0x1f0(%RBP),%XMM21

(191) 0x4235b0 VMOVAPD	-0x1e0(%RBP),%XMM22

(191) 0x4235b7 VMOVAPD	-0x1d0(%RBP),%XMM23

(191) 0x4235be MOV	-0x190(%RBP),%R10

(191) 0x4235c5 MOV	-0x188(%RBP),%RBX

(191) 0x4235cc MOV	-0x180(%RBP),%RDX

(191) 0x4235d3 MOV	-0x178(%RBP),%R15

(191) 0x4235da MOV	-0x40(%RBP),%R14

(191) 0x4235de MOV	-0x170(%RBP),%RDI

(191) 0x4235e5 MOV	-0x168(%RBP),%R13

(191) 0x4235ec MOV	-0x160(%RBP),%R11

(191) 0x4235f3 MOV	-0x158(%RBP),%R8

(191) 0x4235fa MOV	-0x150(%RBP),%R12

(191) 0x423601 JE	423000

(191) 0x423607 JMP	423643

0x423609 NOPL	(%RAX)

(191) 0x423610 SUB	-0x68(%RBP),%R8

(191) 0x423614 MOV	%R11,%R12

(191) 0x423617 IMUL	%R8,%R12

(191) 0x42361b LEA	0x1(%R8),%RAX

(191) 0x42361f MOV	%R11,%RCX

(191) 0x423622 IMUL	%RAX,%RCX

(191) 0x423626 MOV	%RCX,-0x78(%RBP)

(191) 0x42362a MOV	%R15,%RCX

(191) 0x42362d IMUL	%R8,%RCX

(191) 0x423631 MOV	%RCX,-0x80(%RBP)

(191) 0x423635 IMUL	%R15,%RAX

(191) 0x423639 MOV	%RAX,-0x38(%RBP)

(191) 0x42363d IMUL	%RDI,%R8

(191) 0x423641 XOR	%EAX,%EAX

(191) 0x423643 MOV	0x18(%RBP),%RCX

(191) 0x423647 MOV	%RDX,%R9

(191) 0x42364a MOV	%RCX,%RDX

(191) 0x42364d ADD	%RCX,%R12

(191) 0x423650 MOV	-0x120(%RBP),%RCX

(191) 0x423657 LEA	(%RCX,%RAX,1),%RSI

(191) 0x42365b MOV	%RSI,%RCX

(191) 0x42365e SUB	-0x118(%RBP),%RCX

(191) 0x423665 VMOVSD	(%R12,%RCX,8),%XMM11

(191) 0x42366b MOV	-0x78(%RBP),%R12

(191) 0x42366f ADD	%RDX,%R12

(191) 0x423672 VMOVSD	(%R12,%RCX,8),%XMM12

(191) 0x423678 MOV	0x20(%RBP),%RDX

(191) 0x42367c MOV	-0x38(%RBP),%R12

(191) 0x423680 ADD	%RDX,%R12

(191) 0x423683 VMOVSD	(%R12,%RCX,8),%XMM0

(191) 0x423689 MOV	-0x80(%RBP),%R12

(191) 0x42368d ADD	%RDX,%R12

(191) 0x423690 VADDSD	(%R12,%RCX,8),%XMM0,%XMM0

(191) 0x423696 ADD	0x60(%RBP),%R8

(191) 0x42369a VMULSD	(%R8,%RCX,8),%XMM0,%XMM13

(191) 0x4236a0 MOV	-0x70(%RBP),%RCX

(191) 0x4236a4 SUB	%RAX,%RCX

(191) 0x4236a7 MOV	%RCX,-0x38(%RBP)

(191) 0x4236ab MOV	%R11,%RAX

(191) 0x4236ae IMUL	%R10,%RAX

(191) 0x4236b2 IMUL	%RBX,%R11

(191) 0x4236b6 IMUL	%RBX,%RDI

(191) 0x4236ba MOV	%R15,%R8

(191) 0x4236bd IMUL	%R10,%R8

(191) 0x4236c1 IMUL	%RBX,%R15

(191) 0x4236c5 IMUL	%R13,%R10

(191) 0x4236c9 IMUL	%RBX,%R13

(191) 0x4236cd IMUL	%RBX,%R14

(191) 0x4236d1 MOV	%R14,-0x40(%RBP)

(191) 0x4236d5 MOV	-0x88(%RBP),%R12

(191) 0x4236dc IMUL	%RBX,%R12

(191) 0x4236e0 IMUL	%RBX,%R9

(191) 0x4236e4 MOV	%R13,%R14

(191) 0x4236e7 MOV	-0x1a8(%RBP),%R13

(191) 0x4236ee IMUL	%RBX,%R13

(191) 0x4236f2 LEA	(%RAX,%RSI,8),%RAX

(191) 0x4236f6 LEA	(%R11,%RSI,8),%RDX

(191) 0x4236fa LEA	(%RDI,%RSI,8),%RDI

(191) 0x4236fe LEA	(%R8,%RSI,8),%R8

(191) 0x423702 MOV	%R9,%RCX

(191) 0x423705 LEA	(%R15,%RSI,8),%R9

(191) 0x423709 LEA	(%R10,%RSI,8),%R10

(191) 0x42370d LEA	(%R14,%RSI,8),%R11

(191) 0x423711 MOV	-0x40(%RBP),%RBX

(191) 0x423715 LEA	(%RBX,%RSI,8),%RBX

(191) 0x423719 LEA	(%R12,%RSI,8),%R14

(191) 0x42371d LEA	(%RCX,%RSI,8),%R15

(191) 0x423721 LEA	(%R13,%RSI,8),%R12

(191) 0x423726 MOV	-0x108(%RBP),%R13

(191) 0x42372d LEA	(%R13,%RSI,8),%R13

(191) 0x423732 MOV	-0xe0(%RBP),%RSI

(191) 0x423739 ADD	%RSI,%RAX

(191) 0x42373c ADD	%RSI,%RDX

(191) 0x42373f ADD	-0xd8(%RBP),%RDI

(191) 0x423746 MOV	-0x110(%RBP),%RSI

(191) 0x42374d ADD	%RSI,%R8

(191) 0x423750 ADD	%RSI,%R9

(191) 0x423753 MOV	-0x128(%RBP),%RSI

(191) 0x42375a ADD	%RSI,%R10

(191) 0x42375d ADD	%RSI,%R11

(191) 0x423760 ADD	-0x100(%RBP),%RBX

(191) 0x423767 ADD	-0xf8(%RBP),%R14

(191) 0x42376e ADD	-0xf0(%RBP),%R15

(191) 0x423775 ADD	-0xe8(%RBP),%R12

(191) 0x42377c XOR	%ESI,%ESI

(191) 0x42377e JMP	423836

0x423783 NOPW	%CS:(%RAX,%RAX,1)

  (192) 0x423790 MOV	0x88(%RBP),%RCX

  (192) 0x423797 VMOVSD	(%RCX),%XMM17

  (192) 0x42379d VMOVSD	(%R13,%RSI,8),%XMM4

  (192) 0x4237a4 VMOVSD	(%R12,%RSI,8),%XMM5

  (192) 0x4237aa VMOVSD	(%R15,%RSI,8),%XMM6

  (192) 0x4237b0 VADDSD	%XMM6,%XMM6,%XMM6

  (192) 0x4237b4 VDIVSD	(%R14,%RSI,8),%XMM6,%XMM6

  (192) 0x4237ba VFMADD231SD	%XMM5,%XMM5,%XMM6

  (192) 0x4237bf VSQRTSD	%XMM6,%XMM6,%XMM5

  (192) 0x4237c3 VMAXSD	%XMM19,%XMM5,%XMM5

  (192) 0x4237c9 VMINSD	%XMM18,%XMM4,%XMM4

  (192) 0x4237cf VMULSD	%XMM4,%XMM20,%XMM4

  (192) 0x4237d5 VDIVSD	%XMM5,%XMM4,%XMM4

  (192) 0x4237d9 VMULSD	%XMM21,%XMM16,%XMM5

  (192) 0x4237df VANDPD	%XMM1,%XMM13,%XMM6

  (192) 0x4237e3 VANDPD	%XMM1,%XMM0,%XMM7

  (192) 0x4237e7 VMULSD	%XMM19,%XMM3,%XMM3

  (192) 0x4237ed VMAXSD	%XMM3,%XMM7,%XMM7

  (192) 0x4237f1 VMAXSD	%XMM7,%XMM6,%XMM6

  (192) 0x4237f5 VDIVSD	%XMM6,%XMM5,%XMM5

  (192) 0x4237f9 VMULSD	%XMM22,%XMM16,%XMM6

  (192) 0x4237ff VANDPD	%XMM1,%XMM14,%XMM7

  (192) 0x423803 VANDPD	%XMM1,%XMM15,%XMM8

  (192) 0x423807 VMAXSD	%XMM3,%XMM8,%XMM3

  (192) 0x42380b VMAXSD	%XMM3,%XMM7,%XMM3

  (192) 0x42380f VDIVSD	%XMM3,%XMM6,%XMM3

  (192) 0x423813 VMINSD	%XMM17,%XMM3,%XMM3

  (192) 0x423819 VMINSD	%XMM3,%XMM5,%XMM3

  (192) 0x42381d VMINSD	%XMM3,%XMM4,%XMM3

  (192) 0x423821 VMINSD	%XMM3,%XMM10,%XMM10

  (192) 0x423825 INC	%RSI

  (192) 0x423828 VMOVAPD	%XMM0,%XMM13

  (192) 0x42382c CMP	%RSI,-0x38(%RBP)

  (192) 0x423830 JE	423000

  (192) 0x423836 VMOVSD	(%R8,%RSI,8),%XMM0

  (192) 0x42383c VADDSD	(%R9,%RSI,8),%XMM0,%XMM0

  (192) 0x423842 VMULSD	(%RDI,%RSI,8),%XMM0,%XMM0

  (192) 0x423847 VMOVSD	(%RBX,%RSI,8),%XMM3

  (192) 0x42384c VMOVAPD	%XMM11,%XMM4

  (192) 0x423850 VMOVSD	(%RDX,%RSI,8),%XMM11

  (192) 0x423855 VADDSD	%XMM4,%XMM11,%XMM4

  (192) 0x423859 VMULSD	(%R11,%RSI,8),%XMM4,%XMM14

  (192) 0x42385f VMOVAPD	%XMM12,%XMM4

  (192) 0x423863 VMOVSD	(%RAX,%RSI,8),%XMM12

  (192) 0x423868 VADDSD	%XMM4,%XMM12,%XMM4

  (192) 0x42386c VMULSD	(%R10,%RSI,8),%XMM4,%XMM15

  (192) 0x423872 VADDSD	%XMM3,%XMM3,%XMM16

  (192) 0x423878 VADDSD	%XMM14,%XMM13,%XMM4

  (192) 0x42387d VSUBSD	%XMM4,%XMM0,%XMM4

  (192) 0x423881 VADDSD	%XMM4,%XMM15,%XMM4

  (192) 0x423885 VDIVSD	%XMM16,%XMM4,%XMM17

  (192) 0x42388b VUCOMISD	%XMM17,%XMM23

  (192) 0x423891 JBE	423790

  (192) 0x423897 MOV	0x68(%RBP),%RCX

  (192) 0x42389b VMOVSD	(%RCX),%XMM4

  (192) 0x42389f VXORPD	%XMM4,%XMM9,%XMM4

  (192) 0x4238a3 VDIVSD	%XMM17,%XMM4,%XMM17

  (192) 0x4238a9 JMP	42379d

0x4238ae XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	calc_dt_kernel.f90:89-133
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-133.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.17 to 5.67 cycles (5.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:93
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:97

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 212 bytes (26 double precision FP elements). The binary function is storing 272 bytes (34 double precision FP elements).

General properties

nb instructions	181
nb uops	187
loop length	827
used x86 registers	14
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	0
nb stack references	50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.17 cycles
front end	31.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.70	10.60	13.00	13.00	26.00	10.67	10.50	26.00	26.00	26.00	10.53	13.00
cycles	10.70	12.17	13.00	13.00	26.00	10.67	10.50	26.00	26.00	26.00	10.53	13.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	31.17
Dispatch	26.00
Overall L1	31.17

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	10%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	9%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.17 cycles. At this rate:

3% of peak load performance is reached (6.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 31.17 to 26.00 cycles (1.20x speedup).

ASM code

In the binary file, the address of the function is: 422cf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0xa0(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,-0x54(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 422e06 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x116>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x54(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5273d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JAE 422e24 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x134>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0xc69bc(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x5273f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x580220,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x90(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x527410,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x422ce0,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x8,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4045b0 <__kmpc_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 422e06 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x116>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x90(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMINSD (%RAX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x580220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x527430,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404170 <__kmpc_end_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x60(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527450,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4047c0 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R8D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EBX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x2(%R15),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %RAX,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RCX),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVGE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffff8,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R12D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA -0x2(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R15D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R8,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R8,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SUB %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x18,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x10,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $-0x2,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RAX,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R9,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x1b8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x18(%RDI,%RAX,1),%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x18(%RCX,%RAX,1),%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x18(%RDX,%RAX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0xc676c(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xc33cc(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xc20cc(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VBROADCASTSD 0xc20c3(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 423021 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x331>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	calc_dt_kernel.f90:89-133
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.17 to 5.67 cycles (5.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:93
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:97

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	181
nb uops	187
loop length	827
used x86 registers	14
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	0
nb stack references	50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.17 cycles
front end	31.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.70	10.60	13.00	13.00	26.00	10.67	10.50	26.00	26.00	26.00	10.53	13.00
cycles	10.70	12.17	13.00	13.00	26.00	10.67	10.50	26.00	26.00	26.00	10.53	13.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	31.17
Dispatch	26.00
Overall L1	31.17

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	10%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	9%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.17 cycles. At this rate:

3% of peak load performance is reached (6.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 422cf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0xa0(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,-0x54(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 422e06 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x116>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x54(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5273d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JAE 422e24 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x134>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0xc69bc(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x5273f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x580220,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x90(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x527410,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x422ce0,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x8,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4045b0 <__kmpc_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 422e06 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x116>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x90(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMINSD (%RAX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x580220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x527430,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404170 <__kmpc_end_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x60(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x527450,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4047c0 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R8D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EBX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x2(%R15),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %RAX,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RCX),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVGE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffff8,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R12D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA -0x2(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R15D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R8,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R8,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SUB %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x18,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x10,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $-0x2,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RAX,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R9,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x1b8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x18(%RDI,%RAX,1),%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x18(%RCX,%RAX,1),%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x18(%RDX,%RAX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0xc676c(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xc33cc(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xc20cc(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VBROADCASTSD 0xc20c3(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 423021 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x331>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2–	3.27	1.22
▼Loop 191 - calc_dt_kernel.f90:92-129 - exec–	0.00	0.01
○Loop 193 - calc_dt_kernel.f90:94-129 - exec	3.27	1.22
○Loop 192 - calc_dt_kernel.f90:94-129 - exec	0.00	0.00

Report Configuration

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Execution units bottlenecks

512-bits vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

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Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

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Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code