OV - exec - Function accelerate_kernel_module_mp_accelerate_kernel

	Function: accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2	Module: exec	Source: accelerate_kernel.f90:57-79	Coverage (incl. loops): 5.41% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 57 - 79

--------------------------------------------------------------------------------

57:     !$OMP PARALLEL

58:

59:     !$OMP DO PRIVATE(j,k,stepbymass_s)

60:     DO k=y_min,y_max+1

61:     !$OMP SIMD

62:       DO j=x_min,x_max+1

63:         stepbymass_s=halfdt/((density0(j-1,k-1)*volume(j-1,k-1)  &

64:           +density0(j  ,k-1)*volume(j  ,k-1)  &

65:           +density0(j  ,k  )*volume(j  ,k  )  &

66:           +density0(j-1,k  )*volume(j-1,k  )) &

67:           *0.25_8)

68:

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

77:       ENDDO

78:     ENDDO

79:   !$OMP END DO

0x414840 PUSH	%RBP

0x414841 MOV	%RSP,%RBP

0x414844 PUSH	%R15

0x414846 PUSH	%R14

0x414848 PUSH	%R13

0x41484a PUSH	%R12

0x41484c PUSH	%RBX

0x41484d SUB	$0x208,%RSP

0x414854 MOV	%R8,-0x30(%RBP)

0x414858 MOV	0xd0(%RBP),%RAX

0x41485f MOV	%RAX,-0x210(%RBP)

0x414866 MOV	0xc8(%RBP),%RAX

0x41486d MOV	%RAX,-0x208(%RBP)

0x414874 MOV	0xc0(%RBP),%RAX

0x41487b MOV	%RAX,-0x200(%RBP)

0x414882 MOV	0xb8(%RBP),%RAX

0x414889 MOV	%RAX,-0x1f8(%RBP)

0x414890 MOV	0xb0(%RBP),%RAX

0x414897 MOV	%RAX,-0x1f0(%RBP)

0x41489e MOV	0xa8(%RBP),%RAX

0x4148a5 MOV	%RAX,-0x1e8(%RBP)

0x4148ac MOV	0xa0(%RBP),%RAX

0x4148b3 MOV	%RAX,-0x1e0(%RBP)

0x4148ba MOV	0x98(%RBP),%RAX

0x4148c1 MOV	%RAX,-0x1d8(%RBP)

0x4148c8 MOV	0x70(%RBP),%R14D

0x4148cc MOV	0x68(%RBP),%EAX

0x4148cf SUB	%R14D,%EAX

0x4148d2 INC	%EAX

0x4148d4 MOV	0x90(%RBP),%RCX

0x4148db MOV	%RCX,-0x1d0(%RBP)

0x4148e2 MOV	0x88(%RBP),%RCX

0x4148e9 MOV	%RCX,-0x1c8(%RBP)

0x4148f0 MOV	0x80(%RBP),%R12

0x4148f7 MOV	0x78(%RBP),%R15

0x4148fb MOV	0x60(%RBP),%RCX

0x4148ff MOV	%RCX,-0xc8(%RBP)

0x414906 MOV	0x58(%RBP),%RCX

0x41490a MOV	%RCX,-0xc0(%RBP)

0x414911 MOV	0x50(%RBP),%RCX

0x414915 MOV	%RCX,-0xb8(%RBP)

0x41491c MOV	0x48(%RBP),%RCX

0x414920 MOV	%RCX,-0xb0(%RBP)

0x414927 MOV	0x40(%RBP),%RCX

0x41492b MOV	%RCX,-0xa8(%RBP)

0x414932 MOV	0x38(%RBP),%RCX

0x414936 MOV	%RCX,-0xa0(%RBP)

0x41493d MOV	0x30(%RBP),%RCX

0x414941 MOV	%RCX,-0x98(%RBP)

0x414948 MOV	0x28(%RBP),%RCX

0x41494c MOV	%RCX,-0x90(%RBP)

0x414953 MOV	0x20(%RBP),%RCX

0x414957 MOV	%RCX,-0x88(%RBP)

0x41495e MOV	0x18(%RBP),%RCX

0x414962 MOV	%RCX,-0x80(%RBP)

0x414966 MOV	0x10(%RBP),%RBX

0x41496a MOVL	$0,-0x78(%RBP)

0x414971 JS	4149e2

0x414973 MOV	%RDX,%R13

0x414976 MOV	%RDI,-0x140(%RBP)

0x41497d MOV	(%RDI),%ESI

0x41497f MOVL	$0,-0x48(%RBP)

0x414986 MOV	%EAX,-0x44(%RBP)

0x414989 MOVL	$0x1,-0x74(%RBP)

0x414990 SUB	$0x8,%RSP

0x414994 LEA	-0x74(%RBP),%RAX

0x414998 LEA	-0x78(%RBP),%RCX

0x41499c LEA	-0x48(%RBP),%R8

0x4149a0 LEA	-0x44(%RBP),%R9

0x4149a4 MOV	$0x526290,%EDI

0x4149a9 MOV	%ESI,-0x6c(%RBP)

0x4149ac MOV	$0x22,%EDX

0x4149b1 PUSH	$0x1

0x4149b3 PUSH	$0x1

0x4149b5 PUSH	%RAX

0x4149b6 CALL	404850 <__kmpc_for_static_init_4@plt>

0x4149bb ADD	$0x20,%RSP

0x4149bf MOV	-0x48(%RBP),%EAX

0x4149c2 MOV	-0x44(%RBP),%R11D

0x4149c6 SUB	%EAX,%R11D

0x4149c9 JAE	4149ff

0x4149cb MOV	$0x5262b0,%EDI

0x4149d0 MOV	-0x6c(%RBP),%ESI

0x4149d3 VZEROUPPER

0x4149d6 CALL	404070 <__kmpc_for_static_fini@plt>

0x4149db MOV	-0x140(%RBP),%RDI

0x4149e2 MOV	(%RDI),%ESI

0x4149e4 MOV	$0x5262d0,%EDI

0x4149e9 ADD	$0x208,%RSP

0x4149f0 POP	%RBX

0x4149f1 POP	%R12

0x4149f3 POP	%R13

0x4149f5 POP	%R14

0x4149f7 POP	%R15

0x4149f9 POP	%RBP

0x4149fa JMP	4047c0

0x4149ff MOV	%RAX,%RDX

0x414a02 VMOVQ	%R13,%XMM0

0x414a07 ADD	%R14D,%EDX

0x414a0a MOVSXD	(%R12),%RCX

0x414a0e MOV	(%R15),%EAX

0x414a11 SUB	%ECX,%EAX

0x414a13 LEA	0x1(%RAX),%R10D

0x414a17 ADD	$0x2,%EAX

0x414a1a CMP	$0x2,%EAX

0x414a1d MOV	$0x1,%ESI

0x414a22 CMOVGE	%EAX,%ESI

0x414a25 MOV	%ESI,%R13D

0x414a28 AND	$0x7ffffffc,%R13D

0x414a2f MOVSXD	-0x30(%RBP),%RDI

0x414a33 MOVSXD	%EBX,%RAX

0x414a36 LEA	-0x2(%RAX),%R8

0x414a3a MOV	%R8,-0x1b0(%RBP)

0x414a41 VPBROADCASTQ	%XMM0,%YMM0

0x414a46 MOV	%RSI,-0x1a8(%RBP)

0x414a4d VPBROADCASTQ	%RSI,%YMM1

0x414a53 MOV	%RCX,-0x1b8(%RBP)

0x414a5a LEA	(,%RCX,8),%RCX

0x414a62 SAL	$0x3,%RAX

0x414a66 SUB	%RAX,%RCX

0x414a69 MOV	-0xa0(%RBP),%RAX

0x414a70 ADD	%RCX,%RAX

0x414a73 ADD	$0x10,%RAX

0x414a77 MOV	%RAX,-0x1a0(%RBP)

0x414a7e MOV	$0x1,%EAX

0x414a83 SUB	%RDI,%RAX

0x414a86 MOV	%RAX,-0x198(%RBP)

0x414a8d MOV	$0x2,%EAX

0x414a92 SUB	%RDI,%RAX

0x414a95 MOV	%RAX,-0x190(%RBP)

0x414a9c MOV	-0xc0(%RBP),%RAX

0x414aa3 ADD	%RCX,%RAX

0x414aa6 ADD	$0x10,%RAX

0x414aaa MOV	%RAX,-0x188(%RBP)

0x414ab1 MOV	-0xa8(%RBP),%RAX

0x414ab8 LEA	0x10(%RAX,%RCX,1),%RAX

0x414abd MOV	%RAX,-0x180(%RBP)

0x414ac4 MOV	-0xb0(%RBP),%RAX

0x414acb LEA	0x10(%RAX,%RCX,1),%RAX

0x414ad0 MOV	%RAX,-0x178(%RBP)

0x414ad7 MOV	-0xb8(%RBP),%RAX

0x414ade LEA	0x10(%RAX,%RCX,1),%RAX

0x414ae3 MOV	%RAX,-0x170(%RBP)

0x414aea MOV	-0x80(%RBP),%RAX

0x414aee LEA	0x10(%RAX,%RCX,1),%RAX

0x414af3 MOV	%RAX,-0x168(%RBP)

0x414afa MOV	-0x90(%RBP),%RAX

0x414b01 LEA	0x10(%RAX,%RCX,1),%RAX

0x414b06 MOV	%RAX,-0x160(%RBP)

0x414b0d MOV	-0x88(%RBP),%RAX

0x414b14 LEA	0x10(%RAX,%RCX,1),%RAX

0x414b19 MOV	%RAX,-0x158(%RBP)

0x414b20 MOV	-0x98(%RBP),%RAX

0x414b27 LEA	0x10(%RAX,%RCX,1),%RAX

0x414b2c MOV	%RAX,-0x150(%RBP)

0x414b33 MOV	-0xc8(%RBP),%RAX

0x414b3a LEA	0x10(%RAX,%RCX,1),%RAX

0x414b3f MOV	%RAX,-0x148(%RBP)

0x414b46 VPMOVSXBQ	0xd11f1(%RIP),%YMM2

0x414b4f LEA	-0x2(%RDI),%RAX

0x414b53 MOV	%RAX,-0xd0(%RBP)

0x414b5a NEG	%RDI

0x414b5d MOV	%RDI,-0xd8(%RBP)

0x414b64 VBROADCASTSD	0xd13cb(%RIP),%YMM3

0x414b6d VBROADCASTSD	0xd0e02(%RIP),%YMM4

0x414b76 XOR	%EDI,%EDI

0x414b78 MOV	%RDX,-0x1c0(%RBP)

0x414b7f MOV	%EDX,%EBX

0x414b81 MOV	%R11D,-0x40(%RBP)

0x414b85 MOV	%R10D,-0x3c(%RBP)

0x414b89 MOV	%R13,-0x68(%RBP)

0x414b8d JMP	414e89

0x414b92 NOPW	%CS:(%RAX,%RAX,1)

(66) 0x414ba0 MOV	-0xd8(%RBP),%RAX

(66) 0x414ba7 ADD	%RCX,%RAX

(66) 0x414baa INC	%RAX

(66) 0x414bad MOV	%R15,%RDX

(66) 0x414bb0 IMUL	%RAX,%RDX

(66) 0x414bb4 MOV	%RDX,-0x100(%RBP)

(66) 0x414bbb MOV	%R8,%RDX

(66) 0x414bbe IMUL	%RAX,%RDX

(66) 0x414bc2 MOV	%RDX,-0xf8(%RBP)

(66) 0x414bc9 MOV	%R11,%RSI

(66) 0x414bcc IMUL	%RAX,%R11

(66) 0x414bd0 MOV	%RDI,%R12

(66) 0x414bd3 IMUL	%RAX,%RDI

(66) 0x414bd7 MOV	%R14,%R9

(66) 0x414bda MOV	%R14,%RDX

(66) 0x414bdd IMUL	%RAX,%R9

(66) 0x414be1 SUB	-0xd0(%RBP),%RCX

(66) 0x414be8 IMUL	%RCX,%R15

(66) 0x414bec IMUL	%RCX,%R8

(66) 0x414bf0 IMUL	%RCX,%RSI

(66) 0x414bf4 MOV	%RSI,-0x118(%RBP)

(66) 0x414bfb IMUL	%RCX,%R12

(66) 0x414bff MOV	%R12,-0x110(%RBP)

(66) 0x414c06 MOV	%R13,%R14

(66) 0x414c09 IMUL	%RCX,%R14

(66) 0x414c0d IMUL	%RCX,%RDX

(66) 0x414c11 MOV	%RDX,-0x120(%RBP)

(66) 0x414c18 IMUL	%RCX,%R10

(66) 0x414c1c MOV	-0x38(%RBP),%R13

(66) 0x414c20 IMUL	%RCX,%R13

(66) 0x414c24 MOV	-0x30(%RBP),%R12

(66) 0x414c28 IMUL	%RCX,%R12

(66) 0x414c2c IMUL	-0x50(%RBP),%RCX

(66) 0x414c31 MOV	%RCX,-0x130(%RBP)

(66) 0x414c38 MOV	%R13,-0x128(%RBP)

(66) 0x414c3f MOV	%R10,-0x108(%RBP)

(66) 0x414c46 MOV	%RDI,-0xf0(%RBP)

(66) 0x414c4d MOV	%R11,-0xe8(%RBP)

(66) 0x414c54 MOV	%R8,-0xe0(%RBP)

(66) 0x414c5b XOR	%EAX,%EAX

(66) 0x414c5d MOV	-0x68(%RBP),%R13

(66) 0x414c61 MOV	-0x138(%RBP),%RDI

(66) 0x414c68 MOV	-0x3c(%RBP),%R10D

(66) 0x414c6c MOV	-0x40(%RBP),%R11D

(66) 0x414c70 VPBROADCASTQ	%RAX,%YMM5

(66) 0x414c76 VPSUBQ	%YMM5,%YMM1,%YMM5

(66) 0x414c7a VPCMPNLEUQ	%YMM2,%YMM5,%K1

(66) 0x414c81 MOV	-0xb8(%RBP),%RDX

(66) 0x414c88 MOV	-0x100(%RBP),%R8

(66) 0x414c8f ADD	%RDX,%R8

(66) 0x414c92 ADD	-0x1b8(%RBP),%RAX

(66) 0x414c99 MOV	-0x1b0(%RBP),%RSI

(66) 0x414ca0 MOV	%RSI,%RCX

(66) 0x414ca3 NOT	%RCX

(66) 0x414ca6 ADD	%RAX,%RCX

(66) 0x414ca9 VMOVUPD	(%R8,%RCX,8),%YMM5{%K1}{z}

(66) 0x414cb0 SUB	%RSI,%RAX

(66) 0x414cb3 VMOVUPD	(%R8,%RAX,8),%YMM7{%K1}{z}

(66) 0x414cba MOV	-0xb0(%RBP),%RSI

(66) 0x414cc1 MOV	-0xf8(%RBP),%R8

(66) 0x414cc8 ADD	%RSI,%R8

(66) 0x414ccb VMOVUPD	(%R8,%RCX,8),%YMM10{%K1}{z}

(66) 0x414cd2 VMOVUPD	(%R8,%RAX,8),%YMM9{%K1}{z}

(66) 0x414cd9 ADD	%RDX,%R15

(66) 0x414cdc VMOVUPD	(%R15,%RAX,8),%YMM12{%K1}{z}

(66) 0x414ce3 VMOVUPD	(%R15,%RCX,8),%YMM13{%K1}{z}

(66) 0x414cea MOV	-0xe0(%RBP),%RDX

(66) 0x414cf1 ADD	%RSI,%RDX

(66) 0x414cf4 VMOVUPD	(%RDX,%RAX,8),%YMM14{%K1}{z}

(66) 0x414cfb VMOVUPD	(%RDX,%RCX,8),%YMM11{%K1}{z}

(66) 0x414d02 MOV	-0xc8(%RBP),%RDX

(66) 0x414d09 MOV	-0x118(%RBP),%RSI

(66) 0x414d10 ADD	%RDX,%RSI

(66) 0x414d13 VMOVUPD	(%RSI,%RAX,8),%YMM15{%K1}{z}

(66) 0x414d1a MOV	-0xa8(%RBP),%RSI

(66) 0x414d21 MOV	-0x110(%RBP),%R8

(66) 0x414d28 ADD	%RSI,%R8

(66) 0x414d2b VMOVUPD	(%R8,%RAX,8),%YMM8{%K1}{z}

(66) 0x414d32 VMOVUPD	(%R8,%RCX,8),%YMM6{%K1}{z}

(66) 0x414d39 MOV	-0xe8(%RBP),%R8

(66) 0x414d40 ADD	%RDX,%R8

(66) 0x414d43 VMOVUPD	(%R8,%RAX,8),%YMM16{%K1}{z}

(66) 0x414d4a MOV	-0xf0(%RBP),%RDX

(66) 0x414d51 ADD	%RSI,%RDX

(66) 0x414d54 VMOVUPD	(%RDX,%RAX,8),%YMM17{%K1}{z}

(66) 0x414d5b VMOVUPD	(%RDX,%RCX,8),%YMM18{%K1}{z}

(66) 0x414d62 ADD	-0xc0(%RBP),%R14

(66) 0x414d69 VMOVUPD	(%R14,%RAX,8),%YMM19{%K1}{z}

(66) 0x414d70 VMOVUPD	(%R14,%RCX,8),%YMM20{%K1}{z}

(66) 0x414d77 MOV	-0xa0(%RBP),%RDX

(66) 0x414d7e MOV	-0x120(%RBP),%RSI

(66) 0x414d85 ADD	%RDX,%RSI

(66) 0x414d88 VMOVUPD	(%RSI,%RAX,8),%YMM21{%K1}{z}

(66) 0x414d8f VMOVUPD	(%RSI,%RCX,8),%YMM22{%K1}{z}

(66) 0x414d96 ADD	%RDX,%R9

(66) 0x414d99 VMOVUPD	(%R9,%RCX,8),%YMM23{%K1}{z}

(66) 0x414da0 VMOVUPD	(%R9,%RAX,8),%YMM24{%K1}{z}

(66) 0x414da7 MOV	-0x108(%RBP),%RCX

(66) 0x414dae ADD	-0x98(%RBP),%RCX

(66) 0x414db5 VMOVUPD	(%RCX,%RAX,8),%YMM25{%K1}{z}

(66) 0x414dbc VMULPD	%YMM5,%YMM10,%YMM5

(66) 0x414dc0 VFMADD213PD	%YMM5,%YMM7,%YMM9

(66) 0x414dc5 VFMADD213PD	%YMM9,%YMM12,%YMM14

(66) 0x414dca VFMADD213PD	%YMM14,%YMM13,%YMM11

(66) 0x414dcf VSUBPD	%YMM8,%YMM6,%YMM5

(66) 0x414dd4 VMULPD	%YMM5,%YMM15,%YMM5

(66) 0x414dd8 VSUBPD	%YMM17,%YMM18,%YMM7

(66) 0x414dde VFMADD213PD	%YMM5,%YMM16,%YMM7

(66) 0x414de4 VSUBPD	%YMM21,%YMM22,%YMM5

(66) 0x414dea VFMADD213PD	%YMM7,%YMM15,%YMM5

(66) 0x414def VSUBPD	%YMM24,%YMM23,%YMM7

(66) 0x414df5 VFMADD231PD	%YMM7,%YMM16,%YMM5

(66) 0x414dfb VMOVAPD	%YMM3,%YMM7

(66) 0x414dff VMULPD	%YMM4,%YMM11,%YMM7{%K1}

(66) 0x414e05 VDIVPD	%YMM7,%YMM0,%YMM7

(66) 0x414e09 VFMADD231PD	%YMM5,%YMM7,%YMM25

(66) 0x414e0f MOV	-0x128(%RBP),%RCX

(66) 0x414e16 ADD	-0x88(%RBP),%RCX

(66) 0x414e1d VMOVUPD	%YMM25,(%RCX,%RAX,8){%K1}

(66) 0x414e24 ADD	-0x90(%RBP),%R12

(66) 0x414e2b VMOVUPD	(%R12,%RAX,8),%YMM5{%K1}{z}

(66) 0x414e32 VSUBPD	%YMM8,%YMM17,%YMM8

(66) 0x414e38 VMULPD	%YMM8,%YMM19,%YMM8

(66) 0x414e3e VSUBPD	%YMM6,%YMM18,%YMM6

(66) 0x414e44 VFMADD213PD	%YMM8,%YMM20,%YMM6

(66) 0x414e4a VSUBPD	%YMM21,%YMM24,%YMM8

(66) 0x414e50 VSUBPD	%YMM22,%YMM23,%YMM9

(66) 0x414e56 VFMADD213PD	%YMM6,%YMM19,%YMM8

(66) 0x414e5c VFMADD231PD	%YMM9,%YMM20,%YMM8

(66) 0x414e62 VFMADD231PD	%YMM8,%YMM7,%YMM5

(66) 0x414e67 MOV	-0x130(%RBP),%RCX

(66) 0x414e6e ADD	-0x80(%RBP),%RCX

(66) 0x414e72 VMOVUPD	%YMM5,(%RCX,%RAX,8){%K1}

(66) 0x414e79 LEA	0x1(%RDI),%EAX

(66) 0x414e7c INC	%EBX

(66) 0x414e7e CMP	%R11D,%EDI

(66) 0x414e81 MOV	%EAX,%EDI

(66) 0x414e83 JE	4149cb

(66) 0x414e89 TEST	%R10D,%R10D

(66) 0x414e8c JS	414e79

(66) 0x414e8e MOV	-0x1c0(%RBP),%RAX

(66) 0x414e95 MOV	%RDI,-0x138(%RBP)

(66) 0x414e9c ADD	%EDI,%EAX

(66) 0x414e9e MOV	-0x1c8(%RBP),%RCX

(66) 0x414ea5 MOV	(%RCX),%R8

(66) 0x414ea8 MOV	-0x1d0(%RBP),%RCX

(66) 0x414eaf MOV	(%RCX),%R15

(66) 0x414eb2 MOV	-0x1d8(%RBP),%RCX

(66) 0x414eb9 MOV	(%RCX),%R10

(66) 0x414ebc MOV	-0x1e0(%RBP),%RCX

(66) 0x414ec3 MOV	(%RCX),%R11

(66) 0x414ec6 MOV	-0x1e8(%RBP),%RCX

(66) 0x414ecd MOV	%R13,%RDX

(66) 0x414ed0 MOV	(%RCX),%RDI

(66) 0x414ed3 MOV	-0x1f0(%RBP),%RCX

(66) 0x414eda MOV	(%RCX),%RCX

(66) 0x414edd MOV	%RCX,-0x38(%RBP)

(66) 0x414ee1 MOV	-0x1f8(%RBP),%RCX

(66) 0x414ee8 MOV	(%RCX),%RCX

(66) 0x414eeb MOV	%RCX,-0x30(%RBP)

(66) 0x414eef MOV	-0x200(%RBP),%RCX

(66) 0x414ef6 MOV	(%RCX),%R13

(66) 0x414ef9 MOV	-0x208(%RBP),%RCX

(66) 0x414f00 MOV	(%RCX),%RCX

(66) 0x414f03 MOV	%RCX,-0x50(%RBP)

(66) 0x414f07 MOV	-0x210(%RBP),%RCX

(66) 0x414f0e MOV	(%RCX),%R14

(66) 0x414f11 MOVSXD	%EAX,%RCX

(66) 0x414f14 TEST	%RDX,%RDX

(66) 0x414f17 JE	414ba0

(66) 0x414f1d MOV	%EBX,-0x70(%RBP)

(66) 0x414f20 MOVSXD	%EBX,%R12

(66) 0x414f23 MOV	-0x198(%RBP),%RAX

(66) 0x414f2a LEA	(%RAX,%R12,1),%R9

(66) 0x414f2e ADD	-0x190(%RBP),%R12

(66) 0x414f35 MOV	-0xd8(%RBP),%RAX

(66) 0x414f3c ADD	%RCX,%RAX

(66) 0x414f3f INC	%RAX

(66) 0x414f42 MOV	%R11,-0x60(%RBP)

(66) 0x414f46 MOV	%R15,%RSI

(66) 0x414f49 IMUL	%RAX,%RSI

(66) 0x414f4d MOV	%RSI,-0x100(%RBP)

(66) 0x414f54 MOV	%R8,%RDX

(66) 0x414f57 MOV	%R8,%RSI

(66) 0x414f5a IMUL	%RAX,%RSI

(66) 0x414f5e MOV	%RSI,-0xf8(%RBP)

(66) 0x414f65 SUB	-0xd0(%RBP),%RCX

(66) 0x414f6c MOV	%R15,%RSI

(66) 0x414f6f IMUL	%RCX,%RSI

(66) 0x414f73 MOV	%RSI,-0x218(%RBP)

(66) 0x414f7a MOV	%R8,%RSI

(66) 0x414f7d IMUL	%RCX,%RSI

(66) 0x414f81 MOV	%RSI,-0xe0(%RBP)

(66) 0x414f88 MOV	%R11,%RSI

(66) 0x414f8b IMUL	%RCX,%RSI

(66) 0x414f8f MOV	%RSI,-0x118(%RBP)

(66) 0x414f96 MOV	%RDI,%RSI

(66) 0x414f99 IMUL	%RCX,%RSI

(66) 0x414f9d MOV	%RSI,-0x110(%RBP)

(66) 0x414fa4 IMUL	%RAX,%R11

(66) 0x414fa8 MOV	%R11,-0xe8(%RBP)

(66) 0x414faf MOV	%RDI,%RSI

(66) 0x414fb2 IMUL	%RAX,%RSI

(66) 0x414fb6 MOV	%RSI,-0xf0(%RBP)

(66) 0x414fbd MOV	%R13,%RSI

(66) 0x414fc0 IMUL	%RCX,%RSI

(66) 0x414fc4 MOV	%RSI,-0x220(%RBP)

(66) 0x414fcb MOV	%R14,%RSI

(66) 0x414fce IMUL	%RCX,%RSI

(66) 0x414fd2 MOV	%RSI,-0x120(%RBP)

(66) 0x414fd9 IMUL	%R14,%RAX

(66) 0x414fdd MOV	%RAX,-0x228(%RBP)

(66) 0x414fe4 MOV	%R10,-0x58(%RBP)

(66) 0x414fe8 IMUL	%RCX,%R10

(66) 0x414fec MOV	%R10,-0x108(%RBP)

(66) 0x414ff3 MOV	-0x38(%RBP),%RAX

(66) 0x414ff7 IMUL	%RCX,%RAX

(66) 0x414ffb MOV	%RAX,-0x128(%RBP)

(66) 0x415002 MOV	-0x30(%RBP),%R11

(66) 0x415006 MOV	%R11,%RAX

(66) 0x415009 IMUL	%RCX,%RAX

(66) 0x41500d MOV	%RAX,-0x230(%RBP)

(66) 0x415014 MOV	-0x50(%RBP),%R8

(66) 0x415018 IMUL	%R8,%RCX

(66) 0x41501c MOV	%RCX,-0x130(%RBP)

(66) 0x415023 MOV	%R14,%RBX

(66) 0x415026 IMUL	%R9,%RBX

(66) 0x41502a IMUL	%R12,%R14

(66) 0x41502e IMUL	%R12,%R13

(66) 0x415032 MOV	%RDI,%RAX

(66) 0x415035 IMUL	%R9,%RAX

(66) 0x415039 IMUL	%R12,%RDI

(66) 0x41503d MOV	%RDX,%RSI

(66) 0x415040 IMUL	%R12,%RSI

(66) 0x415044 MOV	%R15,%R10

(66) 0x415047 IMUL	%R12,%R10

(66) 0x41504b IMUL	%R9,%RDX

(66) 0x41504f IMUL	%R9,%R15

(66) 0x415053 IMUL	%R12,%R8

(66) 0x415057 IMUL	%R12,%R11

(66) 0x41505b MOV	-0x38(%RBP),%RCX

(66) 0x41505f IMUL	%R12,%RCX

(66) 0x415063 MOV	%RCX,-0x38(%RBP)

(66) 0x415067 MOV	-0x58(%RBP),%RCX

(66) 0x41506b IMUL	%R12,%RCX

(66) 0x41506f MOV	%RCX,-0x58(%RBP)

(66) 0x415073 MOV	-0x60(%RBP),%RCX

(66) 0x415077 IMUL	%RCX,%R9

(66) 0x41507b IMUL	%RCX,%R12

(66) 0x41507f MOV	-0x1a0(%RBP),%RCX

(66) 0x415086 ADD	%RCX,%RBX

(66) 0x415089 ADD	%RCX,%R14

(66) 0x41508c MOV	%R14,-0x50(%RBP)

(66) 0x415090 ADD	-0x188(%RBP),%R13

(66) 0x415097 MOV	%R13,-0x30(%RBP)

(66) 0x41509b MOV	-0x180(%RBP),%RCX

(66) 0x4150a2 ADD	%RCX,%RAX

(66) 0x4150a5 ADD	%RCX,%RDI

(66) 0x4150a8 MOV	%RDI,-0x60(%RBP)

(66) 0x4150ac MOV	-0x178(%RBP),%RCX

(66) 0x4150b3 ADD	%RCX,%RSI

(66) 0x4150b6 MOV	-0x170(%RBP),%RDI

(66) 0x4150bd ADD	%RDI,%R10

(66) 0x4150c0 ADD	%RCX,%RDX

(66) 0x4150c3 MOV	%RDX,%R14

(66) 0x4150c6 ADD	%RDI,%R15

(66) 0x4150c9 MOV	%R15,%RDI

(66) 0x4150cc ADD	-0x168(%RBP),%R8

(66) 0x4150d3 ADD	-0x160(%RBP),%R11

(66) 0x4150da MOV	%R11,%RDX

(66) 0x4150dd MOV	-0x38(%RBP),%R11

(66) 0x4150e1 ADD	-0x158(%RBP),%R11

(66) 0x4150e8 MOV	-0x58(%RBP),%R13

(66) 0x4150ec ADD	-0x150(%RBP),%R13

(66) 0x4150f3 MOV	-0x148(%RBP),%RCX

(66) 0x4150fa ADD	%RCX,%R9

(66) 0x4150fd ADD	%RCX,%R12

(66) 0x415100 XOR	%ECX,%ECX

(66) 0x415102 NOPW	%CS:(%RAX,%RAX,1)

  (67) 0x415110 VMOVUPD	-0x8(%RDI,%RCX,8),%YMM5

  (67) 0x415116 VMOVUPD	(%RDI,%RCX,8),%YMM6

  (67) 0x41511b VMULPD	-0x8(%R14,%RCX,8),%YMM5,%YMM5

  (67) 0x415122 VFMADD231PD	(%R14,%RCX,8),%YMM6,%YMM5

  (67) 0x415128 VMOVUPD	-0x8(%R10,%RCX,8),%YMM6

  (67) 0x41512f VMOVUPD	(%R10,%RCX,8),%YMM7

  (67) 0x415135 VFMADD132PD	(%RSI,%RCX,8),%YMM5,%YMM7

  (67) 0x41513b VFMADD231PD	-0x8(%RSI,%RCX,8),%YMM6,%YMM7

  (67) 0x415142 VMULPD	%YMM4,%YMM7,%YMM5

  (67) 0x415146 VDIVPD	%YMM5,%YMM0,%YMM5

  (67) 0x41514a VMOVUPD	(%R12,%RCX,8),%YMM6

  (67) 0x415150 MOV	-0x60(%RBP),%R15

  (67) 0x415154 VMOVUPD	-0x8(%R15,%RCX,8),%YMM7

  (67) 0x41515b VMOVUPD	(%R15,%RCX,8),%YMM8

  (67) 0x415161 VSUBPD	%YMM8,%YMM7,%YMM9

  (67) 0x415166 VMULPD	%YMM6,%YMM9,%YMM9

  (67) 0x41516a VMOVUPD	(%R9,%RCX,8),%YMM10

  (67) 0x415170 VMOVUPD	-0x8(%RAX,%RCX,8),%YMM11

  (67) 0x415176 VMOVUPD	(%RAX,%RCX,8),%YMM12

  (67) 0x41517b VSUBPD	%YMM12,%YMM11,%YMM13

  (67) 0x415180 VFMADD213PD	%YMM9,%YMM10,%YMM13

  (67) 0x415185 MOV	-0x30(%RBP),%R15

  (67) 0x415189 VMOVUPD	-0x8(%R15,%RCX,8),%YMM9

  (67) 0x415190 VMOVUPD	(%R15,%RCX,8),%YMM14

  (67) 0x415196 VSUBPD	%YMM8,%YMM12,%YMM8

  (67) 0x41519b VMULPD	%YMM8,%YMM14,%YMM8

  (67) 0x4151a0 VSUBPD	%YMM7,%YMM11,%YMM7

  (67) 0x4151a4 VFMADD213PD	%YMM8,%YMM9,%YMM7

  (67) 0x4151a9 MOV	-0x50(%RBP),%R15

  (67) 0x4151ad VMOVUPD	-0x8(%R15,%RCX,8),%YMM8

  (67) 0x4151b4 VMOVUPD	(%R15,%RCX,8),%YMM11

  (67) 0x4151ba VMOVUPD	-0x8(%RBX,%RCX,8),%YMM12

  (67) 0x4151c0 VMOVUPD	(%RBX,%RCX,8),%YMM15

  (67) 0x4151c5 VSUBPD	%YMM11,%YMM8,%YMM16

  (67) 0x4151cb VSUBPD	%YMM15,%YMM12,%YMM17

  (67) 0x4151d1 VFMADD213PD	%YMM13,%YMM6,%YMM16

  (67) 0x4151d7 VFMADD231PD	%YMM17,%YMM10,%YMM16

  (67) 0x4151dd VFMADD213PD	(%R13,%RCX,8),%YMM5,%YMM16

  (67) 0x4151e5 VMOVUPD	%YMM16,(%R11,%RCX,8)

  (67) 0x4151ec VSUBPD	%YMM11,%YMM15,%YMM6

  (67) 0x4151f1 VSUBPD	%YMM8,%YMM12,%YMM8

  (67) 0x4151f6 VFMADD213PD	%YMM7,%YMM14,%YMM6

  (67) 0x4151fb VFMADD231PD	%YMM8,%YMM9,%YMM6

  (67) 0x415200 VFMADD213PD	(%RDX,%RCX,8),%YMM5,%YMM6

  (67) 0x415206 VMOVUPD	%YMM6,(%R8,%RCX,8)

  (67) 0x41520c ADD	$0x4,%RCX

  (67) 0x415210 CMP	-0x68(%RBP),%RCX

  (67) 0x415214 JB	415110

(66) 0x41521a MOV	-0x68(%RBP),%R13

(66) 0x41521e MOV	%R13,%RAX

(66) 0x415221 CMP	-0x1a8(%RBP),%R13D

(66) 0x415228 MOV	-0x40(%RBP),%R11D

(66) 0x41522c MOV	-0x3c(%RBP),%R10D

(66) 0x415230 MOV	-0x70(%RBP),%EBX

(66) 0x415233 MOV	-0x138(%RBP),%RDI

(66) 0x41523a MOV	-0x230(%RBP),%R12

(66) 0x415241 MOV	-0x228(%RBP),%R9

(66) 0x415248 MOV	-0x220(%RBP),%R14

(66) 0x41524f MOV	-0x218(%RBP),%R15

(66) 0x415256 JNE	414c70

(66) 0x41525c JMP	414e79

0x415261 NOPW	%CS:(%RAX,%RAX,1)

0x41526b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►99.96+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	accelerate_kernel.f90:57-79
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:57-79.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.83 to 9.13 cycles (3.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:79
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:61

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:60
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:79

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 332 bytes. The binary function is storing 356 bytes.

General properties

nb instructions	175
nb uops	179
loop length	879
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	5
used zmm registers	0
nb stack references	73

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.83 cycles
front end	29.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.20	8.20	17.67	17.67	29.50	8.20	8.20	29.50	29.50	29.50	8.20	17.67
cycles	8.20	13.13	17.67	17.67	29.50	8.20	8.20	29.50	29.50	29.50	8.20	17.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	29.83
Dispatch	29.50
Overall L1	29.83

Vectorization ratios

INT

all	2%
load	14%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

INT

all	10%
load	7%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	8%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.83 cycles. At this rate:

5% of peak load performance is reached (11.13 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.93 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 414840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x208,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x210(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x208(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x200(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1f8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1f0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1e8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1e0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1d8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x68(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x1d0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x1c8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVL $0,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 4149e2 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x1a2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x74(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x74(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x78(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x44(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x526290,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x6c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x44(%RBP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %EAX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 4149ff <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x1bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x5262b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x6c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x140(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x5262d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x208,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4047c0 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD (%R12),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVGE %EAX,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %ESI,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffffc,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOVSXD -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EBX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA -0x2(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x1b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %XMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RSI,-0x1a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RSI,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,-0x1b8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x178(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPMOVSXBQ 0xd11f1(%RIP),%YMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
LEA -0x2(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NEG %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD 0xd13cb(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0xd0e02(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,-0x1c0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11D,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10D,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R13,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 414e89 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x649>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	accelerate_kernel.f90:57-79
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.83 to 9.13 cycles (3.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:79
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:61

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:60
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:79

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 332 bytes. The binary function is storing 356 bytes.

General properties

nb instructions	175
nb uops	179
loop length	879
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	5
used zmm registers	0
nb stack references	73

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.83 cycles
front end	29.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.20	8.20	17.67	17.67	29.50	8.20	8.20	29.50	29.50	29.50	8.20	17.67
cycles	8.20	13.13	17.67	17.67	29.50	8.20	8.20	29.50	29.50	29.50	8.20	17.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	29.83
Dispatch	29.50
Overall L1	29.83

Vectorization ratios

INT

all	2%
load	14%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

INT

all	10%
load	7%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	8%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.83 cycles. At this rate:

5% of peak load performance is reached (11.13 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.93 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 414840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x208,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x210(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x208(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x200(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1f8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1f0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1e8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1e0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x1d8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x68(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x1d0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x1c8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVL $0,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 4149e2 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x1a2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x74(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x74(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x78(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x44(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x526290,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x6c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x44(%RBP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %EAX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 4149ff <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x1bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x5262b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x6c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x140(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x5262d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x208,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4047c0 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD (%R12),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVGE %EAX,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %ESI,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffffc,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOVSXD -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EBX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA -0x2(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x1b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %XMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RSI,-0x1a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RSI,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,-0x1b8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x178(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RCX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPMOVSXBQ 0xd11f1(%RIP),%YMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
LEA -0x2(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NEG %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD 0xd13cb(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0xd0e02(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,-0x1c0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11D,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10D,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R13,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 414e89 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x649>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2–	5.41	2.02
▼Loop 66 - accelerate_kernel.f90:60-76 - exec–	0.00	0.01
○Loop 67 - accelerate_kernel.f90:62-76 - exec	5.40	2.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code