OV - exec - Function viscosity_kernel_module_mp_viscosity_kernel

	Function: viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2	Module: exec	Source: viscosity_kernel.f90:50-94	Coverage (incl. loops): 2.22% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 50 - 94

--------------------------------------------------------------------------------

50:     !$OMP PARALLEL

51:

52:     !$OMP DO PRIVATE(ugrad,vgrad,div,strain2,pgradx,pgrady,pgradx2,pgrady2,limiter,pgrad,xgrad,ygrad,grad,grad2,dirx,diry)

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

90:         ENDIF

91:

92:       ENDDO

93:     ENDDO

94:   !$OMP END DO

0x451af0 PUSH	%RBP

0x451af1 MOV	%RSP,%RBP

0x451af4 PUSH	%R15

0x451af6 PUSH	%R14

0x451af8 PUSH	%R13

0x451afa PUSH	%R12

0x451afc PUSH	%RBX

0x451afd AND	$-0x20,%RSP

0x451b01 SUB	$0x2c0,%RSP

0x451b08 MOV	0x50(%RBP),%EBX

0x451b0b MOV	0x48(%RBP),%EAX

0x451b0e SUB	%EBX,%EAX

0x451b10 MOVL	$0,0x3c(%RSP)

0x451b18 JS	451b95

0x451b1a MOV	%R9,%R15

0x451b1d MOV	%RCX,%R12

0x451b20 MOV	%RDI,0x70(%RSP)

0x451b25 MOV	(%RDI),%ESI

0x451b27 MOVL	$0,0x14(%RSP)

0x451b2f MOV	%EAX,0x10(%RSP)

0x451b33 MOVL	$0x1,0x38(%RSP)

0x451b3b SUB	$0x8,%RSP

0x451b3f LEA	0x40(%RSP),%RAX

0x451b44 LEA	0x44(%RSP),%RCX

0x451b49 LEA	0x1c(%RSP),%R8

0x451b4e LEA	0x18(%RSP),%R9

0x451b53 MOV	$0x52d630,%EDI

0x451b58 MOV	%ESI,0x34(%RSP)

0x451b5c MOV	$0x22,%EDX

0x451b61 PUSH	$0x1

0x451b63 PUSH	$0x1

0x451b65 PUSH	%RAX

0x451b66 CALL	404850 <__kmpc_for_static_init_4@plt>

0x451b6b ADD	$0x20,%RSP

0x451b6f MOV	0x14(%RSP),%EAX

0x451b73 MOV	0x10(%RSP),%ECX

0x451b77 SUB	%EAX,%ECX

0x451b79 MOV	%ECX,0x30(%RSP)

0x451b7d JAE	451bb0

0x451b7f MOV	$0x52d650,%EDI

0x451b84 MOV	0x2c(%RSP),%ESI

0x451b88 VZEROUPPER

0x451b8b CALL	404070 <__kmpc_for_static_fini@plt>

0x451b90 MOV	0x70(%RSP),%RDI

0x451b95 MOV	(%RDI),%ESI

0x451b97 MOV	$0x52d670,%EDI

0x451b9c CALL	4047c0 <__kmpc_barrier@plt>

0x451ba1 LEA	-0x28(%RBP),%RSP

0x451ba5 POP	%RBX

0x451ba6 POP	%R12

0x451ba8 POP	%R13

0x451baa POP	%R14

0x451bac POP	%R15

0x451bae POP	%RBP

0x451baf RET

0x451bb0 MOV	%RAX,%RSI

0x451bb3 MOV	0x60(%RBP),%RAX

0x451bb7 MOV	0x58(%RBP),%RCX

0x451bbb MOVSXD	(%RAX),%RDI

0x451bbe MOV	(%RCX),%ECX

0x451bc0 SUB	%EDI,%ECX

0x451bc2 ADD	%EBX,%ESI

0x451bc4 LEA	-0x2(%R12),%EAX

0x451bc9 CLTQ

0x451bcb MOV	%RAX,0x100(%RSP)

0x451bd3 MOV	%RCX,0x138(%RSP)

0x451bdb LEA	0x1(%RCX),%EAX

0x451bde CMP	$0x2,%EAX

0x451be1 MOV	$0x1,%ECX

0x451be6 CMOVGE	%EAX,%ECX

0x451be9 MOV	%RCX,0x48(%RSP)

0x451bee AND	$0x7ffffffc,%ECX

0x451bf4 MOV	%RCX,0x20(%RSP)

0x451bf9 MOVSXD	%R12D,%RCX

0x451bfc MOVSXD	%R15D,%RDX

0x451bff LEA	-0x2(%RDX),%RAX

0x451c03 MOV	%RAX,0xd8(%RSP)

0x451c0b MOV	%RDI,0xe0(%RSP)

0x451c13 LEA	(,%RDI,8),%RAX

0x451c1b SAL	$0x3,%RDX

0x451c1f SUB	%RDX,%RAX

0x451c22 MOV	$0x2,%EDI

0x451c27 SUB	%RCX,%RDI

0x451c2a MOV	%RDI,0xf8(%RSP)

0x451c32 MOV	$0x1,%EDI

0x451c37 SUB	%RCX,%RDI

0x451c3a MOV	%RDI,0xf0(%RSP)

0x451c42 MOV	$0x10,%EDI

0x451c47 SUB	%RDX,%RDI

0x451c4a MOV	$0x18,%R8D

0x451c50 SUB	%RDX,%R8

0x451c53 MOV	$0x3,%EDX

0x451c58 SUB	%RCX,%RDX

0x451c5b MOV	%RDX,0xe8(%RSP)

0x451c63 ADD	$-0x2,%RCX

0x451c67 MOV	%RCX,0x40(%RSP)

0x451c6c MOV	0x40(%RBP),%RCX

0x451c70 MOV	0x30(%RBP),%RDX

0x451c74 MOV	0x28(%RBP),%R9

0x451c78 MOV	0x20(%RBP),%R10

0x451c7c MOV	0x18(%RBP),%RBX

0x451c80 MOV	0x10(%RBP),%R14

0x451c84 LEA	0x18(%R9,%RAX,1),%R11

0x451c89 MOV	%R11,0x98(%RSP)

0x451c91 LEA	0x10(%R10,%RAX,1),%R11

0x451c96 MOV	%R11,0x90(%RSP)

0x451c9e LEA	0x10(%RDX,%RAX,1),%R11

0x451ca3 MOV	%R11,0x158(%RSP)

0x451cab LEA	0x10(%R9,%RAX,1),%R11

0x451cb0 MOV	%R11,0x88(%RSP)

0x451cb8 LEA	0x18(%RCX,%RAX,1),%R11

0x451cbd LEA	0x18(%R14,%RAX,1),%R15

0x451cc2 MOV	%R15,0x80(%RSP)

0x451cca ADD	%RBX,%RAX

0x451ccd ADD	$0x18,%RAX

0x451cd1 MOV	%RAX,0x78(%RSP)

0x451cd6 ADD	%RDI,%R10

0x451cd9 MOV	%R10,0xb8(%RSP)

0x451ce1 ADD	%RDI,%RDX

0x451ce4 MOV	%RDX,0xc0(%RSP)

0x451cec ADD	%R9,%RDI

0x451cef MOV	%RDI,0xd0(%RSP)

0x451cf7 LEA	(%RCX,%R8,1),%RAX

0x451cfb MOV	%RAX,0xb0(%RSP)

0x451d03 LEA	(%R9,%R8,1),%RAX

0x451d07 MOV	%RAX,0xa8(%RSP)

0x451d0f LEA	(%R14,%R8,1),%RAX

0x451d13 MOV	%RAX,0xa0(%RSP)

0x451d1b ADD	%RBX,%R8

0x451d1e MOV	%R8,0xc8(%RSP)

0x451d26 VMOVSD	0x9350a(%RIP),%XMM15

0x451d2e VMOVSD	0x941fa(%RIP),%XMM1

0x451d36 VMOVSD	0xb0218(%RIP),%XMM16

0x451d40 VMOVSD	0xb0216(%RIP),%XMM17

0x451d4a VBROADCASTSD	0x934e4(%RIP),%YMM20

0x451d54 VXORPD	%XMM18,%XMM18,%XMM18

0x451d5a XOR	%EDI,%EDI

0x451d5c MOV	%RSI,0x108(%RSP)

0x451d64 MOV	%ESI,%ECX

0x451d66 JMP	451d8d

0x451d68 NOPL	(%RAX,%RAX,1)

(967) 0x451d70 MOV	0x150(%RSP),%RDX

(967) 0x451d78 LEA	0x1(%RDX),%EAX

(967) 0x451d7b MOV	0x34(%RSP),%ECX

(967) 0x451d7f INC	%ECX

(967) 0x451d81 CMP	0x30(%RSP),%EDX

(967) 0x451d85 MOV	%EAX,%EDI

(967) 0x451d87 JE	451b7f

(967) 0x451d8d CMPL	$0,0x138(%RSP)

(967) 0x451d95 MOV	%ECX,0x34(%RSP)

(967) 0x451d99 MOV	%RDI,0x150(%RSP)

(967) 0x451da1 JS	451d70

(967) 0x451da3 MOVSXD	%ECX,%RBX

(967) 0x451da6 MOV	0xf8(%RSP),%RAX

(967) 0x451dae LEA	(%RAX,%RBX,1),%R8

(967) 0x451db2 MOV	0xf0(%RSP),%RAX

(967) 0x451dba LEA	(%RAX,%RBX,1),%R14

(967) 0x451dbe ADD	0xe8(%RSP),%RBX

(967) 0x451dc6 MOV	0x108(%RSP),%RCX

(967) 0x451dce LEA	(%RCX,%RDI,1),%EAX

(967) 0x451dd1 MOVSXD	%EAX,%R13

(967) 0x451dd4 MOV	%R13,%RAX

(967) 0x451dd7 MOV	0x100(%RSP),%RDX

(967) 0x451ddf SUB	%RDX,%RAX

(967) 0x451de2 ADD	%EDI,%ECX

(967) 0x451de4 INC	%ECX

(967) 0x451de6 MOVSXD	%ECX,%RCX

(967) 0x451de9 SUB	%RDX,%RCX

(967) 0x451dec MOV	0x68(%RBP),%RDX

(967) 0x451df0 MOV	(%RDX),%R12

(967) 0x451df3 MOV	0x38(%RBP),%RDX

(967) 0x451df7 VMOVSD	(%RDX,%RAX,8),%XMM4

(967) 0x451dfc MOV	0x70(%RBP),%RAX

(967) 0x451e00 MOV	(%RAX),%R9

(967) 0x451e03 MOV	0x78(%RBP),%RAX

(967) 0x451e07 MOV	(%RAX),%RDI

(967) 0x451e0a VADDSD	(%RDX,%RCX,8),%XMM4,%XMM2

(967) 0x451e0f MOV	0x80(%RBP),%RAX

(967) 0x451e16 MOV	(%RAX),%R10

(967) 0x451e19 CMPQ	$0,0x20(%RSP)

(967) 0x451e1f VMOVAPD	%XMM4,0x180(%RSP)

(967) 0x451e28 MOV	%R12,0x148(%RSP)

(967) 0x451e30 MOV	%R9,0x140(%RSP)

(967) 0x451e38 JE	4524e0

(967) 0x451e3e VMOVAPD	%XMM13,0x60(%RSP)

(967) 0x451e44 VMOVAPD	%XMM31,%XMM0

(967) 0x451e4a VBROADCASTSD	%XMM13,%YMM31

(967) 0x451e50 VBROADCASTSD	%XMM14,%YMM29

(967) 0x451e56 VMOVAPD	%XMM19,0x1b0(%RSP)

(967) 0x451e5e VBROADCASTSD	%XMM19,%YMM27

(967) 0x451e64 VMOVAPD	%XMM30,0x1a0(%RSP)

(967) 0x451e6c VBROADCASTSD	%XMM30,%YMM25

(967) 0x451e72 VBROADCASTSD	0x170(%RSP),%YMM24

(967) 0x451e7a VMOVAPD	%XMM0,0x190(%RSP)

(967) 0x451e83 VBROADCASTSD	%XMM0,%YMM23

(967) 0x451e89 VBROADCASTSD	0x160(%RSP),%YMM22

(967) 0x451e91 SUB	0x40(%RSP),%R13

(967) 0x451e96 MOV	%R12,%RAX

(967) 0x451e99 IMUL	%R13,%RAX

(967) 0x451e9d MOV	%RAX,0x18(%RSP)

(967) 0x451ea2 LEA	0x1(%R13),%RCX

(967) 0x451ea6 MOV	%R12,%RAX

(967) 0x451ea9 IMUL	%RCX,%RAX

(967) 0x451ead MOV	%RAX,0x110(%RSP)

(967) 0x451eb5 IMUL	%R9,%RCX

(967) 0x451eb9 MOV	%RCX,0x58(%RSP)

(967) 0x451ebe MOV	%R9,%RAX

(967) 0x451ec1 IMUL	%R13,%RAX

(967) 0x451ec5 MOV	%RAX,0x50(%RSP)

(967) 0x451eca VBROADCASTSD	%XMM4,%YMM26

(967) 0x451ed0 IMUL	%RDI,%R13

(967) 0x451ed4 VDIVSD	%XMM4,%XMM15,%XMM0

(967) 0x451ed8 VBROADCASTSD	%XMM0,%YMM28

(967) 0x451ede VMOVSD	%XMM2,0x130(%RSP)

(967) 0x451ee7 VDIVSD	%XMM2,%XMM15,%XMM0

(967) 0x451eeb VBROADCASTSD	%XMM0,%YMM30

(967) 0x451ef1 MOV	%RDI,%RSI

(967) 0x451ef4 IMUL	%R8,%RSI

(967) 0x451ef8 ADD	0x98(%RSP),%RSI

(967) 0x451f00 MOV	%R10,0x118(%RSP)

(967) 0x451f08 IMUL	%R8,%R10

(967) 0x451f0c ADD	0x90(%RSP),%R10

(967) 0x451f14 MOV	%RDI,%RDX

(967) 0x451f17 MOV	%R14,0x128(%RSP)

(967) 0x451f1f IMUL	%R14,%RDX

(967) 0x451f23 MOV	0x88(%RSP),%RAX

(967) 0x451f2b ADD	%RAX,%RDX

(967) 0x451f2e MOV	%RDI,0x120(%RSP)

(967) 0x451f36 MOV	%RDI,%R14

(967) 0x451f39 IMUL	%RBX,%R14

(967) 0x451f3d ADD	%RAX,%R14

(967) 0x451f40 MOV	%R9,%R15

(967) 0x451f43 IMUL	%R8,%R15

(967) 0x451f47 MOV	0x80(%RSP),%RAX

(967) 0x451f4f ADD	%RAX,%R15

(967) 0x451f52 IMUL	%RBX,%R9

(967) 0x451f56 ADD	%RAX,%R9

(967) 0x451f59 MOV	%R12,%RCX

(967) 0x451f5c IMUL	%RBX,%RCX

(967) 0x451f60 MOV	0x78(%RSP),%RDI

(967) 0x451f65 ADD	%RDI,%RCX

(967) 0x451f68 MOV	%R12,%RAX

(967) 0x451f6b IMUL	%R8,%RAX

(967) 0x451f6f ADD	%RDI,%RAX

(967) 0x451f72 VPCMPEQD	%YMM12,%YMM12,%YMM12

(967) 0x451f77 XOR	%R12D,%R12D

(967) 0x451f7a VPCMPEQD	%YMM11,%YMM11,%YMM11

(967) 0x451f7f VPCMPEQD	%YMM3,%YMM3,%YMM3

(967) 0x451f83 VPCMPEQD	%YMM6,%YMM6,%YMM6

(967) 0x451f87 VPCMPEQD	%YMM9,%YMM9,%YMM9

(967) 0x451f8c VPCMPEQD	%YMM2,%YMM2,%YMM2

(967) 0x451f90 VPCMPEQD	%YMM0,%YMM0,%YMM0

(967) 0x451f94 VBROADCASTSD	0xaffbb(%RIP),%YMM1

(967) 0x451f9d JMP	4520d7

0x451fa2 NOPW	%CS:(%RAX,%RAX,1)

  (969) 0x451fb0 VCMPPD	$0x1,%YMM13,%YMM18,%K2

  (969) 0x451fb7 VBROADCASTSD	0xaffa0(%RIP),%YMM7

  (969) 0x451fc0 VBLENDMPD	%YMM7,%YMM20,%YMM4{%K2}

  (969) 0x451fc6 VBROADCASTSD	0x930e0(%RIP),%YMM19

  (969) 0x451fd0 VANDPD	%YMM19,%YMM18,%YMM5

  (969) 0x451fd6 VMAXPD	%YMM1,%YMM5,%YMM5

  (969) 0x451fda VMULPD	%YMM5,%YMM4,%YMM5

  (969) 0x451fde VCMPPD	$0x1,%YMM13,%YMM5,%K2

  (969) 0x451fe5 VBLENDMPD	%YMM7,%YMM20,%YMM7{%K2}

  (969) 0x451feb VANDPD	%YMM19,%YMM17,%YMM8

  (969) 0x451ff1 VMAXPD	%YMM1,%YMM8,%YMM8

  (969) 0x451ff5 VMULPD	%YMM7,%YMM8,%YMM8

  (969) 0x451ff9 VMULPD	%YMM5,%YMM5,%YMM10

  (969) 0x451ffd VFMADD231PD	%YMM8,%YMM8,%YMM10

  (969) 0x452002 VSQRTPD	%YMM10,%YMM10

  (969) 0x452007 VMULPD	%YMM21,%YMM10,%YMM15

  (969) 0x45200d VDIVPD	%YMM5,%YMM15,%YMM5

  (969) 0x452011 VANDPD	%YMM19,%YMM5,%YMM5

  (969) 0x452017 VMULPD	%YMM26,%YMM10,%YMM15

  (969) 0x45201d VDIVPD	%YMM8,%YMM15,%YMM8

  (969) 0x452022 VANDPD	%YMM19,%YMM8,%YMM8

  (969) 0x452028 VMINPD	%YMM8,%YMM5,%YMM15

  (969) 0x45202d VMULPD	%YMM15,%YMM15,%YMM17

  (969) 0x452033 VMULPD	%YMM16,%YMM16,%YMM16

  (969) 0x452039 VADDPD	%YMM17,%YMM17,%YMM18

  (969) 0x45203f VMULPD	%YMM18,%YMM16,%YMM16

  (969) 0x452045 IMUL	%R8,%RDI

  (969) 0x452049 ADD	0x158(%RSP),%RDI

  (969) 0x452051 VMOVUPD	(%RDI,%R12,8),%YMM18{%K1}{z}

  (969) 0x452058 VPBROADCASTQ	%R12,%YMM19

  (969) 0x45205e VPADDQ	0x931f8(%RIP),%YMM19,%YMM19

  (969) 0x452068 VMOVDQA64	%YMM19,%YMM0{%K1}

  (969) 0x45206e VMOVAPD	%YMM4,%YMM31{%K1}

  (969) 0x452074 VMOVDQA64	%YMM19,%YMM2{%K1}

  (969) 0x45207a VMOVAPD	%YMM7,%YMM29{%K1}

  (969) 0x452080 VMOVDQA64	%YMM19,%YMM9{%K1}

  (969) 0x452086 VMOVAPD	%YMM10,%YMM27{%K1}

  (969) 0x45208c VMOVDQA64	%YMM19,%YMM6{%K1}

  (969) 0x452092 VMOVAPD	%YMM5,%YMM25{%K1}

  (969) 0x452098 VMOVDQA64	%YMM19,%YMM3{%K1}

  (969) 0x45209e VMOVAPD	%YMM8,%YMM24{%K1}

  (969) 0x4520a4 VMOVDQA64	%YMM19,%YMM11{%K1}

  (969) 0x4520aa VMOVAPD	%YMM15,%YMM23{%K1}

  (969) 0x4520b0 VMOVDQA64	%YMM19,%YMM12{%K1}

  (969) 0x4520b6 VMOVAPD	%YMM17,%YMM22{%K1}

  (969) 0x4520bc VMULPD	%YMM18,%YMM16,%YMM4{%K1}{z}

  (969) 0x4520c2 VMOVUPD	%YMM4,(%R10,%R12,8)

  (969) 0x4520c8 ADD	$0x4,%R12

  (969) 0x4520cc CMP	0x20(%RSP),%R12

  (969) 0x4520d1 JAE	452250

  (969) 0x4520d7 VMOVUPD	-0x8(%RAX,%R12,8),%YMM16

  (969) 0x4520e2 VMOVUPD	(%RAX,%R12,8),%YMM17

  (969) 0x4520e9 VMOVUPD	-0x8(%RCX,%R12,8),%YMM18

  (969) 0x4520f4 VMOVUPD	(%RCX,%R12,8),%YMM19

  (969) 0x4520fb VADDPD	%YMM17,%YMM19,%YMM21

  (969) 0x452101 VADDPD	%YMM18,%YMM16,%YMM5

  (969) 0x452107 VSUBPD	%YMM5,%YMM21,%YMM5

  (969) 0x45210d VMOVUPD	-0x8(%R9,%R12,8),%YMM7

  (969) 0x452114 VMOVAPD	%YMM20,%YMM13

  (969) 0x45211a VMOVUPD	(%R9,%R12,8),%YMM20

  (969) 0x452121 VMOVUPD	-0x8(%R15,%R12,8),%YMM15

  (969) 0x452128 VMOVUPD	(%R15,%R12,8),%YMM4

  (969) 0x45212e VADDPD	%YMM7,%YMM20,%YMM8

  (969) 0x452134 VADDPD	%YMM4,%YMM15,%YMM10

  (969) 0x452138 VMOVUPD	-0x8(%R11,%R12,8),%YMM21

  (969) 0x452143 VSUBPD	%YMM10,%YMM8,%YMM8

  (969) 0x452148 VMULPD	%YMM5,%YMM21,%YMM10

  (969) 0x45214e VFMADD231PD	%YMM8,%YMM26,%YMM10

  (969) 0x452154 VADDPD	%YMM16,%YMM17,%YMM16

  (969) 0x45215a VSUBPD	%YMM16,%YMM19,%YMM16

  (969) 0x452160 VADDPD	%YMM18,%YMM16,%YMM16

  (969) 0x452166 VBROADCASTSD	0x93dc0(%RIP),%YMM19

  (969) 0x452170 VMULPD	%YMM19,%YMM16,%YMM16

  (969) 0x452176 VADDPD	%YMM7,%YMM15,%YMM7

  (969) 0x45217a VSUBPD	%YMM7,%YMM20,%YMM7

  (969) 0x452180 VMOVAPD	%YMM13,%YMM20

  (969) 0x452186 VXORPD	%XMM13,%XMM13,%XMM13

  (969) 0x45218b VADDPD	%YMM4,%YMM7,%YMM4

  (969) 0x45218f VMULPD	%YMM19,%YMM4,%YMM4

  (969) 0x452195 VDIVPD	%YMM21,%YMM20,%YMM7

  (969) 0x45219b VMULPD	%YMM7,%YMM4,%YMM4

  (969) 0x45219f VFMADD231PD	%YMM16,%YMM28,%YMM4

  (969) 0x4521a5 VMOVUPD	(%RSI,%R12,8),%YMM15

  (969) 0x4521ab VSUBPD	-0x10(%RSI,%R12,8),%YMM15,%YMM15

  (969) 0x4521b2 VADDPD	(%R11,%R12,8),%YMM21,%YMM16

  (969) 0x4521b9 VMOVUPD	(%R14,%R12,8),%YMM17

  (969) 0x4521c0 VSUBPD	(%RDX,%R12,8),%YMM17,%YMM17

  (969) 0x4521c7 VDIVPD	%YMM16,%YMM15,%YMM18

  (969) 0x4521cd VMULPD	%YMM30,%YMM17,%YMM17

  (969) 0x4521d3 VMULPD	%YMM18,%YMM18,%YMM15

  (969) 0x4521d9 VMULPD	%YMM17,%YMM17,%YMM16

  (969) 0x4521df VMULPD	%YMM19,%YMM5,%YMM5

  (969) 0x4521e5 VMULPD	%YMM7,%YMM5,%YMM5

  (969) 0x4521e9 VMULPD	%YMM5,%YMM15,%YMM5

  (969) 0x4521ed VMULPD	%YMM19,%YMM8,%YMM7

  (969) 0x4521f3 VMULPD	%YMM16,%YMM7,%YMM7

  (969) 0x4521f9 VMULPD	%YMM4,%YMM18,%YMM4

  (969) 0x4521ff VFMADD213PD	%YMM5,%YMM17,%YMM4

  (969) 0x452205 VFMADD231PD	%YMM7,%YMM28,%YMM4

  (969) 0x45220b VADDPD	%YMM15,%YMM16,%YMM5

  (969) 0x452211 VMAXPD	%YMM1,%YMM5,%YMM5

  (969) 0x452215 VDIVPD	%YMM5,%YMM4,%YMM16

  (969) 0x45221b VCMPPD	$0x6,%YMM10,%YMM13,%K1

  (969) 0x452222 VCMPPD	$0x5,%YMM16,%YMM13,%K1{%K1}

  (969) 0x452229 KORTESTB	%K1,%K1

  (969) 0x45222d JE	451fb0

  (969) 0x452233 MOV	0x88(%RBP),%RDI

  (969) 0x45223a MOV	(%RDI),%RDI

  (969) 0x45223d JMP	451fb0

0x452242 NOPW	%CS:(%RAX,%RAX,1)

(967) 0x452250 VPCMPEQD	%YMM7,%YMM7,%YMM7

(967) 0x452254 VPTEST	%YMM7,%YMM0

(967) 0x452259 VMOVAPD	0x60(%RSP),%XMM13

(967) 0x45225f JB	45229f

(967) 0x452261 VEXTRACTI128	$0x1,%YMM0,%XMM4

(967) 0x452267 VPMAXSQ	%XMM4,%XMM0,%XMM4

(967) 0x45226d VPSHUFD	$-0x12,%XMM4,%XMM5

(967) 0x452272 VPMAXSQ	%XMM5,%XMM4,%XMM4

(967) 0x452278 VPBROADCASTQ	%XMM4,%YMM4

(967) 0x45227d VPCMPEQQ	%YMM4,%YMM0,%K0

(967) 0x452283 KMOVD	%K0,%EAX

(967) 0x452287 TZCNT	%EAX,%EAX

(967) 0x45228b VMOVAPD	%YMM31,0x280(%RSP)

(967) 0x452293 AND	$0x3,%EAX

(967) 0x452296 VMOVSD	0x280(%RSP,%RAX,8),%XMM13

(967) 0x45229f VPTEST	%YMM7,%YMM2

(967) 0x4522a4 VMOVAPD	0x1a0(%RSP),%XMM30

(967) 0x4522ac MOV	0x128(%RSP),%R14

(967) 0x4522b4 MOV	0x120(%RSP),%RDI

(967) 0x4522bc MOV	0x118(%RSP),%R10

(967) 0x4522c4 MOV	0x110(%RSP),%R15

(967) 0x4522cc JB	45230c

(967) 0x4522ce VEXTRACTI128	$0x1,%YMM2,%XMM0

(967) 0x4522d4 VPMAXSQ	%XMM0,%XMM2,%XMM0

(967) 0x4522da VPSHUFD	$-0x12,%XMM0,%XMM4

(967) 0x4522df VPMAXSQ	%XMM4,%XMM0,%XMM0

(967) 0x4522e5 VPBROADCASTQ	%XMM0,%YMM0

(967) 0x4522ea VPCMPEQQ	%YMM0,%YMM2,%K0

(967) 0x4522f0 KMOVD	%K0,%EAX

(967) 0x4522f4 TZCNT	%EAX,%EAX

(967) 0x4522f8 VMOVAPD	%YMM29,0x260(%RSP)

(967) 0x452300 AND	$0x3,%EAX

(967) 0x452303 VMOVSD	0x260(%RSP,%RAX,8),%XMM14

(967) 0x45230c VPTEST	%YMM7,%YMM9

(967) 0x452311 VMOVAPD	0x1b0(%RSP),%XMM19

(967) 0x452319 VMOVAPD	0x190(%RSP),%XMM31

(967) 0x452321 JB	452360

(967) 0x452323 VEXTRACTI128	$0x1,%YMM9,%XMM0

(967) 0x452329 VPMAXSQ	%XMM0,%XMM9,%XMM0

(967) 0x45232f VPSHUFD	$-0x12,%XMM0,%XMM2

(967) 0x452334 VPMAXSQ	%XMM2,%XMM0,%XMM0

(967) 0x45233a VPBROADCASTQ	%XMM0,%YMM0

(967) 0x45233f VPCMPEQQ	%YMM0,%YMM9,%K0

(967) 0x452345 KMOVD	%K0,%EAX

(967) 0x452349 TZCNT	%EAX,%EAX

(967) 0x45234d VMOVAPD	%YMM27,0x240(%RSP)

(967) 0x452355 AND	$0x3,%EAX

(967) 0x452358 VMOVSD	0x240(%RSP,%RAX,8),%XMM19

(967) 0x452360 VPTEST	%YMM7,%YMM6

(967) 0x452365 VMOVSD	0x92ecb(%RIP),%XMM15

(967) 0x45236d VMOVSD	0xafbe1(%RIP),%XMM16

(967) 0x452377 VMOVSD	0xafbdf(%RIP),%XMM17

(967) 0x452381 VMOVSD	0x93ba7(%RIP),%XMM1

(967) 0x452389 VXORPD	%XMM18,%XMM18,%XMM18

(967) 0x45238f VMOVAPD	0x180(%RSP),%XMM4

(967) 0x452398 JB	4523d7

(967) 0x45239a VEXTRACTI128	$0x1,%YMM6,%XMM0

(967) 0x4523a0 VPMAXSQ	%XMM0,%XMM6,%XMM0

(967) 0x4523a6 VPSHUFD	$-0x12,%XMM0,%XMM2

(967) 0x4523ab VPMAXSQ	%XMM2,%XMM0,%XMM0

(967) 0x4523b1 VPBROADCASTQ	%XMM0,%YMM0

(967) 0x4523b6 VPCMPEQQ	%YMM0,%YMM6,%K0

(967) 0x4523bc KMOVD	%K0,%EAX

(967) 0x4523c0 TZCNT	%EAX,%EAX

(967) 0x4523c4 VMOVAPD	%YMM25,0x220(%RSP)

(967) 0x4523cc AND	$0x3,%EAX

(967) 0x4523cf VMOVSD	0x220(%RSP,%RAX,8),%XMM30

(967) 0x4523d7 VPTEST	%YMM7,%YMM3

(967) 0x4523dc JB	452425

(967) 0x4523de VEXTRACTI128	$0x1,%YMM3,%XMM0

(967) 0x4523e4 VPMAXSQ	%XMM0,%XMM3,%XMM0

(967) 0x4523ea VPSHUFD	$-0x12,%XMM0,%XMM2

(967) 0x4523ef VPMAXSQ	%XMM2,%XMM0,%XMM0

(967) 0x4523f5 VPBROADCASTQ	%XMM0,%YMM0

(967) 0x4523fa VPCMPEQQ	%YMM0,%YMM3,%K0

(967) 0x452400 KMOVD	%K0,%EAX

(967) 0x452404 TZCNT	%EAX,%EAX

(967) 0x452408 VMOVAPD	%YMM24,0x200(%RSP)

(967) 0x452410 AND	$0x3,%EAX

(967) 0x452413 VMOVQ	0x200(%RSP,%RAX,8),%XMM0

(967) 0x45241c VMOVDQA	%XMM0,0x170(%RSP)

(967) 0x452425 VPTEST	%YMM7,%YMM11

(967) 0x45242a JB	452469

(967) 0x45242c VEXTRACTI128	$0x1,%YMM11,%XMM0

(967) 0x452432 VPMAXSQ	%XMM0,%XMM11,%XMM0

(967) 0x452438 VPSHUFD	$-0x12,%XMM0,%XMM2

(967) 0x45243d VPMAXSQ	%XMM2,%XMM0,%XMM0

(967) 0x452443 VPBROADCASTQ	%XMM0,%YMM0

(967) 0x452448 VPCMPEQQ	%YMM0,%YMM11,%K0

(967) 0x45244e KMOVD	%K0,%EAX

(967) 0x452452 TZCNT	%EAX,%EAX

(967) 0x452456 VMOVAPD	%YMM23,0x1e0(%RSP)

(967) 0x45245e AND	$0x3,%EAX

(967) 0x452461 VMOVSD	0x1e0(%RSP,%RAX,8),%XMM31

(967) 0x452469 VPTEST	%YMM7,%YMM12

(967) 0x45246e JB	4524b7

(967) 0x452470 VEXTRACTI128	$0x1,%YMM12,%XMM0

(967) 0x452476 VPMAXSQ	%XMM0,%XMM12,%XMM0

(967) 0x45247c VPSHUFD	$-0x12,%XMM0,%XMM2

(967) 0x452481 VPMAXSQ	%XMM2,%XMM0,%XMM0

(967) 0x452487 VPBROADCASTQ	%XMM0,%YMM0

(967) 0x45248c VPCMPEQQ	%YMM0,%YMM12,%K0

(967) 0x452492 KMOVD	%K0,%EAX

(967) 0x452496 TZCNT	%EAX,%EAX

(967) 0x45249a VMOVAPD	%YMM22,0x1c0(%RSP)

(967) 0x4524a2 AND	$0x3,%EAX

(967) 0x4524a5 VMOVQ	0x1c0(%RSP,%RAX,8),%XMM0

(967) 0x4524ae VMOVDQA	%XMM0,0x160(%RSP)

(967) 0x4524b7 MOV	0x20(%RSP),%RAX

(967) 0x4524bc MOV	%RAX,%RDX

(967) 0x4524bf CMP	0x48(%RSP),%EAX

(967) 0x4524c3 VMOVSD	0x130(%RSP),%XMM2

(967) 0x4524cc JE	451d70

(967) 0x4524d2 JMP	452514

0x4524d4 NOPW	%CS:(%RAX,%RAX,1)

(967) 0x4524e0 SUB	0x40(%RSP),%R13

(967) 0x4524e5 MOV	%R9,%RAX

(967) 0x4524e8 IMUL	%R13,%RAX

(967) 0x4524ec MOV	%RAX,0x50(%RSP)

(967) 0x4524f1 LEA	0x1(%R13),%R15

(967) 0x4524f5 IMUL	%R15,%R9

(967) 0x4524f9 MOV	%R9,0x58(%RSP)

(967) 0x4524fe MOV	%R12,%RAX

(967) 0x452501 IMUL	%R13,%RAX

(967) 0x452505 MOV	%RAX,0x18(%RSP)

(967) 0x45250a IMUL	%R12,%R15

(967) 0x45250e IMUL	%RDI,%R13

(967) 0x452512 XOR	%EDX,%EDX

(967) 0x452514 MOV	0x10(%RBP),%RCX

(967) 0x452518 MOV	0x50(%RSP),%R12

(967) 0x45251d ADD	%RCX,%R12

(967) 0x452520 MOV	0xe0(%RSP),%RAX

(967) 0x452528 MOV	%RDX,0x60(%RSP)

(967) 0x45252d ADD	%RAX,%RDX

(967) 0x452530 MOV	%RDX,%R9

(967) 0x452533 MOV	0xd8(%RSP),%RSI

(967) 0x45253b SUB	%RSI,%R9

(967) 0x45253e VMOVSD	(%R12,%R9,8),%XMM3

(967) 0x452544 MOV	0x58(%RSP),%RAX

(967) 0x452549 ADD	%RCX,%RAX

(967) 0x45254c VMOVSD	(%RAX,%R9,8),%XMM12

(967) 0x452552 MOV	0x18(%RBP),%RAX

(967) 0x452556 MOV	0x18(%RSP),%RCX

(967) 0x45255b ADD	%RAX,%RCX

(967) 0x45255e VMOVSD	(%RCX,%R9,8),%XMM11

(967) 0x452564 NOT	%RSI

(967) 0x452567 ADD	%RDX,%RSI

(967) 0x45256a ADD	%RAX,%R15

(967) 0x45256d VMOVSD	(%R15,%R9,8),%XMM6

(967) 0x452573 IMUL	%R8,%R10

(967) 0x452577 LEA	(%R10,%RDX,8),%RAX

(967) 0x45257b MOV	0xc0(%RSP),%RCX

(967) 0x452583 LEA	(%RCX,%RDX,8),%RCX

(967) 0x452587 MOV	%RCX,0x18(%RSP)

(967) 0x45258c ADD	0x28(%RBP),%R13

(967) 0x452590 VMOVSD	(%R13,%RSI,8),%XMM24

(967) 0x452598 IMUL	%RDI,%R14

(967) 0x45259c LEA	(%R14,%RDX,8),%R10

(967) 0x4525a0 MOV	%RDI,%RSI

(967) 0x4525a3 IMUL	%RBX,%RSI

(967) 0x4525a7 LEA	(%RSI,%RDX,8),%RSI

(967) 0x4525ab VMOVSD	(%R13,%R9,8),%XMM22

(967) 0x4525b3 IMUL	%R8,%RDI

(967) 0x4525b7 LEA	(%RDI,%RDX,8),%RDI

(967) 0x4525bb MOV	0x140(%RSP),%RCX

(967) 0x4525c3 MOV	%RCX,%R14

(967) 0x4525c6 IMUL	%R8,%R14

(967) 0x4525ca LEA	(%R14,%RDX,8),%R13

(967) 0x4525ce IMUL	%RBX,%RCX

(967) 0x4525d2 LEA	(%RCX,%RDX,8),%R12

(967) 0x4525d6 MOV	0x148(%RSP),%RCX

(967) 0x4525de IMUL	%RCX,%RBX

(967) 0x4525e2 LEA	(%RBX,%RDX,8),%RBX

(967) 0x4525e6 IMUL	%R8,%RCX

(967) 0x4525ea LEA	(%RCX,%RDX,8),%R14

(967) 0x4525ee MOV	0xb0(%RSP),%RCX

(967) 0x4525f6 LEA	(%RCX,%RDX,8),%R15

(967) 0x4525fa MOV	0x40(%RBP),%RCX

(967) 0x4525fe VMOVSD	(%RCX,%R9,8),%XMM0

(967) 0x452604 VDIVSD	%XMM4,%XMM15,%XMM9

(967) 0x452608 VDIVSD	%XMM2,%XMM15,%XMM2

(967) 0x45260c MOV	0x48(%RSP),%RDX

(967) 0x452611 SUB	0x60(%RSP),%RDX

(967) 0x452616 ADD	0xb8(%RSP),%RAX

(967) 0x45261e MOV	0xd0(%RSP),%RCX

(967) 0x452626 ADD	%RCX,%R10

(967) 0x452629 ADD	%RCX,%RSI

(967) 0x45262c ADD	0xa8(%RSP),%RDI

(967) 0x452634 MOV	0xa0(%RSP),%RCX

(967) 0x45263c ADD	%RCX,%R13

(967) 0x45263f ADD	%RCX,%R12

(967) 0x452642 MOV	0xc8(%RSP),%RCX

(967) 0x45264a ADD	%RCX,%RBX

(967) 0x45264d ADD	%RCX,%R14

(967) 0x452650 XOR	%R9D,%R9D

(967) 0x452653 JMP	452679

0x452655 NOPW	%CS:(%RAX,%RAX,1)

  (968) 0x452660 VMOVSD	%XMM26,(%RAX,%R9,8)

  (968) 0x452667 INC	%R9

  (968) 0x45266a VMOVAPD	%XMM23,%XMM24

  (968) 0x452670 CMP	%R9,%RDX

  (968) 0x452673 JE	451d70

  (968) 0x452679 VMOVAPD	%XMM22,%XMM23

  (968) 0x45267f VMOVAPD	%XMM0,%XMM25

  (968) 0x452685 VMOVAPD	%XMM6,%XMM0

  (968) 0x452689 VMOVAPD	%XMM11,%XMM4

  (968) 0x45268d VMOVAPD	%XMM12,%XMM5

  (968) 0x452691 VMOVAPD	%XMM3,%XMM7

  (968) 0x452695 VMOVSD	(%R14,%R9,8),%XMM11

  (968) 0x45269b VMOVSD	(%RBX,%R9,8),%XMM6

  (968) 0x4526a1 VADDSD	%XMM6,%XMM11,%XMM8

  (968) 0x4526a5 VADDSD	%XMM0,%XMM4,%XMM10

  (968) 0x4526a9 VMOVSD	(%R12,%R9,8),%XMM12

  (968) 0x4526af VMOVSD	(%R13,%R9,8),%XMM3

  (968) 0x4526b6 VSUBSD	%XMM10,%XMM8,%XMM29

  (968) 0x4526bc VADDSD	%XMM5,%XMM12,%XMM8

  (968) 0x4526c0 VADDSD	%XMM3,%XMM7,%XMM10

  (968) 0x4526c4 VSUBSD	%XMM10,%XMM8,%XMM28

  (968) 0x4526ca VADDSD	%XMM4,%XMM11,%XMM4

  (968) 0x4526ce VSUBSD	%XMM4,%XMM6,%XMM4

  (968) 0x4526d2 VADDSD	%XMM0,%XMM4,%XMM0

  (968) 0x4526d6 VMULSD	%XMM1,%XMM0,%XMM0

  (968) 0x4526da VADDSD	%XMM7,%XMM5,%XMM4

  (968) 0x4526de VSUBSD	%XMM4,%XMM12,%XMM4

  (968) 0x4526e2 VADDSD	%XMM3,%XMM4,%XMM4

  (968) 0x4526e6 VMULSD	%XMM1,%XMM4,%XMM4

  (968) 0x4526ea VDIVSD	%XMM25,%XMM15,%XMM5

  (968) 0x4526f0 VMULSD	%XMM5,%XMM4,%XMM4

  (968) 0x4526f4 VFMADD231SD	%XMM0,%XMM9,%XMM4

  (968) 0x4526f9 VMOVSD	(%RDI,%R9,8),%XMM22

  (968) 0x452700 VSUBSD	%XMM24,%XMM22,%XMM7

  (968) 0x452706 VMOVSD	(%R15,%R9,8),%XMM0

  (968) 0x45270c VADDSD	%XMM25,%XMM0,%XMM8

  (968) 0x452712 VDIVSD	%XMM8,%XMM7,%XMM27

  (968) 0x452718 VMOVSD	(%RSI,%R9,8),%XMM7

  (968) 0x45271e VSUBSD	(%R10,%R9,8),%XMM7,%XMM7

  (968) 0x452724 VMULSD	%XMM2,%XMM7,%XMM24

  (968) 0x45272a VMULSD	%XMM27,%XMM27,%XMM7

  (968) 0x452730 VMULSD	%XMM24,%XMM24,%XMM8

  (968) 0x452736 VMULSD	%XMM1,%XMM29,%XMM10

  (968) 0x45273c VMULSD	%XMM5,%XMM10,%XMM5

  (968) 0x452740 VMULSD	%XMM7,%XMM5,%XMM5

  (968) 0x452744 VMULSD	%XMM1,%XMM28,%XMM10

  (968) 0x45274a VMULSD	%XMM8,%XMM10,%XMM10

  (968) 0x45274f VMULSD	%XMM4,%XMM27,%XMM4

  (968) 0x452755 VFMADD213SD	%XMM5,%XMM24,%XMM4

  (968) 0x45275b VFMADD231SD	%XMM10,%XMM9,%XMM4

  (968) 0x452760 VADDSD	%XMM7,%XMM8,%XMM5

  (968) 0x452764 VMAXSD	%XMM16,%XMM5,%XMM5

  (968) 0x45276a VDIVSD	%XMM5,%XMM4,%XMM21

  (968) 0x452770 VXORPD	%XMM26,%XMM26,%XMM26

  (968) 0x452776 VUCOMISD	%XMM26,%XMM21

  (968) 0x45277c JA	452660

  (968) 0x452782 VMULSD	%XMM29,%XMM25,%XMM4

  (968) 0x452788 VMOVAPD	0x180(%RSP),%XMM10

  (968) 0x452791 VFMADD213SD	%XMM4,%XMM10,%XMM28

  (968) 0x452797 VUCOMISD	%XMM18,%XMM28

  (968) 0x45279d JAE	452660

  (968) 0x4527a3 VCMPSD	$0x1,%XMM18,%XMM27,%K1

  (968) 0x4527aa VMOVAPD	%XMM15,%XMM13

  (968) 0x4527af VMOVSD	%XMM17,%XMM13,%XMM13{%K1}

  (968) 0x4527b5 VMOVDDUP	0x928f3(%RIP),%XMM4

  (968) 0x4527bd VANDPD	%XMM4,%XMM27,%XMM5

  (968) 0x4527c3 VMAXSD	%XMM16,%XMM5,%XMM5

  (968) 0x4527c9 VMULSD	%XMM5,%XMM13,%XMM5

  (968) 0x4527cd VCMPSD	$0x1,%XMM18,%XMM5,%K1

  (968) 0x4527d4 VMOVAPD	%XMM15,%XMM14

  (968) 0x4527d9 VMOVSD	%XMM17,%XMM14,%XMM14{%K1}

  (968) 0x4527df VANDPD	%XMM4,%XMM24,%XMM7

  (968) 0x4527e5 VMAXSD	%XMM16,%XMM7,%XMM7

  (968) 0x4527eb VMULSD	%XMM7,%XMM14,%XMM7

  (968) 0x4527ef VMULSD	%XMM5,%XMM5,%XMM8

  (968) 0x4527f3 VFMADD231SD	%XMM7,%XMM7,%XMM8

  (968) 0x4527f8 VSQRTSD	%XMM8,%XMM8,%XMM19

  (968) 0x4527fe VMULSD	%XMM25,%XMM19,%XMM8

  (968) 0x452804 VDIVSD	%XMM5,%XMM8,%XMM5

  (968) 0x452808 VANDPD	%XMM4,%XMM5,%XMM30

  (968) 0x45280e VMULSD	%XMM10,%XMM19,%XMM5

  (968) 0x452814 VDIVSD	%XMM7,%XMM5,%XMM5

  (968) 0x452818 VANDPD	%XMM4,%XMM5,%XMM4

  (968) 0x45281c VMOVAPD	%XMM4,0x170(%RSP)

  (968) 0x452825 VMINSD	%XMM4,%XMM30,%XMM31

  (968) 0x45282b VMULSD	%XMM31,%XMM31,%XMM5

  (968) 0x452831 VMULSD	%XMM21,%XMM21,%XMM4

  (968) 0x452837 VMOVAPD	%XMM5,0x160(%RSP)

  (968) 0x452840 VADDSD	%XMM5,%XMM5,%XMM5

  (968) 0x452844 VMULSD	%XMM5,%XMM4,%XMM4

  (968) 0x452848 MOV	0x88(%RBP),%RCX

  (968) 0x45284f MOV	(%RCX),%RCX

  (968) 0x452852 IMUL	%R8,%RCX

  (968) 0x452856 ADD	0x18(%RSP),%RCX

  (968) 0x45285b VMULSD	(%RCX,%R9,8),%XMM4,%XMM26

  (968) 0x452862 JMP	452660

0x452867 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	viscosity_kernel.f90:50-94
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:50-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 3.00 cycles (8.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:94
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:94
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:54

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:94

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 148 bytes. The binary function is storing 224 bytes.

General properties

nb instructions	146
nb uops	150
loop length	700
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	0
nb stack references	46

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.00 cycles
front end	25.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.10	9.00	10.00	10.00	21.50	9.07	8.90	21.50	21.50	21.50	8.93	10.00
cycles	9.10	13.37	10.00	10.00	21.50	9.07	8.90	21.50	21.50	21.50	8.93	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.00
Dispatch	21.50
Overall L1	25.00

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	16%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

INT

all	11%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	11%
load	10%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

3% of peak load performance is reached (5.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (8.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.00 to 21.50 cycles (1.16x speedup).

ASM code

In the binary file, the address of the function is: 451af0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x2c0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 451b95 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0xa5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,0x14(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x44(%RSP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1c(%RSP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RSP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x52d630,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x14(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JAE 451bb0 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x52d650,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x2c(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x52d670,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4047c0 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EBX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x2(%R12),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %RAX,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RCX),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVGE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffffc,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R12D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %R15D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA -0x2(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RDI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SUB %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x2,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x18,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,0xe8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $-0x2,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x18(%R9,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x10(%R10,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x10(%RDX,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x10(%R9,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x18(%RCX,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA 0x18(%R14,%RAX,1),%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R15,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R14,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RBX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x9350a(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x941fa(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0218(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0216(%RIP),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VBROADCASTSD 0x934e4(%RIP),%YMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0x108(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 451d8d <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x29d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	viscosity_kernel.f90:50-94
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 3.00 cycles (8.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:94
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:94
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:54

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:94

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 148 bytes. The binary function is storing 224 bytes.

General properties

nb instructions	146
nb uops	150
loop length	700
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	0
nb stack references	46

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.00 cycles
front end	25.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.10	9.00	10.00	10.00	21.50	9.07	8.90	21.50	21.50	21.50	8.93	10.00
cycles	9.10	13.37	10.00	10.00	21.50	9.07	8.90	21.50	21.50	21.50	8.93	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.00
Dispatch	21.50
Overall L1	25.00

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	16%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

INT

all	11%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	11%
load	10%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

3% of peak load performance is reached (5.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (8.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 451af0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x2c0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 451b95 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0xa5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,0x14(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x44(%RSP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1c(%RSP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RSP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x52d630,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x14(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JAE 451bb0 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x52d650,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x2c(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x52d670,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4047c0 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EBX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x2(%R12),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %RAX,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RCX),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVGE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffffc,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R12D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %R15D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA -0x2(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RDI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SUB %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x2,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x18,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,0xe8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $-0x2,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x18(%R9,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x10(%R10,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x10(%RDX,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x10(%R9,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x18(%RCX,%RAX,1),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA 0x18(%R14,%RAX,1),%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R15,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R9,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R14,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RBX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x9350a(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x941fa(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0218(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0216(%RIP),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VBROADCASTSD 0x934e4(%RIP),%YMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0x108(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 451d8d <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x29d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2–	2.22	0.83
▼Loop 967 - viscosity_kernel.f90:53-89 - exec–	0.00	0.00
○Loop 969 - viscosity_kernel.f90:53-89 - exec	2.22	0.83
○Loop 968 - viscosity_kernel.f90:55-89 - exec	0.00	0.00

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512-bits vectorization

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CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code