OV - exec - Function revert_kernel_module_mp_revert_kernel

	Function: revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2	Module: exec	Source: revert_kernel.f90:41-51	Coverage (incl. loops): 2.56% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90: 41 - 51

--------------------------------------------------------------------------------

41:     !$OMP PARALLEL

42:

43:     !$OMP DO

44:     DO k=y_min,y_max

45:     !$OMP SIMD

46:       DO j=x_min,x_max

47:         density1(j,k)=density0(j,k)

48:         energy1(j,k)=energy0(j,k)

49:       ENDDO

50:     ENDDO

51:   !$OMP END DO

0x4306c0 PUSH	%RBP

0x4306c1 MOV	%RSP,%RBP

0x4306c4 PUSH	%R15

0x4306c6 PUSH	%R14

0x4306c8 PUSH	%R13

0x4306ca PUSH	%R12

0x4306cc PUSH	%RBX

0x4306cd SUB	$0xa8,%RSP

0x4306d4 MOV	0x68(%RBP),%RAX

0x4306d8 MOV	%RAX,-0xc8(%RBP)

0x4306df MOV	0x60(%RBP),%RAX

0x4306e3 MOV	%RAX,-0xc0(%RBP)

0x4306ea MOV	0x58(%RBP),%RAX

0x4306ee MOV	%RAX,-0xb8(%RBP)

0x4306f5 MOV	0x50(%RBP),%RAX

0x4306f9 MOV	%RAX,-0xb0(%RBP)

0x430700 MOV	0x48(%RBP),%R14

0x430704 MOV	0x40(%RBP),%RBX

0x430708 MOV	0x28(%RBP),%RAX

0x43070c MOV	%RAX,-0x50(%RBP)

0x430710 MOV	0x20(%RBP),%RDX

0x430714 MOV	0x38(%RBP),%R12D

0x430718 MOV	0x30(%RBP),%EAX

0x43071b SUB	%R12D,%EAX

0x43071e MOV	0x18(%RBP),%R13

0x430722 MOV	0x10(%RBP),%R15

0x430726 MOVL	$0,-0x64(%RBP)

0x43072d JS	43079f

0x43072f MOV	%RCX,-0x48(%RBP)

0x430733 MOV	%R9,-0x58(%RBP)

0x430737 MOV	%RDX,-0x40(%RBP)

0x43073b MOV	%RDI,-0x78(%RBP)

0x43073f MOV	(%RDI),%ESI

0x430741 MOVL	$0,-0x34(%RBP)

0x430748 MOV	%EAX,-0x30(%RBP)

0x43074b MOVL	$0x1,-0x60(%RBP)

0x430752 SUB	$0x8,%RSP

0x430756 LEA	-0x60(%RBP),%RAX

0x43075a LEA	-0x64(%RBP),%RCX

0x43075e LEA	-0x34(%RBP),%R8

0x430762 LEA	-0x30(%RBP),%R9

0x430766 MOV	$0x529090,%EDI

0x43076b MOV	%ESI,-0x5c(%RBP)

0x43076e MOV	$0x22,%EDX

0x430773 PUSH	$0x1

0x430775 PUSH	$0x1

0x430777 PUSH	%RAX

0x430778 CALL	404850 <__kmpc_for_static_init_4@plt>

0x43077d ADD	$0x20,%RSP

0x430781 MOV	-0x34(%RBP),%EAX

0x430784 MOV	-0x30(%RBP),%ECX

0x430787 SUB	%EAX,%ECX

0x430789 JAE	4307bc

0x43078b MOV	$0x5290b0,%EDI

0x430790 MOV	-0x5c(%RBP),%ESI

0x430793 VZEROUPPER

0x430796 CALL	404070 <__kmpc_for_static_fini@plt>

0x43079b MOV	-0x78(%RBP),%RDI

0x43079f MOV	(%RDI),%ESI

0x4307a1 MOV	$0x5290d0,%EDI

0x4307a6 ADD	$0xa8,%RSP

0x4307ad POP	%RBX

0x4307ae POP	%R12

0x4307b0 POP	%R13

0x4307b2 POP	%R14

0x4307b4 POP	%R15

0x4307b6 POP	%RBP

0x4307b7 JMP	4047c0

0x4307bc MOVSXD	(%R14),%RDI

0x4307bf MOV	%ECX,-0x2c(%RBP)

0x4307c2 MOV	(%RBX),%ECX

0x4307c4 SUB	%EDI,%ECX

0x4307c6 LEA	0x1(%RCX),%EDX

0x4307c9 CMP	$0x2,%EDX

0x4307cc MOV	$0x1,%R8D

0x4307d2 CMOVGE	%EDX,%R8D

0x4307d6 MOV	%R8,-0x70(%RBP)

0x4307da AND	$0x7ffffffc,%R8D

0x4307e1 MOVSXD	-0x48(%RBP),%RDX

0x4307e5 MOVSXD	-0x58(%RBP),%RSI

0x4307e9 MOV	%RDI,-0xa0(%RBP)

0x4307f0 LEA	(,%RDI,8),%RDI

0x4307f8 SAL	$0x3,%RSI

0x4307fc SUB	%RSI,%RDI

0x4307ff MOV	%R15,%R9

0x430802 LEA	(%R15,%RDI,1),%R10

0x430806 ADD	$0x10,%R10

0x43080a MOV	%R10,-0x98(%RBP)

0x430811 MOV	$0x2,%R10D

0x430817 SUB	%RDX,%R10

0x43081a MOV	%R10,-0x58(%RBP)

0x43081e ADD	%R12D,%EAX

0x430821 LEA	(%RDI,%R13,1),%RDX

0x430825 ADD	$0x10,%RDX

0x430829 MOV	%RDX,-0x90(%RBP)

0x430830 MOV	$0x10,%EDX

0x430835 SUB	%RSI,%RDX

0x430838 MOV	%RCX,%RSI

0x43083b MOV	-0x2c(%RBP),%ECX

0x43083e MOV	-0x40(%RBP),%R11

0x430842 LEA	(%R11,%RDI,1),%R10

0x430846 ADD	$0x10,%R10

0x43084a MOV	%R10,-0x88(%RBP)

0x430851 MOV	-0x50(%RBP),%R15

0x430855 ADD	%R15,%RDI

0x430858 ADD	$0x10,%RDI

0x43085c MOV	%RDI,-0x80(%RBP)

0x430860 ADD	%RDX,%R13

0x430863 MOV	%R13,-0x48(%RBP)

0x430867 ADD	%RDX,%R9

0x43086a MOV	%R9,-0xa8(%RBP)

0x430871 ADD	%RDX,%R15

0x430874 MOV	%R15,-0x50(%RBP)

0x430878 ADD	%R11,%RDX

0x43087b MOV	%RDX,-0x40(%RBP)

0x43087f XOR	%R11D,%R11D

0x430882 JMP	4308a2

0x430884 NOPW	%CS:(%RAX,%RAX,1)

(388) 0x430890 LEA	0x1(%R11),%EDX

(388) 0x430894 INC	%EAX

(388) 0x430896 CMP	%ECX,%R11D

(388) 0x430899 MOV	%EDX,%R11D

(388) 0x43089c JE	43078b

(388) 0x4308a2 TEST	%ESI,%ESI

(388) 0x4308a4 JS	430890

(388) 0x4308a6 MOVSXD	%EAX,%R12

(388) 0x4308a9 ADD	-0x58(%RBP),%R12

(388) 0x4308ad MOV	-0xb0(%RBP),%RDX

(388) 0x4308b4 MOV	(%RDX),%R15

(388) 0x4308b7 MOV	-0xb8(%RBP),%RDX

(388) 0x4308be MOV	(%RDX),%R10

(388) 0x4308c1 MOV	-0xc0(%RBP),%RDX

(388) 0x4308c8 MOV	(%RDX),%RBX

(388) 0x4308cb MOV	-0xc8(%RBP),%RDX

(388) 0x4308d2 MOV	(%RDX),%R14

(388) 0x4308d5 TEST	%R8,%R8

(388) 0x4308d8 JE	430960

(388) 0x4308de MOV	%RSI,%RCX

(388) 0x4308e1 MOV	%R14,%RDI

(388) 0x4308e4 IMUL	%R12,%RDI

(388) 0x4308e8 ADD	-0x98(%RBP),%RDI

(388) 0x4308ef MOV	%RBX,%R9

(388) 0x4308f2 IMUL	%R12,%R9

(388) 0x4308f6 ADD	-0x90(%RBP),%R9

(388) 0x4308fd MOV	%R10,%RDX

(388) 0x430900 IMUL	%R12,%RDX

(388) 0x430904 ADD	-0x88(%RBP),%RDX

(388) 0x43090b MOV	%R15,%R13

(388) 0x43090e IMUL	%R12,%R13

(388) 0x430912 ADD	-0x80(%RBP),%R13

(388) 0x430916 XOR	%ESI,%ESI

(388) 0x430918 NOPL	(%RAX,%RAX,1)

  (390) 0x430920 VMOVUPS	(%R13,%RSI,8),%YMM0

  (390) 0x430927 VMOVUPS	%YMM0,(%RDX,%RSI,8)

  (390) 0x43092c VMOVUPS	(%R9,%RSI,8),%YMM0

  (390) 0x430932 VMOVUPS	%YMM0,(%RDI,%RSI,8)

  (390) 0x430937 ADD	$0x4,%RSI

  (390) 0x43093b CMP	%R8,%RSI

  (390) 0x43093e JB	430920

(388) 0x430940 MOV	%R8,%R9

(388) 0x430943 CMP	-0x70(%RBP),%R8D

(388) 0x430947 MOV	%RCX,%RSI

(388) 0x43094a MOV	-0x2c(%RBP),%ECX

(388) 0x43094d JE	430890

(388) 0x430953 JMP	430963

0x430955 NOPW	%CS:(%RAX,%RAX,1)

(388) 0x430960 XOR	%R9D,%R9D

(388) 0x430963 MOV	-0x70(%RBP),%RDI

(388) 0x430967 SUB	%R9,%RDI

(388) 0x43096a IMUL	%R12,%RBX

(388) 0x43096e ADD	-0xa0(%RBP),%R9

(388) 0x430975 LEA	(%RBX,%R9,8),%RBX

(388) 0x430979 ADD	-0x48(%RBP),%RBX

(388) 0x43097d IMUL	%R12,%R14

(388) 0x430981 LEA	(%R14,%R9,8),%R14

(388) 0x430985 ADD	-0xa8(%RBP),%R14

(388) 0x43098c IMUL	%R12,%R15

(388) 0x430990 LEA	(%R15,%R9,8),%R13

(388) 0x430994 ADD	-0x50(%RBP),%R13

(388) 0x430998 IMUL	%R12,%R10

(388) 0x43099c LEA	(%R10,%R9,8),%RDX

(388) 0x4309a0 ADD	-0x40(%RBP),%RDX

(388) 0x4309a4 XOR	%R9D,%R9D

(388) 0x4309a7 NOPW	(%RAX,%RAX,1)

  (389) 0x4309b0 VMOVSD	(%R13,%R9,8),%XMM0

  (389) 0x4309b7 VMOVSD	%XMM0,(%RDX,%R9,8)

  (389) 0x4309bd VMOVSD	(%RBX,%R9,8),%XMM0

  (389) 0x4309c3 VMOVSD	%XMM0,(%R14,%R9,8)

  (389) 0x4309c9 INC	%R9

  (389) 0x4309cc CMP	%R9,%RDI

  (389) 0x4309cf JNE	4309b0

(388) 0x4309d1 JMP	430890

0x4309d6 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►99.99+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	revert_kernel.f90:41-51
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:41-51.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 20.50 to 1.78 cycles (11.51x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:51
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:45

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:51

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	120
nb uops	123
loop length	485
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.60	5.60	10.33	10.33	18.50	5.60	5.60	18.50	18.50	18.50	5.60	10.33
cycles	5.60	5.60	10.33	10.33	18.50	5.60	5.60	18.50	18.50	18.50	5.60	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.50
Dispatch	18.50
Overall L1	20.50

Vectorization ratios

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

all	10%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.50 cycles. At this rate:

3% of peak load performance is reached (7.41 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (8.98 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.50 to 18.50 cycles (1.11x speedup).

ASM code

In the binary file, the address of the function is: 4306c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x18(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x64(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 43079f <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0xdf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x64(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x34(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x529090,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x5c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x34(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 4307bc <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0xfc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x5290b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x5c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x5290d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4047c0 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOVSXD (%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ECX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RBX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RCX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVGE %EDX,%R8D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffffc,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOVSXD -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD -0x58(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
SUB %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R15,%RDI,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x2,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDI,%R13,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x10,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x2c(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%RDI,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R15,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4308a2 <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0x1e2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	revert_kernel.f90:41-51
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:51
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:45

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:51

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	120
nb uops	123
loop length	485
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.60	5.60	10.33	10.33	18.50	5.60	5.60	18.50	18.50	18.50	5.60	10.33
cycles	5.60	5.60	10.33	10.33	18.50	5.60	5.60	18.50	18.50	18.50	5.60	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.50
Dispatch	18.50
Overall L1	20.50

Vectorization ratios

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

all	10%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.50 cycles. At this rate:

3% of peak load performance is reached (7.41 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (8.98 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4306c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x18(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x64(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 43079f <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0xdf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x64(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x34(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x529090,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x5c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x34(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 4307bc <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0xfc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x5290b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x5c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x5290d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4047c0 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOVSXD (%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ECX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RBX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RCX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVGE %EDX,%R8D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffffc,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOVSXD -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD -0x58(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
SUB %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R15,%RDI,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x2,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDI,%R13,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x10,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x2c(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%RDI,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R15,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4308a2 <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0x1e2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2–	2.56	0.96
▼Loop 388 - revert_kernel.f90:44-48 - exec–	0.00	0.00
○Loop 390 - revert_kernel.f90:46-48 - exec	2.56	0.95
○Loop 389 - revert_kernel.f90:46-48 - exec	0.00	0.00

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