OV - exec - Function pack_kernel_module_mp_clover_pack_message_right

	Function: pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97	Module: exec	Source: pack_kernel.f90:155-163	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 155 - 163

--------------------------------------------------------------------------------

155:     !$OMP PARALLEL DO PRIVATE(index)

156:     DO k=y_min-depth,y_max+y_inc+depth

157:     !$OMP SIMD

158:       DO j=1,depth

159:         index= buffer_offset + j+(k+depth-1)*depth

160:         right_snd_buffer(index)=field(x_max+1-j,k)

161:       ENDDO

162:     ENDDO

163:   !$OMP END PARALLEL DO

0x42c8c0 PUSH	%RBP

0x42c8c1 MOV	%RSP,%RBP

0x42c8c4 PUSH	%R15

0x42c8c6 PUSH	%R14

0x42c8c8 PUSH	%R13

0x42c8ca PUSH	%R12

0x42c8cc PUSH	%RBX

0x42c8cd SUB	$0x58,%RSP

0x42c8d1 MOV	%R9,-0x70(%RBP)

0x42c8d5 MOV	%RCX,-0x68(%RBP)

0x42c8d9 MOV	0x18(%RBP),%RAX

0x42c8dd MOV	%RAX,-0x60(%RBP)

0x42c8e1 MOV	0x10(%RBP),%RAX

0x42c8e5 MOV	%RAX,-0x58(%RBP)

0x42c8e9 MOV	0x28(%RBP),%EAX

0x42c8ec MOVL	$0,-0x40(%RBP)

0x42c8f3 TEST	%EAX,%EAX

0x42c8f5 JS	42c967

0x42c8f7 MOV	%R8,%R13

0x42c8fa MOV	%RDX,%R14

0x42c8fd MOV	(%RDI),%ESI

0x42c8ff MOVL	$0,-0x30(%RBP)

0x42c906 MOV	%EAX,-0x2c(%RBP)

0x42c909 MOVL	$0x1,-0x3c(%RBP)

0x42c910 SUB	$0x8,%RSP

0x42c914 LEA	-0x3c(%RBP),%RAX

0x42c918 LEA	-0x40(%RBP),%RCX

0x42c91c LEA	-0x30(%RBP),%R8

0x42c920 LEA	-0x2c(%RBP),%R9

0x42c924 MOV	$0x5288b0,%EDI

0x42c929 MOV	%ESI,-0x34(%RBP)

0x42c92c MOV	$0x22,%EDX

0x42c931 PUSH	$0x1

0x42c933 PUSH	$0x1

0x42c935 PUSH	%RAX

0x42c936 CALL	404850 <__kmpc_for_static_init_4@plt>

0x42c93b ADD	$0x20,%RSP

0x42c93f MOV	-0x30(%RBP),%ECX

0x42c942 MOV	-0x2c(%RBP),%EBX

0x42c945 SUB	%ECX,%EBX

0x42c947 JAE	42c976

0x42c949 MOV	$0x5288d0,%EDI

0x42c94e MOV	-0x34(%RBP),%ESI

0x42c951 ADD	$0x58,%RSP

0x42c955 POP	%RBX

0x42c956 POP	%R12

0x42c958 POP	%R13

0x42c95a POP	%R14

0x42c95c POP	%R15

0x42c95e POP	%RBP

0x42c95f VZEROUPPER

0x42c962 JMP	404070

0x42c967 ADD	$0x58,%RSP

0x42c96b POP	%RBX

0x42c96c POP	%R12

0x42c96e POP	%R13

0x42c970 POP	%R14

0x42c972 POP	%R15

0x42c974 POP	%RBP

0x42c975 RET

0x42c976 MOV	%RCX,%RAX

0x42c979 MOV	(%R13),%R15D

0x42c97d ADD	%R14D,%EAX

0x42c980 MOV	%R15D,%ESI

0x42c983 AND	$0x7ffffffc,%ESI

0x42c989 MOV	%RAX,-0x50(%RBP)

0x42c98d ADD	%R15D,%EAX

0x42c990 DEC	%EAX

0x42c992 IMUL	%R15D,%EAX

0x42c996 XOR	%EDI,%EDI

0x42c998 VPMOVSXBD	0xc119f(%RIP),%XMM0

0x42c9a1 VPCMPEQD	%YMM1,%YMM1,%YMM1

0x42c9a5 VPMOVSXBQ	0xb9392(%RIP),%YMM2

0x42c9ae MOV	%EBX,-0x38(%RBP)

0x42c9b1 MOV	%R15,-0x48(%RBP)

0x42c9b5 JMP	42c9d1

0x42c9b7 NOPW	(%RAX,%RAX,1)

(331) 0x42c9c0 LEA	0x1(%RDI),%ECX

(331) 0x42c9c3 LEA	(%R15,%R8,1),%EAX

(331) 0x42c9c7 CMP	%EBX,%EDI

(331) 0x42c9c9 MOV	%ECX,%EDI

(331) 0x42c9cb JE	42c949

(331) 0x42c9d1 MOVSXD	%EAX,%R8

(331) 0x42c9d4 TEST	%R15D,%R15D

(331) 0x42c9d7 JLE	42c9c0

(331) 0x42c9d9 MOV	-0x50(%RBP),%RAX

(331) 0x42c9dd LEA	(%RAX,%RDI,1),%ECX

(331) 0x42c9e0 MOV	-0x68(%RBP),%RAX

(331) 0x42c9e4 MOVSXD	(%RAX),%R12

(331) 0x42c9e7 MOV	-0x58(%RBP),%RDX

(331) 0x42c9eb MOV	(%RDX),%R9

(331) 0x42c9ee MOV	0x38(%RDX),%R10

(331) 0x42c9f2 MOV	-0x60(%RBP),%RAX

(331) 0x42c9f6 MOV	(%RAX),%R11D

(331) 0x42c9f9 MOV	0x50(%RDX),%RAX

(331) 0x42c9fd MOV	-0x70(%RBP),%RDX

(331) 0x42ca01 MOV	(%RDX),%R13

(331) 0x42ca04 MOV	0x38(%RDX),%R14

(331) 0x42ca08 MOVSXD	%ECX,%RCX

(331) 0x42ca0b INC	%RCX

(331) 0x42ca0e IMUL	%RCX,%RAX

(331) 0x42ca12 TEST	%RSI,%RSI

(331) 0x42ca15 JE	42cac0

(331) 0x42ca1b LEA	(%R9,%RAX,1),%RBX

(331) 0x42ca1f VPBROADCASTQ	%R10,%YMM3

(331) 0x42ca25 VPBROADCASTQ	%R14,%YMM4

(331) 0x42ca2b MOV	%R12,-0x78(%RBP)

(331) 0x42ca2f LEA	(%R12,%R8,1),%RCX

(331) 0x42ca33 MOV	%R11D,%R12D

(331) 0x42ca36 XOR	%R15D,%R15D

(331) 0x42ca39 NOPL	(%RAX)

  (333) 0x42ca40 VPBROADCASTD	%R12D,%XMM5

  (333) 0x42ca46 VPADDD	%XMM0,%XMM5,%XMM5

  (333) 0x42ca4a VPMOVSXDQ	%XMM5,%YMM5

  (333) 0x42ca4f VPSUBQ	%YMM1,%YMM5,%YMM5

  (333) 0x42ca53 VPMULLQ	%YMM5,%YMM3,%YMM5

  (333) 0x42ca59 VPCMPEQB	%XMM0,%XMM0,%K1

  (333) 0x42ca5f VXORPD	%XMM6,%XMM6,%XMM6

  (333) 0x42ca63 VGATHERQPD	(%RBX,%YMM5,1),%YMM6{%K1}

  (333) 0x42ca6a LEA	(%RCX,%R15,1),%RDX

  (333) 0x42ca6e VPBROADCASTQ	%RDX,%YMM5

  (333) 0x42ca74 VPADDQ	%YMM2,%YMM5,%YMM5

  (333) 0x42ca78 VPMULLQ	%YMM5,%YMM4,%YMM5

  (333) 0x42ca7e VPCMPEQB	%XMM0,%XMM0,%K1

  (333) 0x42ca84 VSCATTERQPD	%YMM6,(%R13,%YMM5,1){%K1}

  (333) 0x42ca8c ADD	$0x4,%R15

  (333) 0x42ca90 ADD	$-0x4,%R12D

  (333) 0x42ca94 CMP	%RSI,%R15

  (333) 0x42ca97 JB	42ca40

(331) 0x42ca99 MOV	%RSI,%RCX

(331) 0x42ca9c MOV	-0x48(%RBP),%R15

(331) 0x42caa0 CMP	%R15D,%ESI

(331) 0x42caa3 MOV	-0x38(%RBP),%EBX

(331) 0x42caa6 MOV	-0x78(%RBP),%R12

(331) 0x42caaa JE	42c9c0

(331) 0x42cab0 JMP	42cac2

0x42cab2 NOPW	%CS:(%RAX,%RAX,1)

(331) 0x42cac0 XOR	%ECX,%ECX

(331) 0x42cac2 ADD	%RAX,%R9

(331) 0x42cac5 MOV	%R15,%RAX

(331) 0x42cac8 SUB	%RCX,%RAX

(331) 0x42cacb SUB	%ECX,%R11D

(331) 0x42cace ADD	%R8,%RCX

(331) 0x42cad1 ADD	%R12,%RCX

(331) 0x42cad4 IMUL	%R14,%RCX

(331) 0x42cad8 ADD	%RCX,%R13

(331) 0x42cadb NOPL	(%RAX,%RAX,1)

  (332) 0x42cae0 MOVSXD	%R11D,%R11

  (332) 0x42cae3 LEA	0x1(%R11),%RCX

  (332) 0x42cae7 IMUL	%R10,%RCX

  (332) 0x42caeb VMOVQ	(%R9,%RCX,1),%XMM3

  (332) 0x42caf1 VMOVQ	%XMM3,(%R13)

  (332) 0x42caf7 DEC	%R11D

  (332) 0x42cafa ADD	%R14,%R13

  (332) 0x42cafd DEC	%RAX

  (332) 0x42cb00 JNE	42cae0

(331) 0x42cb02 JMP	42c9c0

0x42cb07 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	pack_kernel.f90:155-163
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:155-163.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.67 to 2.17 cycles (6.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:157

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:163

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:156
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	79
nb uops	82
loop length	279
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	2
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.20	3.20	7.67	7.67	11.00	3.30	3.10	11.00	11.00	11.00	3.20	7.67
cycles	3.20	3.20	7.67	7.67	11.00	3.30	3.10	11.00	11.00	11.00	3.20	7.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.67
Dispatch	11.00
Overall L1	13.67

Vectorization ratios

all	12%
load	28%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

all	10%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.67 cycles. At this rate:

1% of peak load performance is reached (3.51 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.67 to 11.00 cycles (1.24x speedup).

ASM code

In the binary file, the address of the function is: 42c8c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 42c967 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0xa7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x3c(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5288b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %ECX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42c976 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0xb6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x5288d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 404070 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R13),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffffc,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R15D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPMOVSXBD 0xc119f(%RIP),%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (6.3%)
VPCMPEQD %YMM1,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXBQ 0xb9392(%RIP),%YMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
MOV %EBX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 42c9d1 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x111>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	pack_kernel.f90:155-163
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.67 to 2.17 cycles (6.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:157

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:163

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:156
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	79
nb uops	82
loop length	279
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	2
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.20	3.20	7.67	7.67	11.00	3.30	3.10	11.00	11.00	11.00	3.20	7.67
cycles	3.20	3.20	7.67	7.67	11.00	3.30	3.10	11.00	11.00	11.00	3.20	7.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.67
Dispatch	11.00
Overall L1	13.67

Vectorization ratios

all	12%
load	28%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

all	10%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.67 cycles. At this rate:

1% of peak load performance is reached (3.51 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42c8c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 42c967 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0xa7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x3c(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5288b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %ECX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42c976 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0xb6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x5288d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 404070 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R13),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffffc,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R15D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPMOVSXBD 0xc119f(%RIP),%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (6.3%)
VPCMPEQD %YMM1,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXBQ 0xb9392(%RIP),%YMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
MOV %EBX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 42c9d1 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x111>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97–	0.01	0.00
▼Loop 331 - pack_kernel.f90:156-160 - exec–	0.00	0.00
○Loop 332 - pack_kernel.f90:158-160 - exec	0.01	0.01
○Loop 333 - pack_kernel.f90:158-160 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code