OV - exec - Function pack_kernel_module_mp_clover_pack_message_left

	Function: pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101	Module: exec	Source: pack_kernel.f90:61-69	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 61 - 69

--------------------------------------------------------------------------------

61:     !$OMP PARALLEL DO PRIVATE(index)

62:     DO k=y_min-depth,y_max+y_inc+depth

63:     !$OMP SIMD

64:       DO j=1,depth

65:         index= buffer_offset + j+(k+depth-1)*depth

66:         left_snd_buffer(index)=field(x_min+x_inc-1+j,k)

67:       ENDDO

68:     ENDDO

69:   !$OMP END PARALLEL DO

0x42c400 PUSH	%RBP

0x42c401 MOV	%RSP,%RBP

0x42c404 PUSH	%R15

0x42c406 PUSH	%R14

0x42c408 PUSH	%R13

0x42c40a PUSH	%R12

0x42c40c PUSH	%RBX

0x42c40d SUB	$0x58,%RSP

0x42c411 MOV	%R8,-0x78(%RBP)

0x42c415 MOV	0x20(%RBP),%RAX

0x42c419 MOV	%RAX,-0x70(%RBP)

0x42c41d MOV	0x18(%RBP),%RAX

0x42c421 MOV	%RAX,-0x68(%RBP)

0x42c425 MOV	0x10(%RBP),%RAX

0x42c429 MOV	%RAX,-0x60(%RBP)

0x42c42d MOV	0x30(%RBP),%EAX

0x42c430 MOVL	$0,-0x48(%RBP)

0x42c437 TEST	%EAX,%EAX

0x42c439 JS	42c4b0

0x42c43b MOV	%R9,%R14

0x42c43e MOV	%RCX,%R12

0x42c441 MOV	%RDX,%RBX

0x42c444 MOV	(%RDI),%ESI

0x42c446 MOVL	$0,-0x30(%RBP)

0x42c44d MOV	%EAX,-0x2c(%RBP)

0x42c450 MOVL	$0x1,-0x44(%RBP)

0x42c457 SUB	$0x8,%RSP

0x42c45b LEA	-0x44(%RBP),%RAX

0x42c45f LEA	-0x48(%RBP),%RCX

0x42c463 LEA	-0x30(%RBP),%R8

0x42c467 LEA	-0x2c(%RBP),%R9

0x42c46b MOV	$0x5287f0,%EDI

0x42c470 MOV	%ESI,-0x3c(%RBP)

0x42c473 MOV	$0x22,%EDX

0x42c478 PUSH	$0x1

0x42c47a PUSH	$0x1

0x42c47c PUSH	%RAX

0x42c47d CALL	404850 <__kmpc_for_static_init_4@plt>

0x42c482 ADD	$0x20,%RSP

0x42c486 MOV	-0x30(%RBP),%ECX

0x42c489 MOV	-0x2c(%RBP),%R13D

0x42c48d SUB	%ECX,%R13D

0x42c490 JAE	42c4bf

0x42c492 MOV	$0x528810,%EDI

0x42c497 MOV	-0x3c(%RBP),%ESI

0x42c49a ADD	$0x58,%RSP

0x42c49e POP	%RBX

0x42c49f POP	%R12

0x42c4a1 POP	%R13

0x42c4a3 POP	%R14

0x42c4a5 POP	%R15

0x42c4a7 POP	%RBP

0x42c4a8 VZEROUPPER

0x42c4ab JMP	404070

0x42c4b0 ADD	$0x58,%RSP

0x42c4b4 POP	%RBX

0x42c4b5 POP	%R12

0x42c4b7 POP	%R13

0x42c4b9 POP	%R14

0x42c4bb POP	%R15

0x42c4bd POP	%RBP

0x42c4be RET

0x42c4bf MOV	%RCX,%RAX

0x42c4c2 MOV	(%R14),%EDX

0x42c4c5 ADD	%EBX,%EAX

0x42c4c7 MOV	%EDX,%ESI

0x42c4c9 AND	$0x7ffffffc,%ESI

0x42c4cf MOV	%RAX,-0x58(%RBP)

0x42c4d3 ADD	%EDX,%EAX

0x42c4d5 DEC	%EAX

0x42c4d7 IMUL	%EDX,%EAX

0x42c4da XOR	%EDI,%EDI

0x42c4dc VPMOVSXBD	0xb985b(%RIP),%XMM0

0x42c4e5 VPCMPEQD	%YMM1,%YMM1,%YMM1

0x42c4e9 VPMOVSXBQ	0xb984e(%RIP),%YMM2

0x42c4f2 MOV	%R12,-0x50(%RBP)

0x42c4f6 MOV	%R13D,-0x40(%RBP)

0x42c4fa JMP	42c518

0x42c4fc NOPL	(%RAX)

(325) 0x42c500 LEA	0x1(%RDI),%ECX

(325) 0x42c503 MOV	%R8,%RDX

(325) 0x42c506 MOV	-0x38(%RBP),%RAX

(325) 0x42c50a ADD	%R8D,%EAX

(325) 0x42c50d CMP	%R13D,%EDI

(325) 0x42c510 MOV	%ECX,%EDI

(325) 0x42c512 JE	42c492

(325) 0x42c518 CLTQ

(325) 0x42c51a MOV	%RAX,-0x38(%RBP)

(325) 0x42c51e MOV	%RDX,%R8

(325) 0x42c521 TEST	%EDX,%EDX

(325) 0x42c523 JLE	42c500

(325) 0x42c525 MOV	-0x58(%RBP),%RAX

(325) 0x42c529 LEA	(%RAX,%RDI,1),%ECX

(325) 0x42c52c MOV	-0x78(%RBP),%RAX

(325) 0x42c530 MOVSXD	(%RAX),%R15

(325) 0x42c533 MOV	-0x68(%RBP),%RDX

(325) 0x42c537 MOV	(%RDX),%R9

(325) 0x42c53a MOV	0x38(%RDX),%R10

(325) 0x42c53e MOV	-0x70(%RBP),%RAX

(325) 0x42c542 MOV	(%RAX),%R14D

(325) 0x42c545 MOV	0x50(%RDX),%RAX

(325) 0x42c549 MOV	-0x60(%RBP),%RDX

(325) 0x42c54d MOV	(%RDX),%R11

(325) 0x42c550 MOV	0x38(%RDX),%RBX

(325) 0x42c554 MOVSXD	%ECX,%RCX

(325) 0x42c557 TEST	%RSI,%RSI

(325) 0x42c55a MOV	%R15,-0x80(%RBP)

(325) 0x42c55e JE	42c600

(325) 0x42c564 INC	%RCX

(325) 0x42c567 IMUL	%RCX,%RAX

(325) 0x42c56b LEA	(%R9,%RAX,1),%R13

(325) 0x42c56f VPBROADCASTQ	%R10,%YMM3

(325) 0x42c575 VPBROADCASTQ	%RBX,%YMM4

(325) 0x42c57b MOV	-0x38(%RBP),%RCX

(325) 0x42c57f ADD	%R15,%RCX

(325) 0x42c582 ADD	%R14D,%R12D

(325) 0x42c585 XOR	%R15D,%R15D

(325) 0x42c588 NOPL	(%RAX,%RAX,1)

  (327) 0x42c590 LEA	(%R12,%R15,1),%EDX

  (327) 0x42c594 VPBROADCASTD	%EDX,%XMM5

  (327) 0x42c59a VPADDD	%XMM0,%XMM5,%XMM5

  (327) 0x42c59e VPMOVSXDQ	%XMM5,%YMM5

  (327) 0x42c5a3 VPSUBQ	%YMM1,%YMM5,%YMM5

  (327) 0x42c5a7 VPMULLQ	%YMM5,%YMM3,%YMM5

  (327) 0x42c5ad VPCMPEQB	%XMM0,%XMM0,%K1

  (327) 0x42c5b3 VXORPD	%XMM6,%XMM6,%XMM6

  (327) 0x42c5b7 VGATHERQPD	(%R13,%YMM5,1),%YMM6{%K1}

  (327) 0x42c5bf LEA	(%RCX,%R15,1),%RDX

  (327) 0x42c5c3 VPBROADCASTQ	%RDX,%YMM5

  (327) 0x42c5c9 VPADDQ	%YMM2,%YMM5,%YMM5

  (327) 0x42c5cd VPMULLQ	%YMM5,%YMM4,%YMM5

  (327) 0x42c5d3 VPCMPEQB	%XMM0,%XMM0,%K1

  (327) 0x42c5d9 VSCATTERQPD	%YMM6,(%R11,%YMM5,1){%K1}

  (327) 0x42c5e0 ADD	$0x4,%R15

  (327) 0x42c5e4 CMP	%RSI,%R15

  (327) 0x42c5e7 JB	42c590

(325) 0x42c5e9 MOV	%RSI,%R15

(325) 0x42c5ec CMP	%R8D,%ESI

(325) 0x42c5ef MOV	-0x50(%RBP),%R12

(325) 0x42c5f3 MOV	-0x40(%RBP),%R13D

(325) 0x42c5f7 JE	42c500

(325) 0x42c5fd JMP	42c60a

0x42c5ff NOP

(325) 0x42c600 INC	%RCX

(325) 0x42c603 IMUL	%RCX,%RAX

(325) 0x42c607 XOR	%R15D,%R15D

(325) 0x42c60a ADD	%RAX,%R9

(325) 0x42c60d MOV	%R8,%RAX

(325) 0x42c610 SUB	%R15,%RAX

(325) 0x42c613 ADD	%R12D,%R14D

(325) 0x42c616 LEA	(%R15,%R14,1),%ECX

(325) 0x42c61a ADD	-0x38(%RBP),%R15

(325) 0x42c61e ADD	-0x80(%RBP),%R15

(325) 0x42c622 IMUL	%RBX,%R15

(325) 0x42c626 ADD	%R15,%R11

(325) 0x42c629 NOPL	(%RAX)

  (326) 0x42c630 MOVSXD	%ECX,%RCX

  (326) 0x42c633 LEA	0x1(%RCX),%RDX

  (326) 0x42c637 IMUL	%R10,%RDX

  (326) 0x42c63b VMOVQ	(%R9,%RDX,1),%XMM3

  (326) 0x42c641 VMOVQ	%XMM3,(%R11)

  (326) 0x42c646 INC	%ECX

  (326) 0x42c648 ADD	%RBX,%R11

  (326) 0x42c64b DEC	%RAX

  (326) 0x42c64e JNE	42c630

(325) 0x42c650 JMP	42c500

0x42c655 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	pack_kernel.f90:61-69
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:61-69.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 2.17 cycles (6.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:63

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:69

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	81
nb uops	84
loop length	268
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	2
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.20	3.20	8.00	8.00	11.00	3.30	3.10	11.00	11.00	11.00	3.20	8.00
cycles	3.20	3.20	8.00	8.00	11.00	3.30	3.10	11.00	11.00	11.00	3.20	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	11.00
Overall L1	14.00

Vectorization ratios

all	12%
load	28%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

all	10%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.00 to 11.00 cycles (1.27x speedup).

ASM code

In the binary file, the address of the function is: 42c400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 42c4b0 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0xb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x44(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5287f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %ECX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42c4bf <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0xbf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x528810,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 404070 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffffc,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %EDX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPMOVSXBD 0xb985b(%RIP),%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (6.3%)
VPCMPEQD %YMM1,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXBQ 0xb984e(%RIP),%YMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
MOV %R12,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13D,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 42c518 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0x118>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	pack_kernel.f90:61-69
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:61-69.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 2.17 cycles (6.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:63

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:69

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	81
nb uops	84
loop length	268
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	2
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.20	3.20	8.00	8.00	11.00	3.30	3.10	11.00	11.00	11.00	3.20	8.00
cycles	3.20	3.20	8.00	8.00	11.00	3.30	3.10	11.00	11.00	11.00	3.20	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	11.00
Overall L1	14.00

Vectorization ratios

all	12%
load	28%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

all	10%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42c400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 42c4b0 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0xb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x44(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5287f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %ECX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42c4bf <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0xbf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x528810,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 404070 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffffc,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %EDX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPMOVSXBD 0xb985b(%RIP),%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (6.3%)
VPCMPEQD %YMM1,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXBQ 0xb984e(%RIP),%YMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
MOV %R12,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13D,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 42c518 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0x118>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101–	0.01	0.01
▼Loop 325 - pack_kernel.f90:62-66 - exec–	0.00	0.00
○Loop 326 - pack_kernel.f90:64-66 - exec	0.01	0.01
○Loop 327 - pack_kernel.f90:64-66 - exec	0.00	0.00

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Code clean check

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Vectorization

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code