OV - exec - Loop 750

	Loop Id: 750	Module: exec	Source: viscosity_kernel.f90:53-89	Coverage: 2.02%

0x45f980 VPBROADCASTQ	%R14,%ZMM1

0x45f986 VPADDQ	0xb4af0(%RIP),%ZMM1,%ZMM1    [9]

0x45f990 VMOVDQA64	%ZMM1,%ZMM10{%K1}

0x45f996 VMOVAPD	%ZMM13,%ZMM30{%K1}

0x45f99c VMOVDQA64	%ZMM1,%ZMM31{%K1}

0x45f9a2 VMOVAPD	%ZMM14,%ZMM28{%K1}

0x45f9a8 VMOVDQA64	%ZMM1,%ZMM29{%K1}

0x45f9ae VMOVAPD	%ZMM2,%ZMM26{%K1}

0x45f9b4 VMOVDQA64	%ZMM1,%ZMM27{%K1}

0x45f9ba VMOVAPD	%ZMM17,%ZMM24{%K1}

0x45f9c0 VMOVDQA64	%ZMM1,%ZMM25{%K1}

0x45f9c6 VMOVAPD	%ZMM18,%ZMM22{%K1}

0x45f9cc VMOVDQA64	%ZMM1,%ZMM23{%K1}

0x45f9d2 VMOVAPD	%ZMM16,%ZMM20{%K1}

0x45f9d8 VMOVDQA64	%ZMM1,%ZMM21{%K1}

0x45f9de VMOVAPD	%ZMM15,%ZMM19{%K1}

0x45f9e4 VMOVAPD	%ZMM12,%ZMM1{%K1}{z}

0x45f9ea VMOVUPD	%ZMM1,(%R15,%R14,8)    [10]

0x45f9f1 ADD	$0x8,%R14

0x45f9f5 CMP	%R11,%R14

0x45f9f8 JAE	45fc80

0x45f9fe VMOVUPD	-0x8(%R8,%R14,8),%ZMM1    [5]

0x45fa09 VMOVUPD	(%R8,%R14,8),%ZMM2    [5]

0x45fa10 VMOVUPD	-0x8(%RCX,%R14,8),%ZMM4    [1]

0x45fa1b VMOVUPD	(%RCX,%R14,8),%ZMM8    [1]

0x45fa22 VADDPD	%ZMM2,%ZMM8,%ZMM11

0x45fa28 VADDPD	%ZMM4,%ZMM1,%ZMM12

0x45fa2e VSUBPD	%ZMM12,%ZMM11,%ZMM12

0x45fa34 VMOVUPD	-0x8(%R13,%R14,8),%ZMM13    [7]

0x45fa3f VMOVUPD	(%R13,%R14,8),%ZMM14    [7]

0x45fa47 VMOVUPD	-0x8(%RBX,%R14,8),%ZMM15    [4]

0x45fa52 VMOVUPD	(%RBX,%R14,8),%ZMM16    [4]

0x45fa59 VADDPD	%ZMM13,%ZMM14,%ZMM11

0x45fa5f VADDPD	%ZMM16,%ZMM15,%ZMM17

0x45fa65 VSUBPD	%ZMM17,%ZMM11,%ZMM17

0x45fa6b VMOVUPD	-0x8(%RDX,%R14,8),%ZMM11    [13]

0x45fa76 VMULPD	%ZMM12,%ZMM11,%ZMM18

0x45fa7c VADDPD	%ZMM1,%ZMM2,%ZMM1

0x45fa82 VSUBPD	%ZMM1,%ZMM8,%ZMM1

0x45fa88 VADDPD	%ZMM4,%ZMM1,%ZMM1

0x45fa8e VBROADCASTSD	0x97668(%RIP),%ZMM3    [9]

0x45fa98 VMULPD	%ZMM3,%ZMM1,%ZMM1

0x45fa9e VADDPD	%ZMM15,%ZMM13,%ZMM2

0x45faa4 VSUBPD	%ZMM2,%ZMM14,%ZMM2

0x45faaa VADDPD	%ZMM16,%ZMM2,%ZMM2

0x45fab0 VDIVPD	%ZMM11,%ZMM9,%ZMM8

0x45fab6 VMULPD	%ZMM3,%ZMM2,%ZMM2

0x45fabc VMULPD	%ZMM8,%ZMM2,%ZMM2

0x45fac2 VFMADD231PD	%ZMM1,%ZMM0,%ZMM2

0x45fac8 VMOVUPD	(%RDI,%R14,8),%ZMM1    [8]

0x45facf VSUBPD	-0x10(%RDI,%R14,8),%ZMM1,%ZMM1    [8]

0x45fada VADDPD	(%RDX,%R14,8),%ZMM11,%ZMM4    [13]

0x45fae1 VDIVPD	%ZMM4,%ZMM1,%ZMM4

0x45fae7 VMOVUPD	(%RSI,%R14,8),%ZMM1    [12]

0x45faee VSUBPD	(%RAX,%R14,8),%ZMM1,%ZMM1    [11]

0x45faf5 VMULPD	%ZMM5,%ZMM1,%ZMM1

0x45fafb VMULPD	%ZMM4,%ZMM4,%ZMM13

0x45fb01 VMULPD	%ZMM1,%ZMM1,%ZMM14

0x45fb07 VMULPD	%ZMM3,%ZMM12,%ZMM12

0x45fb0d VMULPD	%ZMM8,%ZMM12,%ZMM8

0x45fb13 VMULPD	%ZMM13,%ZMM8,%ZMM8

0x45fb19 VMULPD	%ZMM3,%ZMM17,%ZMM12

0x45fb1f VMULPD	%ZMM14,%ZMM12,%ZMM12

0x45fb25 VMULPD	%ZMM2,%ZMM4,%ZMM2

0x45fb2b VFMADD213PD	%ZMM8,%ZMM1,%ZMM2

0x45fb31 VFMADD231PD	%ZMM12,%ZMM0,%ZMM2

0x45fb37 VADDPD	%ZMM13,%ZMM14,%ZMM8

0x45fb3d VBROADCASTSD	0xb4901(%RIP),%ZMM3    [9]

0x45fb47 VMAXPD	%ZMM3,%ZMM8,%ZMM8

0x45fb4d VDIVPD	%ZMM8,%ZMM2,%ZMM8

0x45fb53 VFMADD231PD	%ZMM17,%ZMM7,%ZMM18

0x45fb59 VXORPD	%XMM12,%XMM12,%XMM12

0x45fb5e VCMPPD	$0x6,%ZMM18,%ZMM12,%K1

0x45fb65 VCMPPD	$0x5,%ZMM8,%ZMM12,%K1{%K1}

0x45fb6c KORTESTB	%K1,%K1

0x45fb70 VXORPD	%XMM13,%XMM13,%XMM13

0x45fb75 VXORPD	%XMM14,%XMM14,%XMM14

0x45fb7a VXORPD	%XMM2,%XMM2,%XMM2

0x45fb7e VXORPD	%XMM17,%XMM17,%XMM17

0x45fb84 VXORPD	%XMM18,%XMM18,%XMM18

0x45fb8a VXORPD	%XMM16,%XMM16,%XMM16

0x45fb90 VXORPD	%XMM15,%XMM15,%XMM15

0x45fb95 JE	45f980

0x45fb9b VFPCLASSPD	$0x50,%ZMM4,%K2

0x45fba2 VBROADCASTSD	0xb48a4(%RIP),%ZMM12    [9]

0x45fbac VBLENDMPD	%ZMM12,%ZMM9,%ZMM13{%K2}

0x45fbb2 VBROADCASTSD	0x96594(%RIP),%ZMM15    [9]

0x45fbbc VANDPD	%ZMM15,%ZMM4,%ZMM2

0x45fbc2 VMAXPD	%ZMM3,%ZMM2,%ZMM2

0x45fbc8 VMULPD	%ZMM2,%ZMM13,%ZMM4

0x45fbce VFPCLASSPD	$0x50,%ZMM4,%K2

0x45fbd5 VBLENDMPD	%ZMM12,%ZMM9,%ZMM14{%K2}

0x45fbdb VANDPD	%ZMM15,%ZMM1,%ZMM1

0x45fbe1 VMAXPD	%ZMM3,%ZMM1,%ZMM1

0x45fbe7 VMULPD	%ZMM14,%ZMM1,%ZMM1

0x45fbed VMULPD	%ZMM4,%ZMM4,%ZMM2

0x45fbf3 VFMADD231PD	%ZMM1,%ZMM1,%ZMM2

0x45fbf9 VSQRTPD	%ZMM2,%ZMM2

0x45fbff VMULPD	%ZMM11,%ZMM2,%ZMM11

0x45fc05 VDIVPD	%ZMM4,%ZMM11,%ZMM4

0x45fc0b VANDPD	%ZMM15,%ZMM4,%ZMM17

0x45fc11 VMULPD	%ZMM7,%ZMM2,%ZMM4

0x45fc17 VDIVPD	%ZMM1,%ZMM4,%ZMM1

0x45fc1d VANDPD	%ZMM15,%ZMM1,%ZMM18

0x45fc23 VMINPD	%ZMM18,%ZMM17,%ZMM16

0x45fc29 VMULPD	%ZMM16,%ZMM16,%ZMM15

0x45fc2f VMULPD	%ZMM8,%ZMM8,%ZMM1

0x45fc35 VADDPD	%ZMM15,%ZMM15,%ZMM4

0x45fc3b MOV	0x88(%RBP),%R10    [6]

0x45fc42 MOV	(%R10),%R10    [3]

0x45fc45 IMUL	%R9,%R10

0x45fc49 ADD	%R12,%R10

0x45fc4c VMOVUPD	(%R10,%R14,8),%ZMM8{%K1}{z}    [2]

0x45fc53 VMULPD	%ZMM8,%ZMM1,%ZMM1

0x45fc59 VMULPD	%ZMM4,%ZMM1,%ZMM12

0x45fc5f JMP	45f980

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 53 - 89

--------------------------------------------------------------------------------

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.30
Bottlenecks
Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source	viscosity_kernel.f90:53-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	73.00
CQA cycles if no scalar integer	73.00
CQA cycles if FP arith vectorized	73.00
CQA cycles if fully vectorized	73.00
Front-end cycles	18.58
P0 cycles	31.75
P1 cycles	19.25
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	0.50
P5 cycles	31.75
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.90
P11 cycles	6.50
DIV/SQRT cycles	73.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.50
Nb uops	108.50
Nb loads	19.50
Nb stores	1.00
Nb stack references	0.50
FLOP/cycle	5.21
Nb FLOP add-sub	132.00
Nb FLOP mul	140.00
Nb FLOP fma	36.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.63
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	64.00
Stride 0	1.50
Stride 1	3.50
Stride n	0.00
Stride unknown	0.50
Stride indirect	0.00
Vectorization ratio all	95.27
Vectorization ratio load	84.12
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	87.85
Vector-efficiency ratio all	89.21
Vector-efficiency ratio load	86.10
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	72.05

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.48
Bottlenecks	P0,
Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source	viscosity_kernel.f90:53-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	98.00
CQA cycles if no scalar integer	98.00
CQA cycles if FP arith vectorized	98.00
CQA cycles if fully vectorized	98.00
Front-end cycles	21.83
P0 cycles	39.50
P1 cycles	22.00
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	0.50
P5 cycles	39.50
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.40
P11 cycles	7.33
DIV/SQRT cycles	98.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	116.00
Nb uops	128.00
Nb loads	22.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	4.49
Nb FLOP add-sub	136.00
Nb FLOP mul	176.00
Nb FLOP fma	40.00
Nb FLOP div	40.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.59
Bytes prefetched	0.00
Bytes loaded	1072.00
Bytes stored	64.00
Stride 0	2.00
Stride 1	4.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	94.39
Vectorization ratio load	80.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	86.05
Vector-efficiency ratio all	89.49
Vector-efficiency ratio load	82.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	73.84

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P0,
Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source	viscosity_kernel.f90:53-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	48.00
CQA cycles if no scalar integer	48.00
CQA cycles if FP arith vectorized	48.00
CQA cycles if fully vectorized	48.00
Front-end cycles	15.33
P0 cycles	24.00
P1 cycles	16.50
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	0.50
P5 cycles	24.00
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.40
P11 cycles	5.67
DIV/SQRT cycles	48.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	83.00
Nb uops	89.00
Nb loads	17.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	6.67
Nb FLOP add-sub	128.00
Nb FLOP mul	104.00
Nb FLOP fma	32.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.67
Bytes prefetched	0.00
Bytes loaded	976.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	96.15
Vectorization ratio load	88.24
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	89.66
Vector-efficiency ratio all	88.94
Vector-efficiency ratio load	89.71
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	70.26

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	viscosity_kernel.f90:53-89
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:53-89.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 89% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

84% of SSE/AVX loads are used in vector version.
87% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 73.00 to 25.00 cycles (2.92x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 36 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 0 occurrences
VSQRTPD: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 0 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

48 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 380 FP arithmetical operations:

168: addition or subtraction (36 inside FMA instructions)
176: multiply (36 inside FMA instructions)
32: divide
4: square root

The binary loop is loading 1024 bytes (128 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.35 FP operations per loaded or stored byte.

General properties

nb instructions	99.50
nb uops	108.50
loop length	639.50
used x86 registers	13
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	31
nb stack references	0.50
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	18.58 cycles
front end	18.58 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	31.75	1.10	6.50	6.50	0.50	31.75	2.00	0.50	0.50	0.50	0.90	6.50
cycles	31.75	19.25	6.50	6.50	0.50	31.75	2.00	0.50	0.50	0.50	0.90	6.50

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	73.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	18.58
Dispatch	31.75
DIV/SQRT	73.00
Data deps.	0.00
Overall L1	73.00

Vectorization ratios

INT

all	84%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	82%

all	96%
load	83%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

INT+FP

all	95%
load	84%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	87%

Vector efficiency ratios

INT

all	86%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	84%

all	89%
load	85%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	67%

INT+FP

all	89%
load	86%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	72%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 73.00 cycles. At this rate:

8% of peak load performance is reached (15.64 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.99 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	viscosity_kernel.f90:53-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 89% of vector register length is used (average across all SSE/AVX instructions).

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX loads are used in vector version.
86% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 98.00 to 39.50 cycles (2.48x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 98.00 to 30.50 cycles (3.21x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 40 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 5 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:71
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:65
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:72
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:84
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:85
VSQRTPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:83

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

58 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 440 FP arithmetical operations:

176: addition or subtraction (40 inside FMA instructions)
216: multiply (40 inside FMA instructions)
40: divide
8: square root

The binary loop is loading 1072 bytes (134 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.39 FP operations per loaded or stored byte.

General properties

nb instructions	116
nb uops	128
loop length	740
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	31
nb stack references	1
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.83 cycles
front end	21.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	39.50	1.60	7.33	7.33	0.50	39.50	2.00	0.50	0.50	0.50	1.40	7.33
cycles	39.50	22.00	7.33	7.33	0.50	39.50	2.00	0.50	0.50	0.50	1.40	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	98.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	21.83
Dispatch	39.50
DIV/SQRT	98.00
Data deps.	0.00
Overall L1	98.00

Vectorization ratios

INT

all	80%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	77%

all	95%
load	78%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	94%
load	80%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	86%

Vector efficiency ratios

INT

all	82%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	90%
load	81%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	72%

INT+FP

all	89%
load	82%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	73%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 98.00 cycles. At this rate:

5% of peak load performance is reached (10.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45f9fe

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %R14,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ 0xb4af0(%RIP),%ZMM1,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM13,%ZMM30{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM31{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM14,%ZMM28{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM29{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM2,%ZMM26{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM27{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM17,%ZMM24{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM25{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM18,%ZMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM16,%ZMM20{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM21{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM15,%ZMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM12,%ZMM1{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVUPD %ZMM1,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 45fc80 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x790>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD -0x8(%R8,%R14,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R8,%R14,8),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD -0x8(%RCX,%R14,8),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RCX,%R14,8),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM8,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM1,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM11,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD -0x8(%R13,%R14,8),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R13,%R14,8),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD -0x8(%RBX,%R14,8),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RBX,%R14,8),%ZMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM14,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM16,%ZMM15,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM17,%ZMM11,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD -0x8(%RDX,%R14,8),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD %ZMM12,%ZMM11,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM1,%ZMM2,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM1,%ZMM8,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x97668(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %ZMM3,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM15,%ZMM13,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM14,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM16,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM11,%ZMM9,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM3,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%RDI,%R14,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD -0x10(%RDI,%R14,8),%ZMM1,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%RDX,%R14,8),%ZMM11,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD %ZMM4,%ZMM1,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD (%RSI,%R14,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%RAX,%R14,8),%ZMM1,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM5,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM4,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM1,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM3,%ZMM12,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM12,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM3,%ZMM17,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM12,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM4,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM8,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM14,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0xb4901(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMAXPD %ZMM3,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM8,%ZMM2,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VFMADD231PD %ZMM17,%ZMM7,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VXORPD %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x6,%ZMM18,%ZMM12,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x5,%ZMM8,%ZMM12,%K1{%K1}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KORTESTB %K1,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JE 45f980 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x490>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VFPCLASSPD $0x50,%ZMM4,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VBROADCASTSD 0xb48a4(%RIP),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBLENDMPD %ZMM12,%ZMM9,%ZMM13{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VBROADCASTSD 0x96594(%RIP),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VANDPD %ZMM15,%ZMM4,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMAXPD %ZMM3,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM13,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFPCLASSPD $0x50,%ZMM4,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VBLENDMPD %ZMM12,%ZMM9,%ZMM14{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM15,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMAXPD %ZMM3,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM4,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM2,%ZMM2	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	23-32	18	vect (100.0%)
VMULPD %ZMM11,%ZMM2,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM4,%ZMM11,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VANDPD %ZMM15,%ZMM4,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM7,%ZMM2,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM1,%ZMM4,%ZMM1	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VANDPD %ZMM15,%ZMM1,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMINPD %ZMM18,%ZMM17,%ZMM16	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM16,%ZMM16,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM8,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM15,%ZMM15,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x88(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R10),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R12,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%R10,%R14,8),%ZMM8{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM1,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
JMP 45f980 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x490>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	viscosity_kernel.f90:53-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 88% of vector register length is used (average across all SSE/AVX instructions).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX loads are used in vector version.
89% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 19.50 cycles (2.46x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:71
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:65
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:72

Type of elements and instruction set

39 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 320 FP arithmetical operations:

160: addition or subtraction (32 inside FMA instructions)
136: multiply (32 inside FMA instructions)
24: divide

The binary loop is loading 976 bytes (122 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	83
nb uops	89
loop length	539
used x86 registers	11
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	31
nb stack references	0
ADD-SUB / MUL ratio	1.23

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	24.00	0.60	5.67	5.67	0.50	24.00	2.00	0.50	0.50	0.50	0.40	5.67
cycles	24.00	16.50	5.67	5.67	0.50	24.00	2.00	0.50	0.50	0.50	0.40	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	48.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	15.33
Dispatch	24.00
DIV/SQRT	48.00
Data deps.	0.00
Overall L1	48.00

Vectorization ratios

INT

all	88%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	87%

all	97%
load	87%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	90%

INT+FP

all	96%
load	88%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

Vector efficiency ratios

INT

all	90%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	89%

all	88%
load	89%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	63%

INT+FP

all	88%
load	89%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	70%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.00 cycles. At this rate:

10% of peak load performance is reached (20.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45f9fe

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %R14,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ 0xb4af0(%RIP),%ZMM1,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM13,%ZMM30{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM31{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM14,%ZMM28{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM29{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM2,%ZMM26{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM27{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM17,%ZMM24{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM25{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM18,%ZMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM16,%ZMM20{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVDQA64 %ZMM1,%ZMM21{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM15,%ZMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM12,%ZMM1{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVUPD %ZMM1,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 45fc80 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x790>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD -0x8(%R8,%R14,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R8,%R14,8),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD -0x8(%RCX,%R14,8),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RCX,%R14,8),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM8,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM1,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM11,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD -0x8(%R13,%R14,8),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R13,%R14,8),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD -0x8(%RBX,%R14,8),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RBX,%R14,8),%ZMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM14,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM16,%ZMM15,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM17,%ZMM11,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD -0x8(%RDX,%R14,8),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD %ZMM12,%ZMM11,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM1,%ZMM2,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM1,%ZMM8,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x97668(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %ZMM3,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM15,%ZMM13,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM14,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM16,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM11,%ZMM9,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM3,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%RDI,%R14,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD -0x10(%RDI,%R14,8),%ZMM1,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%RDX,%R14,8),%ZMM11,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD %ZMM4,%ZMM1,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD (%RSI,%R14,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%RAX,%R14,8),%ZMM1,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM5,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM4,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM1,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM3,%ZMM12,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM12,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM3,%ZMM17,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM12,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM4,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM8,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM14,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0xb4901(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMAXPD %ZMM3,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM8,%ZMM2,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VFMADD231PD %ZMM17,%ZMM7,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VXORPD %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x6,%ZMM18,%ZMM12,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x5,%ZMM8,%ZMM12,%K1{%K1}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KORTESTB %K1,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JE 45f980 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x490>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

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Expensive FP math instructions/calls

Masked instructions

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FMA

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Complex instructions

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Slow data structures access

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code