OV - exec - Loop 74

	Loop Id: 74	Module: exec	Source: advec_cell_kernel.f90:83-157 [...]	Coverage: 3.43%

0x419020 MOV	(%RSP),%R12    [10]

0x419024 ADD	%RSI,%R12

0x419027 VPBROADCASTQ	%R12,%ZMM18

0x41902d LEA	(%R9,%RSI,1),%R12D

0x419031 VPBROADCASTD	%R12D,%YMM21

0x419037 MOV	0x58(%RSP),%R12    [10]

0x41903c VMOVUPD	(%R12,%RSI,8),%ZMM23    [6]

0x419043 VCMPPD	$0x1,%ZMM23,%ZMM7,%K1

0x41904a VPADDQ	%ZMM8,%ZMM18,%ZMM20

0x419050 VPMOVQD	%ZMM20,%YMM19

0x419056 VPADDD	%YMM16,%YMM21,%YMM18

0x41905c VPBLENDMD	%YMM18,%YMM19,%YMM22{%K1}

0x419062 VPMOVSXDQ	%YMM22,%ZMM22

0x419068 VPSUBQ	%ZMM5,%ZMM22,%ZMM24

0x41906e VXORPD	%XMM25,%XMM25,%XMM25

0x419074 KXNORW	%K0,%K0,%K2

0x419078 MOV	0x50(%RSP),%R12    [10]

0x41907d VGATHERQPD	(%R12,%ZMM24,8),%ZMM25{%K2}    [5]

0x419084 VPCMPGTQ	%ZMM20,%ZMM0,%K2

0x41908a VMOVDQA64	%YMM4,%YMM20

0x419090 VPADDD	%YMM15,%YMM21,%YMM20{%K2}

0x419096 VPBLENDMD	%YMM18,%YMM20,%YMM22{%K1}

0x41909c VPMOVSXDQ	%YMM22,%ZMM22

0x4190a2 VPSUBQ	%ZMM5,%ZMM22,%ZMM22

0x4190a8 VXORPD	%XMM26,%XMM26,%XMM26

0x4190ae KXNORW	%K0,%K0,%K2

0x4190b2 VGATHERQPD	(%RBX,%ZMM22,8),%ZMM26{%K2}    [8]

0x4190b9 VPADDD	%YMM17,%YMM21,%YMM22

0x4190bf VPBLENDMD	%YMM22,%YMM20,%YMM21{%K1}

0x4190c5 VANDPD	%ZMM10,%ZMM23,%ZMM27

0x4190cb VXORPD	%XMM28,%XMM28,%XMM28

0x4190d1 KXNORW	%K0,%K0,%K2

0x4190d5 VGATHERQPD	(%RDX,%ZMM24,8),%ZMM28{%K2}    [13]

0x4190dc VDIVPD	%ZMM25,%ZMM27,%ZMM27

0x4190e2 VPMOVSXDQ	%YMM21,%ZMM21

0x4190e8 VPSUBQ	%ZMM5,%ZMM21,%ZMM29

0x4190ee VXORPD	%XMM30,%XMM30,%XMM30

0x4190f4 KXNORW	%K0,%K0,%K2

0x4190f8 VGATHERQPD	(%RDX,%ZMM29,8),%ZMM30{%K2}    [13]

0x4190ff VPBLENDMD	%YMM19,%YMM18,%YMM31{%K1}

0x419105 MOV	0x98(%RSP),%R12    [10]

0x41910d VMOVUPD	(%R12,%RSI,8),%ZMM9    [4]

0x419114 VMOVAPD	%ZMM9,%ZMM21

0x41911a VFMADD213PD	%ZMM9,%ZMM27,%ZMM21

0x419120 VPMOVSXDQ	%YMM31,%ZMM31

0x419126 VPSUBQ	%ZMM5,%ZMM31,%ZMM31

0x41912c VPXOR	%XMM1,%XMM1,%XMM1

0x419130 KXNORW	%K0,%K0,%K1

0x419134 VGATHERQPD	(%RDX,%ZMM31,8),%ZMM1{%K1}    [13]

0x41913b VDIVPD	%ZMM26,%ZMM21,%ZMM21

0x419141 VSUBPD	%ZMM27,%ZMM12,%ZMM26

0x419147 VSUBPD	%ZMM30,%ZMM28,%ZMM30

0x41914d VSUBPD	%ZMM28,%ZMM1,%ZMM1

0x419153 VMULPD	%ZMM30,%ZMM1,%ZMM2

0x419159 VCMPPD	$0x1,%ZMM2,%ZMM7,%K1

0x419160 VSUBPD	%ZMM27,%ZMM11,%ZMM2

0x419166 VFPCLASSPD	$0x56,%ZMM1,%K2

0x41916d VXORPD	%ZMM13,%ZMM2,%ZMM2{%K2}

0x419173 VANDPD	%ZMM10,%ZMM30,%ZMM27

0x419179 VANDPD	%ZMM10,%ZMM1,%ZMM1

0x41917f VMULPD	%ZMM21,%ZMM27,%ZMM30

0x419185 VFMADD231PD	%ZMM26,%ZMM1,%ZMM30

0x41918b VMULPD	%ZMM14,%ZMM30,%ZMM30

0x419191 VMINPD	%ZMM30,%ZMM1,%ZMM1

0x419197 VMINPD	%ZMM1,%ZMM27,%ZMM1

0x41919d VMULPD	%ZMM25,%ZMM28,%ZMM25

0x4191a3 VFMADD231PD	%ZMM2,%ZMM1,%ZMM28{%K1}

0x4191a9 VMULPD	%ZMM23,%ZMM28,%ZMM1

0x4191af MOV	0xf0(%RSP),%R12    [10]

0x4191b7 VMOVUPD	%ZMM1,(%R12,%RSI,8)    [3]

0x4191be VXORPD	%XMM2,%XMM2,%XMM2

0x4191c2 KXNORW	%K0,%K0,%K1

0x4191c6 VGATHERQPD	(%R11,%ZMM24,8),%ZMM2{%K1}    [15]

0x4191cd VXORPD	%XMM23,%XMM23,%XMM23

0x4191d3 KXNORW	%K0,%K0,%K1

0x4191d7 VGATHERQPD	(%R11,%ZMM29,8),%ZMM23{%K1}    [15]

0x4191de VXORPD	%XMM24,%XMM24,%XMM24

0x4191e4 KXNORW	%K0,%K0,%K1

0x4191e8 VGATHERQPD	(%R11,%ZMM31,8),%ZMM24{%K1}    [15]

0x4191ef VSUBPD	%ZMM23,%ZMM2,%ZMM23

0x4191f5 VSUBPD	%ZMM2,%ZMM24,%ZMM24

0x4191fb VMULPD	%ZMM23,%ZMM24,%ZMM27

0x419201 VCMPPD	$0x1,%ZMM27,%ZMM7,%K1

0x419208 VANDPD	%ZMM10,%ZMM1,%ZMM27

0x41920e VDIVPD	%ZMM25,%ZMM27,%ZMM25

0x419214 VSUBPD	%ZMM25,%ZMM11,%ZMM25

0x41921a VFPCLASSPD	$0x56,%ZMM24,%K2

0x419221 VXORPD	%ZMM13,%ZMM25,%ZMM25{%K2}

0x419227 VANDPD	%ZMM10,%ZMM23,%ZMM23

0x41922d VANDPD	%ZMM10,%ZMM24,%ZMM24

0x419233 VMULPD	%ZMM21,%ZMM23,%ZMM21

0x419239 VFMADD231PD	%ZMM26,%ZMM24,%ZMM21

0x41923f VMULPD	%ZMM14,%ZMM21,%ZMM21

0x419245 VMINPD	%ZMM21,%ZMM24,%ZMM21

0x41924b VMINPD	%ZMM21,%ZMM23,%ZMM21

0x419251 VFMADD231PD	%ZMM25,%ZMM21,%ZMM2{%K1}

0x419257 VMULPD	%ZMM1,%ZMM2,%ZMM1

0x41925d MOV	0xa0(%RSP),%R12    [10]

0x419265 VMOVUPD	%ZMM1,(%R12,%RSI,8)    [2]

0x41926c MOV	0x68(%RSP),%R12    [10]

0x419271 VMOVUPD	(%R12,%RSI,8),%ZMM1    [25]

0x419278 VCMPPD	$0x1,%ZMM1,%ZMM7,%K1

0x41927f VPBLENDMD	%YMM18,%YMM19,%YMM2{%K1}

0x419285 VPMOVSXDQ	%YMM2,%ZMM2

0x41928b VPSUBQ	%ZMM5,%ZMM2,%ZMM2

0x419291 VXORPD	%XMM21,%XMM21,%XMM21

0x419297 KXNORW	%K0,%K0,%K2

0x41929b MOV	0x48(%RSP),%R12    [10]

0x4192a0 VGATHERQPD	(%R12,%ZMM2,8),%ZMM21{%K2}    [24]

0x4192a7 VPBLENDMD	%YMM18,%YMM20,%YMM23{%K1}

0x4192ad VPMOVSXDQ	%YMM23,%ZMM23

0x4192b3 VPSUBQ	%ZMM5,%ZMM23,%ZMM23

0x4192b9 VXORPD	%XMM24,%XMM24,%XMM24

0x4192bf KXNORW	%K0,%K0,%K2

0x4192c3 VGATHERQPD	(%RBX,%ZMM23,8),%ZMM24{%K2}    [8]

0x4192ca VPBLENDMD	%YMM22,%YMM20,%YMM23{%K1}

0x4192d0 VANDPD	%ZMM10,%ZMM1,%ZMM25

0x4192d6 VXORPD	%XMM26,%XMM26,%XMM26

0x4192dc KXNORW	%K0,%K0,%K2

0x4192e0 VGATHERQPD	(%R13,%ZMM2,8),%ZMM26{%K2}    [12]

0x4192e8 VDIVPD	%ZMM21,%ZMM25,%ZMM25

0x4192ee VPMOVSXDQ	%YMM23,%ZMM23

0x4192f4 VPSUBQ	%ZMM5,%ZMM23,%ZMM23

0x4192fa VXORPD	%XMM27,%XMM27,%XMM27

0x419300 KXNORW	%K0,%K0,%K2

0x419304 VGATHERQPD	(%R13,%ZMM23,8),%ZMM27{%K2}    [12]

0x41930c VPBLENDMD	%YMM19,%YMM18,%YMM28{%K1}

0x419312 VMOVAPD	%ZMM9,%ZMM29

0x419318 VFMADD213PD	%ZMM9,%ZMM25,%ZMM29

0x41931e VPMOVSXDQ	%YMM28,%ZMM28

0x419324 VPSUBQ	%ZMM5,%ZMM28,%ZMM28

0x41932a VXORPD	%XMM30,%XMM30,%XMM30

0x419330 KXNORW	%K0,%K0,%K1

0x419334 VGATHERQPD	(%R13,%ZMM28,8),%ZMM30{%K1}    [12]

0x41933c VDIVPD	%ZMM24,%ZMM29,%ZMM24

0x419342 VSUBPD	%ZMM25,%ZMM12,%ZMM29

0x419348 VSUBPD	%ZMM27,%ZMM26,%ZMM27

0x41934e VSUBPD	%ZMM26,%ZMM30,%ZMM30

0x419354 VMULPD	%ZMM27,%ZMM30,%ZMM31

0x41935a VCMPPD	$0x1,%ZMM31,%ZMM7,%K1

0x419361 VSUBPD	%ZMM25,%ZMM11,%ZMM25

0x419367 VFPCLASSPD	$0x56,%ZMM30,%K2

0x41936e VXORPD	%ZMM13,%ZMM25,%ZMM25{%K2}

0x419374 VANDPD	%ZMM10,%ZMM27,%ZMM27

0x41937a VANDPD	%ZMM10,%ZMM30,%ZMM30

0x419380 VMULPD	%ZMM24,%ZMM27,%ZMM31

0x419386 VFMADD231PD	%ZMM29,%ZMM30,%ZMM31

0x41938c VMULPD	%ZMM14,%ZMM31,%ZMM31

0x419392 VMINPD	%ZMM31,%ZMM30,%ZMM30

0x419398 VMINPD	%ZMM30,%ZMM27,%ZMM27

0x41939e VMULPD	%ZMM21,%ZMM26,%ZMM21

0x4193a4 VFMADD231PD	%ZMM25,%ZMM27,%ZMM26{%K1}

0x4193aa VMULPD	%ZMM1,%ZMM26,%ZMM1

0x4193b0 MOV	0x40(%RSP),%R12    [10]

0x4193b5 VMOVUPD	%ZMM1,(%R12,%RSI,8)    [23]

0x4193bc VXORPD	%XMM25,%XMM25,%XMM25

0x4193c2 KXNORW	%K0,%K0,%K1

0x4193c6 VGATHERQPD	(%RDI,%ZMM2,8),%ZMM25{%K1}    [7]

0x4193cd VXORPD	%XMM2,%XMM2,%XMM2

0x4193d1 KXNORW	%K0,%K0,%K1

0x4193d5 VGATHERQPD	(%RDI,%ZMM23,8),%ZMM2{%K1}    [7]

0x4193dc VXORPD	%XMM23,%XMM23,%XMM23

0x4193e2 KXNORW	%K0,%K0,%K1

0x4193e6 VGATHERQPD	(%RDI,%ZMM28,8),%ZMM23{%K1}    [7]

0x4193ed VSUBPD	%ZMM2,%ZMM25,%ZMM2

0x4193f3 VSUBPD	%ZMM25,%ZMM23,%ZMM23

0x4193f9 VMULPD	%ZMM2,%ZMM23,%ZMM26

0x4193ff VCMPPD	$0x1,%ZMM26,%ZMM7,%K1

0x419406 VANDPD	%ZMM10,%ZMM1,%ZMM26

0x41940c VDIVPD	%ZMM21,%ZMM26,%ZMM21

0x419412 VSUBPD	%ZMM21,%ZMM11,%ZMM21

0x419418 VFPCLASSPD	$0x56,%ZMM23,%K2

0x41941f VXORPD	%ZMM13,%ZMM21,%ZMM21{%K2}

0x419425 VANDPD	%ZMM10,%ZMM2,%ZMM2

0x41942b VANDPD	%ZMM10,%ZMM23,%ZMM23

0x419431 VMULPD	%ZMM24,%ZMM2,%ZMM24

0x419437 VFMADD231PD	%ZMM29,%ZMM23,%ZMM24

0x41943d VMULPD	%ZMM14,%ZMM24,%ZMM24

0x419443 VMINPD	%ZMM24,%ZMM23,%ZMM23

0x419449 VMINPD	%ZMM23,%ZMM2,%ZMM2

0x41944f VFMADD231PD	%ZMM21,%ZMM2,%ZMM25{%K1}

0x419455 VMULPD	%ZMM1,%ZMM25,%ZMM1

0x41945b MOV	0xa8(%RSP),%R12    [10]

0x419463 VMOVUPD	%ZMM1,(%R12,%RSI,8)    [22]

0x41946a MOV	0x18(%RSP),%R12    [10]

0x41946f VMOVUPD	(%R12,%RSI,8),%ZMM1    [21]

0x419476 VCMPPD	$0x1,%ZMM1,%ZMM7,%K1

0x41947d VPBLENDMD	%YMM18,%YMM19,%YMM2{%K1}

0x419483 VPMOVSXDQ	%YMM2,%ZMM2

0x419489 VPSUBQ	%ZMM5,%ZMM2,%ZMM2

0x41948f VXORPD	%XMM21,%XMM21,%XMM21

0x419495 KXNORW	%K0,%K0,%K2

0x419499 VGATHERQPD	(%R15,%ZMM2,8),%ZMM21{%K2}    [27]

0x4194a0 VPBLENDMD	%YMM18,%YMM20,%YMM23{%K1}

0x4194a6 VPMOVSXDQ	%YMM23,%ZMM23

0x4194ac VPSUBQ	%ZMM5,%ZMM23,%ZMM23

0x4194b2 VXORPD	%XMM24,%XMM24,%XMM24

0x4194b8 KXNORW	%K0,%K0,%K2

0x4194bc VGATHERQPD	(%RBX,%ZMM23,8),%ZMM24{%K2}    [8]

0x4194c3 VPBLENDMD	%YMM22,%YMM20,%YMM23{%K1}

0x4194c9 VANDPD	%ZMM10,%ZMM1,%ZMM25

0x4194cf VXORPD	%XMM26,%XMM26,%XMM26

0x4194d5 KXNORW	%K0,%K0,%K2

0x4194d9 VGATHERQPD	(%R14,%ZMM2,8),%ZMM26{%K2}    [26]

0x4194e0 VDIVPD	%ZMM21,%ZMM25,%ZMM25

0x4194e6 VPMOVSXDQ	%YMM23,%ZMM23

0x4194ec VPSUBQ	%ZMM5,%ZMM23,%ZMM23

0x4194f2 VXORPD	%XMM27,%XMM27,%XMM27

0x4194f8 KXNORW	%K0,%K0,%K2

0x4194fc VGATHERQPD	(%R14,%ZMM23,8),%ZMM27{%K2}    [26]

0x419503 VPBLENDMD	%YMM19,%YMM18,%YMM28{%K1}

0x419509 VMOVAPD	%ZMM9,%ZMM29

0x41950f VFMADD213PD	%ZMM9,%ZMM25,%ZMM29

0x419515 VPMOVSXDQ	%YMM28,%ZMM28

0x41951b VPSUBQ	%ZMM5,%ZMM28,%ZMM28

0x419521 VXORPD	%XMM30,%XMM30,%XMM30

0x419527 KXNORW	%K0,%K0,%K1

0x41952b VGATHERQPD	(%R14,%ZMM28,8),%ZMM30{%K1}    [26]

0x419532 VDIVPD	%ZMM24,%ZMM29,%ZMM24

0x419538 VSUBPD	%ZMM25,%ZMM12,%ZMM29

0x41953e VSUBPD	%ZMM27,%ZMM26,%ZMM27

0x419544 VSUBPD	%ZMM26,%ZMM30,%ZMM30

0x41954a VMULPD	%ZMM27,%ZMM30,%ZMM31

0x419550 VCMPPD	$0x1,%ZMM31,%ZMM7,%K1

0x419557 VSUBPD	%ZMM25,%ZMM11,%ZMM25

0x41955d VFPCLASSPD	$0x56,%ZMM30,%K2

0x419564 VXORPD	%ZMM13,%ZMM25,%ZMM25{%K2}

0x41956a VANDPD	%ZMM10,%ZMM27,%ZMM27

0x419570 VANDPD	%ZMM10,%ZMM30,%ZMM30

0x419576 VMULPD	%ZMM24,%ZMM27,%ZMM31

0x41957c VFMADD231PD	%ZMM29,%ZMM30,%ZMM31

0x419582 VMULPD	%ZMM14,%ZMM31,%ZMM31

0x419588 VMINPD	%ZMM31,%ZMM30,%ZMM30

0x41958e VMINPD	%ZMM30,%ZMM27,%ZMM27

0x419594 VMULPD	%ZMM21,%ZMM26,%ZMM21

0x41959a VFMADD231PD	%ZMM25,%ZMM27,%ZMM26{%K1}

0x4195a0 VMULPD	%ZMM1,%ZMM26,%ZMM1

0x4195a6 MOV	0x20(%RSP),%R12    [10]

0x4195ab VMOVUPD	%ZMM1,(%R12,%RSI,8)    [20]

0x4195b2 VXORPD	%XMM25,%XMM25,%XMM25

0x4195b8 KXNORW	%K0,%K0,%K1

0x4195bc VGATHERQPD	(%R8,%ZMM2,8),%ZMM25{%K1}    [1]

0x4195c3 VXORPD	%XMM2,%XMM2,%XMM2

0x4195c7 KXNORW	%K0,%K0,%K1

0x4195cb VGATHERQPD	(%R8,%ZMM23,8),%ZMM2{%K1}    [1]

0x4195d2 VXORPD	%XMM23,%XMM23,%XMM23

0x4195d8 KXNORW	%K0,%K0,%K1

0x4195dc VGATHERQPD	(%R8,%ZMM28,8),%ZMM23{%K1}    [1]

0x4195e3 VSUBPD	%ZMM2,%ZMM25,%ZMM2

0x4195e9 VSUBPD	%ZMM25,%ZMM23,%ZMM23

0x4195ef VMULPD	%ZMM2,%ZMM23,%ZMM26

0x4195f5 VCMPPD	$0x1,%ZMM26,%ZMM7,%K1

0x4195fc VANDPD	%ZMM10,%ZMM1,%ZMM26

0x419602 VDIVPD	%ZMM21,%ZMM26,%ZMM21

0x419608 VSUBPD	%ZMM21,%ZMM11,%ZMM21

0x41960e VFPCLASSPD	$0x56,%ZMM23,%K2

0x419615 VXORPD	%ZMM13,%ZMM21,%ZMM21{%K2}

0x41961b VANDPD	%ZMM10,%ZMM2,%ZMM2

0x419621 VANDPD	%ZMM10,%ZMM23,%ZMM23

0x419627 VMULPD	%ZMM24,%ZMM2,%ZMM24

0x41962d VFMADD231PD	%ZMM29,%ZMM23,%ZMM24

0x419633 VMULPD	%ZMM14,%ZMM24,%ZMM24

0x419639 VMINPD	%ZMM24,%ZMM23,%ZMM23

0x41963f VMINPD	%ZMM23,%ZMM2,%ZMM2

0x419645 VFMADD231PD	%ZMM21,%ZMM2,%ZMM25{%K1}

0x41964b VMULPD	%ZMM1,%ZMM25,%ZMM1

0x419651 MOV	0x10(%RSP),%R12    [10]

0x419656 VMOVUPD	%ZMM1,(%R12,%RSI,8)    [19]

0x41965d MOV	0x28(%RSP),%R12    [10]

0x419662 VMOVUPD	(%R12,%RSI,8),%ZMM1    [18]

0x419669 VCMPPD	$0x1,%ZMM1,%ZMM7,%K1

0x419670 VPBLENDMD	%YMM19,%YMM18,%YMM2{%K1}

0x419676 VMOVDQA32	%YMM18,%YMM19{%K1}

0x41967c VPMOVSXDQ	%YMM19,%ZMM19

0x419682 VPSUBQ	%ZMM5,%ZMM19,%ZMM19

0x419688 VXORPD	%XMM21,%XMM21,%XMM21

0x41968e KXNORW	%K0,%K0,%K2

0x419692 VGATHERQPD	(%R10,%ZMM19,8),%ZMM21{%K2}    [9]

0x419699 VPBLENDMD	%YMM22,%YMM20,%YMM22{%K1}

0x41969f VMOVDQA32	%YMM18,%YMM20{%K1}

0x4196a5 VPMOVSXDQ	%YMM20,%ZMM18

0x4196ab VPSUBQ	%ZMM5,%ZMM18,%ZMM18

0x4196b1 VPXORD	%XMM20,%XMM20,%XMM20

0x4196b7 KXNORW	%K0,%K0,%K1

0x4196bb VGATHERQPD	(%RBX,%ZMM18,8),%ZMM20{%K1}    [8]

0x4196c2 VANDPD	%ZMM10,%ZMM1,%ZMM18

0x4196c8 VXORPD	%XMM23,%XMM23,%XMM23

0x4196ce KXNORW	%K0,%K0,%K1

0x4196d2 VGATHERQPD	(%RCX,%ZMM19,8),%ZMM23{%K1}    [11]

0x4196d9 VDIVPD	%ZMM21,%ZMM18,%ZMM18

0x4196df VPMOVSXDQ	%YMM22,%ZMM22

0x4196e5 VPSUBQ	%ZMM5,%ZMM22,%ZMM22

0x4196eb VXORPD	%XMM24,%XMM24,%XMM24

0x4196f1 KXNORW	%K0,%K0,%K1

0x4196f5 VGATHERQPD	(%RCX,%ZMM22,8),%ZMM24{%K1}    [11]

0x4196fc VFMADD213PD	%ZMM9,%ZMM18,%ZMM9

0x419702 VPMOVSXDQ	%YMM2,%ZMM2

0x419708 VPSUBQ	%ZMM5,%ZMM2,%ZMM2

0x41970e VXORPD	%XMM25,%XMM25,%XMM25

0x419714 KXNORW	%K0,%K0,%K1

0x419718 VGATHERQPD	(%RCX,%ZMM2,8),%ZMM25{%K1}    [11]

0x41971f VDIVPD	%ZMM20,%ZMM9,%ZMM9

0x419725 VSUBPD	%ZMM18,%ZMM12,%ZMM20

0x41972b VSUBPD	%ZMM24,%ZMM23,%ZMM24

0x419731 VSUBPD	%ZMM23,%ZMM25,%ZMM25

0x419737 VMULPD	%ZMM24,%ZMM25,%ZMM26

0x41973d VCMPPD	$0x1,%ZMM26,%ZMM7,%K1

0x419744 VSUBPD	%ZMM18,%ZMM11,%ZMM18

0x41974a VFPCLASSPD	$0x56,%ZMM25,%K2

0x419751 VXORPD	%ZMM13,%ZMM18,%ZMM18{%K2}

0x419757 VANDPD	%ZMM10,%ZMM24,%ZMM24

0x41975d VANDPD	%ZMM10,%ZMM25,%ZMM25

0x419763 VMULPD	%ZMM9,%ZMM24,%ZMM26

0x419769 VFMADD231PD	%ZMM20,%ZMM25,%ZMM26

0x41976f VMULPD	%ZMM14,%ZMM26,%ZMM26

0x419775 VMINPD	%ZMM26,%ZMM25,%ZMM25

0x41977b VMINPD	%ZMM25,%ZMM24,%ZMM24

0x419781 VMULPD	%ZMM21,%ZMM23,%ZMM21

0x419787 VFMADD231PD	%ZMM18,%ZMM24,%ZMM23{%K1}

0x41978d VMULPD	%ZMM1,%ZMM23,%ZMM1

0x419793 MOV	0x8(%RSP),%R12    [10]

0x419798 VMOVUPD	%ZMM1,(%R12,%RSI,8)    [17]

0x41979f VXORPD	%XMM18,%XMM18,%XMM18

0x4197a5 KXNORW	%K0,%K0,%K1

0x4197a9 VGATHERQPD	(%RAX,%ZMM19,8),%ZMM18{%K1}    [14]

0x4197b0 VXORPD	%XMM19,%XMM19,%XMM19

0x4197b6 KXNORW	%K0,%K0,%K1

0x4197ba VGATHERQPD	(%RAX,%ZMM22,8),%ZMM19{%K1}    [14]

0x4197c1 VXORPD	%XMM22,%XMM22,%XMM22

0x4197c7 KXNORW	%K0,%K0,%K1

0x4197cb VGATHERQPD	(%RAX,%ZMM2,8),%ZMM22{%K1}    [14]

0x4197d2 VSUBPD	%ZMM19,%ZMM18,%ZMM2

0x4197d8 VSUBPD	%ZMM18,%ZMM22,%ZMM19

0x4197de VANDPD	%ZMM10,%ZMM1,%ZMM22

0x4197e4 VDIVPD	%ZMM21,%ZMM22,%ZMM21

0x4197ea VMULPD	%ZMM2,%ZMM19,%ZMM22

0x4197f0 VCMPPD	$0x1,%ZMM22,%ZMM7,%K1

0x4197f7 VSUBPD	%ZMM21,%ZMM11,%ZMM21

0x4197fd VFPCLASSPD	$0x56,%ZMM19,%K2

0x419804 VXORPD	%ZMM13,%ZMM21,%ZMM21{%K2}

0x41980a VANDPD	%ZMM10,%ZMM2,%ZMM2

0x419810 VANDPD	%ZMM10,%ZMM19,%ZMM19

0x419816 VMULPD	%ZMM9,%ZMM2,%ZMM9

0x41981c VFMADD231PD	%ZMM20,%ZMM19,%ZMM9

0x419822 VMULPD	%ZMM14,%ZMM9,%ZMM9

0x419828 VMINPD	%ZMM9,%ZMM19,%ZMM9

0x41982e VMINPD	%ZMM9,%ZMM2,%ZMM2

0x419834 VFMADD231PD	%ZMM21,%ZMM2,%ZMM18{%K1}

0x41983a VMULPD	%ZMM1,%ZMM18,%ZMM1

0x419840 MOV	0x1a0(%RSP),%R12    [10]

0x419848 VMOVUPD	%ZMM1,(%R12,%RSI,8)    [16]

0x41984f ADD	$0x8,%RSI

0x419853 CMP	0x90(%RSP),%RSI    [10]

0x41985b JBE	419020

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 83 - 157

--------------------------------------------------------------------------------

83:     IF(dir.EQ.g_xdir) THEN

[...]

112:           IF(vol_flux_x(j,k).GT.0.0)THEN

[...]

118:             upwind   =MIN(j+1,x_max+2)

[...]

124:           sigmat=ABS(vol_flux_x(j,k))/pre_vol(donor,k)

125:           sigma3=(1.0_8+sigmat)*(vertexdx(j)/vertexdx(dif))

126:           sigma4=2.0_8-sigmat

127:

128:           sigma=sigmat

129:           sigmav=sigmat

130:

131:           diffuw=density1(donor,k)-density1(upwind,k)

132:           diffdw=density1(downwind,k)-density1(donor,k)

133:           wind=1.0_8

134:           IF(diffdw.LE.0.0) wind=-1.0_8

135:           IF(diffuw*diffdw.GT.0.0)THEN

136:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

137:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

138:           ELSE

139:             limiter=0.0

140:           ENDIF

141:           mass_flux_x(j,k)=vol_flux_x(j,k)*(density1(donor,k)+limiter)

142:

143:           sigmam=ABS(mass_flux_x(j,k))/(density1(donor,k)*pre_vol(donor,k))

144:           diffuw=energy1(donor,k)-energy1(upwind,k)

145:           diffdw=energy1(downwind,k)-energy1(donor,k)

146:           wind=1.0_8

147:           IF(diffdw.LE.0.0) wind=-1.0_8

148:           IF(diffuw*diffdw.GT.0.0)THEN

149:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

150:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

151:           ELSE

152:             limiter=0.0

153:           ENDIF

154:

155:           ener_flux(j,k)=mass_flux_x(j,k)*(energy1(donor,k)+limiter)

156:

157:         ENDDO

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P0,
Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source	advec_cell_kernel.f90:83-83,advec_cell_kernel.f90:112-112,advec_cell_kernel.f90:118-118,advec_cell_kernel.f90:124-157
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	192.00
CQA cycles if no scalar integer	192.00
CQA cycles if FP arith vectorized	192.00
CQA cycles if fully vectorized	192.00
Front-end cycles	84.17
P0 cycles	176.50
P1 cycles	42.00
P2 cycles	92.67
P3 cycles	92.67
P4 cycles	4.00
P5 cycles	176.50
P6 cycles	1.60
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	1.40
P11 cycles	92.67
DIV/SQRT cycles	192.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	354.00
Nb uops	505.00
Nb loads	54.00
Nb stores	8.00
Nb stack references	17.00
FLOP/cycle	4.83
Nb FLOP add-sub	224.00
Nb FLOP mul	288.00
Nb FLOP fma	160.00
Nb FLOP div	96.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.71
Bytes prefetched	0.00
Bytes loaded	2504.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	13.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	13.00
Vectorization ratio all	99.34
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	98.84
Vector-efficiency ratio all	85.44
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	96.88
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	75.40

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P0,
Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source	advec_cell_kernel.f90:83-83,advec_cell_kernel.f90:112-112,advec_cell_kernel.f90:118-118,advec_cell_kernel.f90:124-157
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	192.00
CQA cycles if no scalar integer	192.00
CQA cycles if FP arith vectorized	192.00
CQA cycles if fully vectorized	192.00
Front-end cycles	84.17
P0 cycles	176.50
P1 cycles	42.00
P2 cycles	92.67
P3 cycles	92.67
P4 cycles	4.00
P5 cycles	176.50
P6 cycles	1.60
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	1.40
P11 cycles	92.67
DIV/SQRT cycles	192.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	354.00
Nb uops	505.00
Nb loads	54.00
Nb stores	8.00
Nb stack references	17.00
FLOP/cycle	4.83
Nb FLOP add-sub	224.00
Nb FLOP mul	288.00
Nb FLOP fma	160.00
Nb FLOP div	96.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.71
Bytes prefetched	0.00
Bytes loaded	2504.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	13.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	13.00
Vectorization ratio all	99.34
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	98.84
Vector-efficiency ratio all	85.44
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	96.88
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	75.40

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	advec_cell_kernel.f90:83-157
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:83,112,118,124-157.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 85% of vector register length is used (average across all SSE/AVX instructions).

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

98% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 192.00 to 176.50 cycles (1.09x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 192.00 to 158.50 cycles (1.21x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 160 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 12 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:143
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:143
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:143
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:143
VGATHERQPD: 32 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 32 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVQD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:118

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

132 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 928 FP arithmetical operations:

384: addition or subtraction (160 inside FMA instructions)
448: multiply (160 inside FMA instructions)
96: divide

The binary loop is loading 2504 bytes (313 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	354
nb uops	505
loop length	2113
used x86 registers	15
used mmx registers	0
used xmm registers	14
used ymm registers	13
used zmm registers	26
nb stack references	17
ADD-SUB / MUL ratio	0.78

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	84.17 cycles
front end	84.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	176.50	18.00	92.67	92.67	4.00	176.50	1.60	4.00	4.00	4.00	1.40	92.67
cycles	176.50	42.00	92.67	92.67	4.00	176.50	1.60	4.00	4.00	4.00	1.40	92.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	192.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	84.17
Dispatch	176.50
DIV/SQRT	192.00
Data deps.	1.00
Overall L1	192.00

Vectorization ratios

INT

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	94%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	99%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	98%

Vector efficiency ratios

INT

all	63%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	92%
fma	NA (no fma vectorizable/vectorized instructions)
other	49%

all	90%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	83%

INT+FP

all	85%
load	100%
store	100%
mul	100%
add-sub	96%
fma	100%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 192.00 cycles. At this rate:

6% of peak load performance is reached (13.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 419020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTQ %R12,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%R9,%RSI,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTD %R12D,%YMM21	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV 0x58(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM23,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPADDQ %ZMM8,%ZMM18,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVQD %ZMM20,%YMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPADDD %YMM16,%YMM21,%YMM18	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBLENDMD %YMM18,%YMM19,%YMM22{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM22,%ZMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM22,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
MOV 0x50(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VGATHERQPD (%R12,%ZMM24,8),%ZMM25{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPCMPGTQ %ZMM20,%ZMM0,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	0-3	1	vect (100.0%)
VMOVDQA64 %YMM4,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPADDD %YMM15,%YMM21,%YMM20{%K2}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBLENDMD %YMM18,%YMM20,%YMM22{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM22,%ZMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM22,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RBX,%ZMM22,8),%ZMM26{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDD %YMM17,%YMM21,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBLENDMD %YMM22,%YMM20,%YMM21{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VANDPD %ZMM10,%ZMM23,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDX,%ZMM24,8),%ZMM28{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM25,%ZMM27,%ZMM27	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM21,%ZMM21	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM21,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDX,%ZMM29,8),%ZMM30{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM19,%YMM18,%YMM31{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
MOV 0x98(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM27,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMOVSXDQ %YMM31,%ZMM31	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM31,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDX,%ZMM31,8),%ZMM1{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM26,%ZMM21,%ZMM21	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM27,%ZMM12,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM30,%ZMM28,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM28,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM30,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM2,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM27,%ZMM11,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM1,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM2,%ZMM2{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM30,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM27,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM1,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM30,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM1,%ZMM27,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM25,%ZMM28,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM1,%ZMM28{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM28,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0xf0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R11,%ZMM24,8),%ZMM2{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R11,%ZMM29,8),%ZMM23{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R11,%ZMM31,8),%ZMM24{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM23,%ZMM2,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM24,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM27,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM25,%ZMM27,%ZMM25	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM25,%ZMM11,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM24,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM25,%ZMM25{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM23,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM24,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM21,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM21,%ZMM24,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM21,%ZMM23,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM21,%ZMM2{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM2,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0xa0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV 0x68(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM1,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPBLENDMD %YMM18,%YMM19,%YMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM2,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
MOV 0x48(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VGATHERQPD (%R12,%ZMM2,8),%ZMM21{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM18,%YMM20,%YMM23{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM23,%ZMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RBX,%ZMM23,8),%ZMM24{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM22,%YMM20,%YMM23{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VANDPD %ZMM10,%ZMM1,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R13,%ZMM2,8),%ZMM26{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM21,%ZMM25,%ZMM25	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM23,%ZMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R13,%ZMM23,8),%ZMM27{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM19,%YMM18,%YMM28{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVAPD %ZMM9,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM25,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMOVSXDQ %YMM28,%ZMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM28,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R13,%ZMM28,8),%ZMM30{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM24,%ZMM29,%ZMM24	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM25,%ZMM12,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM27,%ZMM26,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM26,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM27,%ZMM30,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM31,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM25,%ZMM11,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM30,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM25,%ZMM25{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM27,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM27,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM30,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM31,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM31,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM30,%ZMM27,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM26,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM27,%ZMM26{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM26,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x40(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDI,%ZMM2,8),%ZMM25{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDI,%ZMM23,8),%ZMM2{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDI,%ZMM28,8),%ZMM23{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM2,%ZMM25,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM25,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM23,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM26,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM21,%ZMM26,%ZMM21	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM21,%ZMM11,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM23,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM21,%ZMM21{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM2,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM23,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM24,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM23,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM2,%ZMM25{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM25,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0xa8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV 0x18(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM1,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPBLENDMD %YMM18,%YMM19,%YMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM2,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R15,%ZMM2,8),%ZMM21{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM18,%YMM20,%YMM23{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM23,%ZMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RBX,%ZMM23,8),%ZMM24{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM22,%YMM20,%YMM23{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VANDPD %ZMM10,%ZMM1,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R14,%ZMM2,8),%ZMM26{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM21,%ZMM25,%ZMM25	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM23,%ZMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R14,%ZMM23,8),%ZMM27{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM19,%YMM18,%YMM28{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVAPD %ZMM9,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM25,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMOVSXDQ %YMM28,%ZMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM28,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R14,%ZMM28,8),%ZMM30{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM24,%ZMM29,%ZMM24	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM25,%ZMM12,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM27,%ZMM26,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM26,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM27,%ZMM30,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM31,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM25,%ZMM11,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM30,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM25,%ZMM25{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM27,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM27,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM30,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM31,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM31,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM30,%ZMM27,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM26,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM27,%ZMM26{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM26,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x20(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R8,%ZMM2,8),%ZMM25{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R8,%ZMM23,8),%ZMM2{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R8,%ZMM28,8),%ZMM23{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM2,%ZMM25,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM25,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM23,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM26,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM21,%ZMM26,%ZMM21	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM21,%ZMM11,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM23,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM21,%ZMM21{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM2,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM23,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM24,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM23,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM2,%ZMM25{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM25,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x10(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV 0x28(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM1,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPBLENDMD %YMM19,%YMM18,%YMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVDQA32 %YMM18,%YMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPMOVSXDQ %YMM19,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM19,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R10,%ZMM19,8),%ZMM21{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM22,%YMM20,%YMM22{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVDQA32 %YMM18,%YMM20{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPMOVSXDQ %YMM20,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM18,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPXORD %XMM20,%XMM20,%XMM20	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RBX,%ZMM18,8),%ZMM20{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RCX,%ZMM19,8),%ZMM23{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM21,%ZMM18,%ZMM18	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM22,%ZMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM22,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RCX,%ZMM22,8),%ZMM24{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM18,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMOVSXDQ %YMM2,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RCX,%ZMM2,8),%ZMM25{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM20,%ZMM9,%ZMM9	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM18,%ZMM12,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM24,%ZMM23,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM23,%ZMM25,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM25,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM26,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM18,%ZMM11,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM25,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM18,%ZMM18{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM25,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM24,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM25,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM26,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM26,%ZMM25,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM25,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM23,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM18,%ZMM24,%ZMM23{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM23,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RAX,%ZMM19,8),%ZMM18{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RAX,%ZMM22,8),%ZMM19{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM22,%XMM22,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RAX,%ZMM2,8),%ZMM22{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM19,%ZMM18,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM18,%ZMM22,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM21,%ZMM22,%ZMM21	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM2,%ZMM19,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM22,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM21,%ZMM11,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM19,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM21,%ZMM21{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM19,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM2,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM19,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM9,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM9,%ZMM19,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM9,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM2,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM18,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x1a0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x90(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JBE 419020 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x2d60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	advec_cell_kernel.f90:83-157
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 85% of vector register length is used (average across all SSE/AVX instructions).

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

98% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 192.00 to 158.50 cycles (1.21x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 160 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 12 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:143
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:143
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:143
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:143
VGATHERQPD: 32 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 32 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:124
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:125
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:132
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:144
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:145

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVQD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:118

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

132 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 928 FP arithmetical operations:

384: addition or subtraction (160 inside FMA instructions)
448: multiply (160 inside FMA instructions)
96: divide

The binary loop is loading 2504 bytes (313 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	354
nb uops	505
loop length	2113
used x86 registers	15
used mmx registers	0
used xmm registers	14
used ymm registers	13
used zmm registers	26
nb stack references	17
ADD-SUB / MUL ratio	0.78

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	84.17 cycles
front end	84.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	176.50	18.00	92.67	92.67	4.00	176.50	1.60	4.00	4.00	4.00	1.40	92.67
cycles	176.50	42.00	92.67	92.67	4.00	176.50	1.60	4.00	4.00	4.00	1.40	92.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	192.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	84.17
Dispatch	176.50
DIV/SQRT	192.00
Data deps.	1.00
Overall L1	192.00

Vectorization ratios

INT

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	94%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	99%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	98%

Vector efficiency ratios

INT

all	63%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	92%
fma	NA (no fma vectorizable/vectorized instructions)
other	49%

all	90%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	83%

INT+FP

all	85%
load	100%
store	100%
mul	100%
add-sub	96%
fma	100%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 192.00 cycles. At this rate:

6% of peak load performance is reached (13.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 419020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTQ %R12,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%R9,%RSI,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTD %R12D,%YMM21	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV 0x58(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM23,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPADDQ %ZMM8,%ZMM18,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVQD %ZMM20,%YMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPADDD %YMM16,%YMM21,%YMM18	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBLENDMD %YMM18,%YMM19,%YMM22{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM22,%ZMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM22,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
MOV 0x50(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VGATHERQPD (%R12,%ZMM24,8),%ZMM25{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPCMPGTQ %ZMM20,%ZMM0,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	0-3	1	vect (100.0%)
VMOVDQA64 %YMM4,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPADDD %YMM15,%YMM21,%YMM20{%K2}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBLENDMD %YMM18,%YMM20,%YMM22{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM22,%ZMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM22,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RBX,%ZMM22,8),%ZMM26{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDD %YMM17,%YMM21,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBLENDMD %YMM22,%YMM20,%YMM21{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VANDPD %ZMM10,%ZMM23,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDX,%ZMM24,8),%ZMM28{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM25,%ZMM27,%ZMM27	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM21,%ZMM21	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM21,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDX,%ZMM29,8),%ZMM30{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM19,%YMM18,%YMM31{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
MOV 0x98(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM27,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMOVSXDQ %YMM31,%ZMM31	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM31,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDX,%ZMM31,8),%ZMM1{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM26,%ZMM21,%ZMM21	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM27,%ZMM12,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM30,%ZMM28,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM28,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM30,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM2,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM27,%ZMM11,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM1,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM2,%ZMM2{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM30,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM27,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM1,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM30,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM1,%ZMM27,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM25,%ZMM28,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM1,%ZMM28{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM28,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0xf0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R11,%ZMM24,8),%ZMM2{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R11,%ZMM29,8),%ZMM23{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R11,%ZMM31,8),%ZMM24{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM23,%ZMM2,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM24,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM27,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM25,%ZMM27,%ZMM25	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM25,%ZMM11,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM24,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM25,%ZMM25{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM23,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM24,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM21,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM21,%ZMM24,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM21,%ZMM23,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM21,%ZMM2{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM2,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0xa0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV 0x68(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM1,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPBLENDMD %YMM18,%YMM19,%YMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM2,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
MOV 0x48(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VGATHERQPD (%R12,%ZMM2,8),%ZMM21{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM18,%YMM20,%YMM23{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM23,%ZMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RBX,%ZMM23,8),%ZMM24{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM22,%YMM20,%YMM23{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VANDPD %ZMM10,%ZMM1,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R13,%ZMM2,8),%ZMM26{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM21,%ZMM25,%ZMM25	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM23,%ZMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R13,%ZMM23,8),%ZMM27{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM19,%YMM18,%YMM28{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVAPD %ZMM9,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM25,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMOVSXDQ %YMM28,%ZMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM28,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R13,%ZMM28,8),%ZMM30{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM24,%ZMM29,%ZMM24	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM25,%ZMM12,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM27,%ZMM26,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM26,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM27,%ZMM30,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM31,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM25,%ZMM11,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM30,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM25,%ZMM25{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM27,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM27,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM30,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM31,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM31,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM30,%ZMM27,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM26,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM27,%ZMM26{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM26,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x40(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDI,%ZMM2,8),%ZMM25{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDI,%ZMM23,8),%ZMM2{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RDI,%ZMM28,8),%ZMM23{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM2,%ZMM25,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM25,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM23,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM26,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM21,%ZMM26,%ZMM21	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM21,%ZMM11,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM23,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM21,%ZMM21{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM2,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM23,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM24,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM23,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM2,%ZMM25{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM25,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0xa8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV 0x18(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM1,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPBLENDMD %YMM18,%YMM19,%YMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM2,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R15,%ZMM2,8),%ZMM21{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM18,%YMM20,%YMM23{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM23,%ZMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RBX,%ZMM23,8),%ZMM24{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM22,%YMM20,%YMM23{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VANDPD %ZMM10,%ZMM1,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R14,%ZMM2,8),%ZMM26{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM21,%ZMM25,%ZMM25	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM23,%ZMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R14,%ZMM23,8),%ZMM27{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM19,%YMM18,%YMM28{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVAPD %ZMM9,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM25,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMOVSXDQ %YMM28,%ZMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM28,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R14,%ZMM28,8),%ZMM30{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM24,%ZMM29,%ZMM24	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM25,%ZMM12,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM27,%ZMM26,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM26,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM27,%ZMM30,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM31,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM25,%ZMM11,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM30,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM25,%ZMM25{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM27,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM27,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM30,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM31,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM31,%ZMM30,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM30,%ZMM27,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM26,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM27,%ZMM26{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM26,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x20(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R8,%ZMM2,8),%ZMM25{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R8,%ZMM23,8),%ZMM2{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R8,%ZMM28,8),%ZMM23{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM2,%ZMM25,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM25,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM23,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM26,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM21,%ZMM26,%ZMM21	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM21,%ZMM11,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM23,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM21,%ZMM21{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM2,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM23,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM24,%ZMM23,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM23,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM2,%ZMM25{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM25,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x10(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV 0x28(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%RSI,8),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM1,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPBLENDMD %YMM19,%YMM18,%YMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVDQA32 %YMM18,%YMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPMOVSXDQ %YMM19,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM19,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%R10,%ZMM19,8),%ZMM21{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %YMM22,%YMM20,%YMM22{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVDQA32 %YMM18,%YMM20{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPMOVSXDQ %YMM20,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM18,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPXORD %XMM20,%XMM20,%XMM20	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RBX,%ZMM18,8),%ZMM20{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RCX,%ZMM19,8),%ZMM23{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM21,%ZMM18,%ZMM18	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM22,%ZMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM22,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RCX,%ZMM22,8),%ZMM24{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM18,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMOVSXDQ %YMM2,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM5,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RCX,%ZMM2,8),%ZMM25{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM20,%ZMM9,%ZMM9	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM18,%ZMM12,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM24,%ZMM23,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM23,%ZMM25,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM25,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM26,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM18,%ZMM11,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM25,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM18,%ZMM18{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM25,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM24,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM25,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM26,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM26,%ZMM25,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM25,%ZMM24,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM23,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM18,%ZMM24,%ZMM23{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM23,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RAX,%ZMM19,8),%ZMM18{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RAX,%ZMM22,8),%ZMM19{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM22,%XMM22,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (%RAX,%ZMM2,8),%ZMM22{%K1}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM19,%ZMM18,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM18,%ZMM22,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM1,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM21,%ZMM22,%ZMM21	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM2,%ZMM19,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM22,%ZMM7,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM21,%ZMM11,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM19,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VXORPD %ZMM13,%ZMM21,%ZMM21{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM19,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM2,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM19,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM9,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM9,%ZMM19,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM9,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM2,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM18,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x1a0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM1,(%R12,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x90(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JBE 419020 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x2d60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code