OV - exec - Loop 58

	Loop Id: 58	Module: exec	Source: PdV_kernel.f90:69-99 [...]	Coverage: 5.61%

0x413d80 VMOVUPD	-0x8(%RDI,%R13,8),%ZMM5    [14]

0x413d8b VMOVUPD	(%RDI,%R13,8),%ZMM6    [14]

0x413d92 VADDPD	-0x8(%RCX,%R13,8),%ZMM5,%ZMM5    [1]

0x413d9d VMULPD	-0x8(%RSI,%R13,8),%ZMM4,%ZMM7    [13]

0x413da8 VADDPD	(%RCX,%R13,8),%ZMM6,%ZMM6    [1]

0x413daf VMULPD	(%RSI,%R13,8),%ZMM4,%ZMM8    [13]

0x413db6 VMOVUPD	(%R14,%R13,8),%ZMM9    [5]

0x413dbd VADDPD	-0x8(%R14,%R13,8),%ZMM9,%ZMM9    [5]

0x413dc8 VMULPD	(%R8,%R13,8),%ZMM4,%ZMM10    [3]

0x413dcf VMULPD	%ZMM9,%ZMM10,%ZMM9

0x413dd5 VFMADD231PD	%ZMM7,%ZMM5,%ZMM9

0x413ddb VMOVUPD	(%RDX,%R13,8),%ZMM5    [10]

0x413de2 VADDPD	-0x8(%RDX,%R13,8),%ZMM5,%ZMM5    [10]

0x413ded VMULPD	(%R9,%R13,8),%ZMM4,%ZMM7    [8]

0x413df4 VFNMADD231PD	%ZMM8,%ZMM6,%ZMM9

0x413dfa VFMSUB213PD	%ZMM9,%ZMM5,%ZMM7

0x413e00 VMOVUPD	(%R12,%R13,8),%ZMM5    [4]

0x413e07 VMOVUPD	(%R10,%R13,8),%ZMM6    [11]

0x413e0e VADDPD	(%RAX,%R13,8),%ZMM6,%ZMM6    [2]

0x413e15 VMULPD	%ZMM6,%ZMM7,%ZMM6

0x413e1b VMULPD	(%R15,%R13,8),%ZMM5,%ZMM8    [6]

0x413e22 VDIVPD	%ZMM8,%ZMM6,%ZMM6

0x413e28 VADDPD	%ZMM5,%ZMM7,%ZMM5

0x413e2e VMOVUPD	(%R11,%R13,8),%ZMM7    [12]

0x413e35 VSUBPD	%ZMM6,%ZMM7,%ZMM6

0x413e3b VDIVPD	%ZMM5,%ZMM8,%ZMM5

0x413e41 MOV	-0x1c0(%RBP),%RBX    [9]

0x413e48 VMOVUPD	%ZMM6,(%RBX,%R13,8)    [7]

0x413e4f MOV	-0x1c8(%RBP),%RBX    [9]

0x413e56 VMOVUPD	%ZMM5,(%RBX,%R13,8)    [15]

0x413e5d ADD	$0x8,%R13

0x413e61 CMP	-0x30(%RBP),%R13    [9]

0x413e65 JB	413d80

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 69 - 99

--------------------------------------------------------------------------------

69:     IF(predict)THEN

[...]

75:         DO j=x_min,x_max

76:

77:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

78:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

79:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

80:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

81:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

82:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

83:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

84:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

85:           total_flux=right_flux-left_flux+top_flux-bottom_flux

86:

87:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

95:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

96:

97:           energy1(j,k)=energy0(j,k)-energy_change

98:

99:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.78
Bottlenecks	P0,
Function	pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2
Source	PdV_kernel.f90:69-69,PdV_kernel.f90:75-87,PdV_kernel.f90:95-99
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	32.00
CQA cycles if fully vectorized	32.00
Front-end cycles	7.67
P0 cycles	11.50
P1 cycles	8.50
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	1.00
P5 cycles	11.50
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	6.67
DIV/SQRT cycles	32.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	36.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	5.50
Nb FLOP add-sub	56.00
Nb FLOP mul	56.00
Nb FLOP fma	24.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.75
Bytes prefetched	0.00
Bytes loaded	1112.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.78
Bottlenecks	P0,
Function	pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2
Source	PdV_kernel.f90:69-69,PdV_kernel.f90:75-87,PdV_kernel.f90:95-99
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	32.00
CQA cycles if fully vectorized	32.00
Front-end cycles	7.67
P0 cycles	11.50
P1 cycles	8.50
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	1.00
P5 cycles	11.50
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	6.67
DIV/SQRT cycles	32.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	36.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	5.50
Nb FLOP add-sub	56.00
Nb FLOP mul	56.00
Nb FLOP fma	24.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.75
Bytes prefetched	0.00
Bytes loaded	1112.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	PdV_kernel.f90:69-99
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:69,75-87,95-99.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 32.00 to 11.50 cycles (2.78x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.00 to 9.50 cycles (3.37x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:95
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:99

Type of elements and instruction set

19 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 176 FP arithmetical operations:

80: addition or subtraction (24 inside FMA instructions)
80: multiply (24 inside FMA instructions)
16: divide

The binary loop is loading 1112 bytes (139 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	33
nb uops	36
loop length	235
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	7
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.50	0.00	6.67	6.67	1.00	11.50	1.00	1.00	1.00	1.00	0.00	6.67
cycles	11.50	8.50	6.67	6.67	1.00	11.50	1.00	1.00	1.00	1.00	0.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	32.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.67
Dispatch	11.50
DIV/SQRT	32.00
Data deps.	1.00
Overall L1	32.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

18% of peak load performance is reached (34.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 413d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD -0x8(%RDI,%R13,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RDI,%R13,8),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD -0x8(%RCX,%R13,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD -0x8(%RSI,%R13,8),%ZMM4,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD (%RCX,%R13,8),%ZMM6,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%RSI,%R13,8),%ZMM4,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD (%R14,%R13,8),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD -0x8(%R14,%R13,8),%ZMM9,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R8,%R13,8),%ZMM4,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM10,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM5,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%RDX,%R13,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD -0x8(%RDX,%R13,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R9,%R13,8),%ZMM4,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFNMADD231PD %ZMM8,%ZMM6,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMSUB213PD %ZMM9,%ZMM5,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%R12,%R13,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R10,%R13,8),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RAX,%R13,8),%ZMM6,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM6,%ZMM7,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD (%R15,%R13,8),%ZMM5,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VDIVPD %ZMM8,%ZMM6,%ZMM6	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VADDPD %ZMM5,%ZMM7,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R11,%R13,8),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD %ZMM6,%ZMM7,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM5,%ZMM8,%ZMM5	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
MOV -0x1c0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM6,(%RBX,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV -0x1c8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM5,(%RBX,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x30(%RBP),%R13	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JB 413d80 <pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2+0xf60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	PdV_kernel.f90:69-99
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.00 to 9.50 cycles (3.37x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:95
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:99

Type of elements and instruction set

19 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 176 FP arithmetical operations:

80: addition or subtraction (24 inside FMA instructions)
80: multiply (24 inside FMA instructions)
16: divide

The binary loop is loading 1112 bytes (139 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	33
nb uops	36
loop length	235
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	7
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.50	0.00	6.67	6.67	1.00	11.50	1.00	1.00	1.00	1.00	0.00	6.67
cycles	11.50	8.50	6.67	6.67	1.00	11.50	1.00	1.00	1.00	1.00	0.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	32.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.67
Dispatch	11.50
DIV/SQRT	32.00
Data deps.	1.00
Overall L1	32.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

18% of peak load performance is reached (34.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 413d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD -0x8(%RDI,%R13,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RDI,%R13,8),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD -0x8(%RCX,%R13,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD -0x8(%RSI,%R13,8),%ZMM4,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD (%RCX,%R13,8),%ZMM6,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%RSI,%R13,8),%ZMM4,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD (%R14,%R13,8),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD -0x8(%R14,%R13,8),%ZMM9,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R8,%R13,8),%ZMM4,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM10,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM5,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%RDX,%R13,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD -0x8(%RDX,%R13,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R9,%R13,8),%ZMM4,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFNMADD231PD %ZMM8,%ZMM6,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMSUB213PD %ZMM9,%ZMM5,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%R12,%R13,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R10,%R13,8),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RAX,%R13,8),%ZMM6,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM6,%ZMM7,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD (%R15,%R13,8),%ZMM5,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VDIVPD %ZMM8,%ZMM6,%ZMM6	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VADDPD %ZMM5,%ZMM7,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R11,%R13,8),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD %ZMM6,%ZMM7,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM5,%ZMM8,%ZMM5	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
MOV -0x1c0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM6,(%RBX,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV -0x1c8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM5,(%RBX,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x30(%RBP),%R13	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JB 413d80 <pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2+0xf60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code