OV - exec - Loop 260

	Loop Id: 260	Module: exec	Source: pack_kernel.f90:156-160	Coverage: 0.02%

0x432b00 LEA	0x1(%R15),%RAX

0x432b04 IMUL	%RAX,%R11

0x432b08 LEA	-0x1(%R15,%RDX,1),%EAX

0x432b0d IMUL	%EDX,%EAX

0x432b10 MOVSXD	%EAX,%R15

0x432b13 ADD	%R12,%R15

0x432b16 XOR	%EAX,%EAX

0x432b18 VPBROADCASTQ	%RAX,%ZMM8

0x432b1e VPSUBQ	%ZMM8,%ZMM0,%ZMM9

0x432b24 VPCMPNLEUQ	%ZMM1,%ZMM9,%K1

0x432b2b VPMOVQD	%ZMM8,%YMM8

0x432b31 VPSUBD	%YMM8,%YMM7,%YMM7

0x432b36 ADD	%R11,%R9

0x432b39 VPADDD	%YMM2,%YMM7,%YMM7

0x432b3d VPMOVSXDQ	%YMM7,%ZMM7

0x432b43 VPSUBQ	%ZMM3,%ZMM7,%ZMM7

0x432b49 VPMULLQ	%ZMM7,%ZMM6,%ZMM6

0x432b4f KMOVQ	%K1,%K2

0x432b54 VPXOR	%XMM7,%XMM7,%XMM7

0x432b58 VGATHERQPD	(%R9,%ZMM6,1),%ZMM7{%K2}

0x432b5f ADD	%RAX,%R15

0x432b62 VPBROADCASTQ	%R15,%ZMM6

0x432b68 VPADDQ	%ZMM1,%ZMM6,%ZMM6

0x432b6e VPMULLQ	%ZMM6,%ZMM5,%ZMM5

0x432b74 VSCATTERQPD	%ZMM7,(%R10,%ZMM5,1){%K1}

0x432b7b JMP	432b80

0x432b80 LEA	0x1(%R8),%EAX

0x432b84 ADD	%EDX,%EDI

0x432b86 CMP	-0x38(%RBP),%R8D

0x432b8a MOV	%EAX,%R8D

0x432b8d JE	432a10

0x432b93 TEST	%EDX,%EDX

0x432b95 JLE	432b80

0x432b97 MOV	-0x48(%RBP),%RAX

0x432b9b ADD	%R8D,%EAX

0x432b9e MOV	-0x58(%RBP),%RCX

0x432ba2 MOVSXD	(%RCX),%R12

0x432ba5 MOV	(%R13),%R9

0x432ba9 MOV	0x38(%R13),%R10

0x432bad MOV	-0x50(%RBP),%RCX

0x432bb1 MOV	(%RCX),%R14D

0x432bb4 MOV	0x50(%R13),%R11

0x432bb8 VPBROADCASTQ	%R10,%ZMM6

0x432bbe MOV	-0x60(%RBP),%RCX

0x432bc2 MOV	0x38(%RCX),%R10

0x432bc6 VPBROADCASTQ	%R10,%ZMM5

0x432bcc MOV	(%RCX),%R10

0x432bcf MOVSXD	%EAX,%R15

0x432bd2 VPBROADCASTD	%R14D,%YMM7

0x432bd8 TEST	%RSI,%RSI

0x432bdb JE	432b00

0x432be1 MOVSXD	%EDI,%RAX

0x432be4 LEA	0x1(%R15),%RBX

0x432be8 IMUL	%RBX,%R11

0x432bec LEA	(%R9,%R11,1),%RBX

0x432bf0 LEA	-0x1(%R15,%RDX,1),%R15D

0x432bf5 IMUL	%EDX,%R15D

0x432bf9 MOVSXD	%R15D,%R15

0x432bfc ADD	%R12,%R15

0x432bff ADD	%R12,%RAX

0x432c02 XOR	%R12D,%R12D

0x432c05 NOPW	%CS:(%RAX,%RAX,1)

  (261) 0x432c10 VPBROADCASTD	%R14D,%YMM8

  (261) 0x432c16 VPADDD	%YMM2,%YMM8,%YMM8

  (261) 0x432c1a VPMOVSXDQ	%YMM8,%ZMM8

  (261) 0x432c20 VPSUBQ	%ZMM3,%ZMM8,%ZMM8

  (261) 0x432c26 VPMULLQ	%ZMM8,%ZMM6,%ZMM8

  (261) 0x432c2c KXNORW	%K0,%K0,%K1

  (261) 0x432c30 VXORPD	%XMM9,%XMM9,%XMM9

  (261) 0x432c35 VGATHERQPD	(%RBX,%ZMM8,1),%ZMM9{%K1}

  (261) 0x432c3c LEA	(%RAX,%R12,1),%RCX

  (261) 0x432c40 VPBROADCASTQ	%RCX,%ZMM8

  (261) 0x432c46 VPADDQ	%ZMM4,%ZMM8,%ZMM8

  (261) 0x432c4c VPMULLQ	%ZMM8,%ZMM5,%ZMM8

  (261) 0x432c52 KXNORW	%K0,%K0,%K1

  (261) 0x432c56 VSCATTERQPD	%ZMM9,(%R10,%ZMM8,1){%K1}

  (261) 0x432c5d ADD	$0x8,%R12

  (261) 0x432c61 ADD	$-0x8,%R14D

  (261) 0x432c65 CMP	%RSI,%R12

  (261) 0x432c68 JB	432c10

0x432c6a MOV	%RSI,%RAX

0x432c6d CMP	%EDX,%ESI

0x432c6f JNE	432b18

0x432c75 JMP	432b80

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 156 - 160

--------------------------------------------------------------------------------

156:     DO k=y_min-depth,y_max+y_inc+depth

157:     !$OMP SIMD

158:       DO j=1,depth

159:         index= buffer_offset + j+(k+depth-1)*depth

160:         right_snd_buffer(index)=field(x_max+1-j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.42
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks
Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source	pack_kernel.f90:156-160
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.88
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	8.88
CQA cycles if fully vectorized	5.45
Front-end cycles	8.88
P0 cycles	6.85
P1 cycles	5.25
P2 cycles	4.42
P3 cycles	4.42
P4 cycles	2.00
P5 cycles	6.85
P6 cycles	4.85
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	4.80
P11 cycles	4.42
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	53.25
Nb loads	9.75
Nb stores	0.50
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.78
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	24.21
Vectorization ratio load	10.42
Vectorization ratio store	100.00
Vectorization ratio mul	75.00
Vectorization ratio add_sub	38.69
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.54
Vector-efficiency ratio all	26.17
Vector-efficiency ratio load	17.32
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	77.34
Vector-efficiency ratio add_sub	34.78
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.71

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks	micro-operation queue, P0, P1, P5, P6, P10,
Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source	pack_kernel.f90:156-160
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.06
Front-end cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	0.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	6.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00
Bytes prefetched	0.00
Bytes loaded	4.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source	pack_kernel.f90:156-160
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.33
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	13.33
CQA cycles if fully vectorized	9.51
Front-end cycles	13.33
P0 cycles	11.00
P1 cycles	6.40
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	4.00
P5 cycles	11.00
P6 cycles	6.40
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	6.20
P11 cycles	6.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	80.00
Nb loads	13.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.90
Bytes prefetched	0.00
Bytes loaded	148.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	44.83
Vectorization ratio load	16.67
Vectorization ratio store	100.00
Vectorization ratio mul	50.00
Vectorization ratio add_sub	71.43
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	38.46
Vector-efficiency ratio all	42.03
Vector-efficiency ratio load	23.96
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	54.69
Vector-efficiency ratio add_sub	58.93
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	34.62

Metric	Value
CQA speedup if no scalar integer	2.22
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source	pack_kernel.f90:156-160
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	0.48
Front-end cycles	6.67
P0 cycles	4.40
P1 cycles	5.80
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	4.40
P6 cycles	4.40
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.40
P11 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.60
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.13
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.93

Metric	Value
CQA speedup if no scalar integer	1.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue,
Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source	pack_kernel.f90:156-160
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	11.75
Front-end cycles	14.50
P0 cycles	11.00
P1 cycles	7.80
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	4.00
P5 cycles	11.00
P6 cycles	7.60
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	7.60
P11 cycles	6.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	87.00
Nb loads	13.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.62
Bytes prefetched	0.00
Bytes loaded	148.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	52.00
Vectorization ratio load	25.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	83.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	35.71
Vector-efficiency ratio all	47.25
Vector-efficiency ratio load	29.69
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	67.71
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.04

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source file and lines	pack_kernel.f90:156-160
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:156-160.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.88 to 5.45 cycles (1.63x speedup).

Details

24% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

10% of SSE/AVX loads are used in vector version.
38% of SSE/AVX addition or subtraction instructions are used in vector version.
75% of SSE/AVX multiply instructions are used in vector version.
18% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- use the vec-report option to understand why your loop was not vectorized. If "existence of vector dependences", try the IVDEP directive. If, using IVDEP, "vectorization possible but seems inefficient", try the VECTOR ALWAYS directive.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	39
nb uops	53.25
loop length	165.25
used x86 registers	12.25
used mmx registers	0
used xmm registers	0.50
used ymm registers	1.75
used zmm registers	4.50
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	8.88 cycles
front end	8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.85	4.90	4.42	4.42	2.00	6.85	4.85	2.00	2.00	2.00	4.80	4.42
cycles	6.85	5.25	4.42	4.42	2.00	6.85	4.85	2.00	2.00	2.00	4.80	4.42

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.88
Dispatch	7.20
Data deps.	1.00
Overall L1	8.88

Vectorization ratios

INT

all	22%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	75%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	24%
load	10%
store	100%
mul	75%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	23%
load	7%
store	NA (no store vectorizable/vectorized instructions)
mul	77%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	26%
load	17%
store	100%
mul	77%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.88 cycles. At this rate:

4% of peak load performance is reached (9.48 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.30 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source file and lines	pack_kernel.f90:156-160
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.06 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- use the vec-report option to understand why your loop was not vectorized. If "existence of vector dependences", try the IVDEP directive. If, using IVDEP, "vectorization possible but seems inefficient", try the VECTOR ALWAYS directive.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 4 bytes.

General properties

nb instructions	7
nb uops	6
loop length	23
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.00	1.00	0.33	0.33	0.00	1.00	1.00	0.00	0.00	0.00	1.00	0.33
cycles	1.00	1.00	0.33	0.33	0.00	1.00	1.00	0.00	0.00	0.00	1.00	0.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.00
Dispatch	1.00
Data deps.	1.00
Overall L1	1.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.00 to 0.33 cycles (3.00x speedup).

ASM code

In the binary file, the address of the loop is: 432b93

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%R8),%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
ADD %EDX,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMP -0x38(%RBP),%R8D	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 432a10 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x90>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
TEST %EDX,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	N/A
JLE 432b80 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x200>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source file and lines	pack_kernel.f90:156-160
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 10.50 cycles (1.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is poorly vectorized. Only 42% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.33 to 9.51 cycles (1.40x speedup).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
71% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
38% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- use the vec-report option to understand why your loop was not vectorized. If "existence of vector dependences", try the IVDEP directive. If, using IVDEP, "vectorization possible but seems inefficient", try the VECTOR ALWAYS directive.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
VPMULLQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
VSCATTERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
VSCATTERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVQD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 148 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	51
nb uops	80
loop length	222
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	3
used zmm registers	8
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.00	6.40	6.67	6.67	4.00	11.00	6.40	4.00	4.00	4.00	6.20	6.67
cycles	11.00	6.40	6.67	6.67	4.00	11.00	6.40	4.00	4.00	4.00	6.20	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.33
Dispatch	11.00
Data deps.	1.00
Overall L1	13.33

Vectorization ratios

INT

all	40%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	44%
load	16%
store	100%
mul	50%
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Vector efficiency ratios

INT

all	37%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	54%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	29%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	42%
load	23%
store	100%
mul	54%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

5% of peak load performance is reached (11.10 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 432b93

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%R15),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LEA -0x1(%R15,%RDX,1),%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R12,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPBROADCASTQ %RAX,%ZMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM8,%ZMM0,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM1,%ZMM9,%K1																vect (100.0%)
VPMOVQD %ZMM8,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPSUBD %YMM8,%YMM7,%YMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
ADD %R11,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPADDD %YMM2,%YMM7,%YMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM7,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM3,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM7,%ZMM6,%ZMM6	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VPXOR %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERQPD (%R9,%ZMM6,1),%ZMM7{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
ADD %RAX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTQ %R15,%ZMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %ZMM1,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM6,%ZMM5,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VSCATTERQPD %ZMM7,(%R10,%ZMM5,1){%K1}	20	2.20	0.20	0	0	4	0.20	0.20	4	4	4	0.20	0	2-12	7	vect (100.0%)
JMP 432b80 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x200>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA 0x1(%R8),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP -0x38(%RBP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 432a10 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x90>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EDX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 432b80 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R8D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RCX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R13),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%R13),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x50(%R13),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %R10,%ZMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RCX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %R10,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV (%RCX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VPBROADCASTD %R14D,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 432b00 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x180>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source file and lines	pack_kernel.f90:156-160
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.67 to 3.00 cycles (2.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 0.48 cycles (13.91x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- use the vec-report option to understand why your loop was not vectorized. If "existence of vector dependences", try the IVDEP directive. If, using IVDEP, "vectorization possible but seems inefficient", try the VECTOR ALWAYS directive.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 84 bytes.

General properties

nb instructions	40
nb uops	40
loop length	160
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	2
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.67 cycles
front end	6.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.40	4.40	4.00	4.00	0.00	4.40	4.40	0.00	0.00	0.00	4.40	4.00
cycles	4.40	5.80	4.00	4.00	0.00	4.40	4.40	0.00	0.00	0.00	4.40	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.67
Dispatch	5.80
Data deps.	1.00
Overall L1	6.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

6% of peak load performance is reached (12.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 432b93

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%R8),%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
ADD %EDX,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMP -0x38(%RBP),%R8D	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 432a10 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x90>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
TEST %EDX,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (6.3%)
JLE 432b80 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x200>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %R8D,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RCX),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R13),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%R13),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%R14D	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x50(%R13),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %R10,%ZMM6	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RCX),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %R10,%ZMM5	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
MOV (%RCX),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %EAX,%R15	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
VPBROADCASTD %R14D,%YMM7	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
TEST %RSI,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (12.5%)
JE 432b00 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x180>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOVSXD %EDI,%RAX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
LEA 0x1(%R15),%RBX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBX,%R11	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%R9,%R11,1),%RBX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%R15,%RDX,1),%R15D	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%R15D	1	0	1	0	0	0	0	0	0	3	1	N/A
MOVSXD %R15D,%R15	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
ADD %R12,%R15	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %R12,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 432b18 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x198>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JMP 432b80 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x200>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97
Source file and lines	pack_kernel.f90:156-160
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 10.50 cycles (1.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is partially vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.50 to 11.75 cycles (1.23x speedup).

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
83% of SSE/AVX addition or subtraction instructions are used in vector version.
35% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- use the vec-report option to understand why your loop was not vectorized. If "existence of vector dependences", try the IVDEP directive. If, using IVDEP, "vectorization possible but seems inefficient", try the VECTOR ALWAYS directive.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
VPMULLQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
VSCATTERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160
VSCATTERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVQD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 148 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	58
nb uops	87
loop length	256
used x86 registers	15
used mmx registers	0
used xmm registers	1
used ymm registers	3
used zmm registers	8
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.00	7.80	6.67	6.67	4.00	11.00	7.60	4.00	4.00	4.00	7.60	6.67
cycles	11.00	7.80	6.67	6.67	4.00	11.00	7.60	4.00	4.00	4.00	7.60	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.50
Dispatch	11.00
Data deps.	1.00
Overall L1	14.50

Vectorization ratios

INT

all	47%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	52%
load	25%
store	100%
mul	100%
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Vector efficiency ratios

INT

all	42%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	67%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	47%
load	29%
store	100%
mul	100%
add-sub	67%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

5% of peak load performance is reached (10.21 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.41 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 432b93

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %RAX,%ZMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM8,%ZMM0,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM1,%ZMM9,%K1																vect (100.0%)
VPMOVQD %ZMM8,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPSUBD %YMM8,%YMM7,%YMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
ADD %R11,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPADDD %YMM2,%YMM7,%YMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMOVSXDQ %YMM7,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM3,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM7,%ZMM6,%ZMM6	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VPXOR %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERQPD (%R9,%ZMM6,1),%ZMM7{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
ADD %RAX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTQ %R15,%ZMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %ZMM1,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM6,%ZMM5,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VSCATTERQPD %ZMM7,(%R10,%ZMM5,1){%K1}	20	2.20	0.20	0	0	4	0.20	0.20	4	4	4	0.20	0	2-12	7	vect (100.0%)
JMP 432b80 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x200>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA 0x1(%R8),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP -0x38(%RBP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 432a10 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x90>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EDX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 432b80 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RCX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R13),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%R13),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x50(%R13),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %R10,%ZMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RCX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %R10,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV (%RCX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VPBROADCASTD %R14D,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 432b00 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x180>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EDI,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA 0x1(%R15),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R9,%R11,1),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%R15,%RDX,1),%R15D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%R15D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %R15D,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R12,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 432b18 <pack_kernel_module_mp_clover_pack_message_right_.DIR.OMP.PARALLEL.LOOP.2.split97+0x198>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions