OV - exec - Loop 182

0x42b990 VMULPD	(%R11,%RDX,8),%ZMM3,%ZMM4    [2]

0x42b997 VMOVUPD	(%R13,%RDX,8),%ZMM5    [5]

0x42b99f VADDPD	(%RCX,%RDX,8),%ZMM5,%ZMM5    [9]

0x42b9a6 VADDPD	(%R12,%RDX,8),%ZMM5,%ZMM5    [4]

0x42b9ad VADDPD	(%R14,%RDX,8),%ZMM5,%ZMM5    [6]

0x42b9b4 VMULPD	%ZMM5,%ZMM4,%ZMM4

0x42b9ba VMOVUPD	%ZMM4,(%R15,%RDX,8)    [7]

0x42b9c1 VMULPD	(%RBX,%RDX,8),%ZMM3,%ZMM4    [10]

0x42b9c8 VMOVUPD	(%RAX,%RDX,8),%ZMM5    [8]

0x42b9cf VADDPD	-0x8(%RAX,%RDX,8),%ZMM5,%ZMM5    [8]

0x42b9da VADDPD	-0x8(%R9,%RDX,8),%ZMM5,%ZMM5    [1]

0x42b9e5 VADDPD	(%R9,%RDX,8),%ZMM5,%ZMM5    [1]

0x42b9ec VMULPD	%ZMM5,%ZMM4,%ZMM4

0x42b9f2 VMOVUPD	%ZMM4,(%RSI,%RDX,8)    [3]

0x42b9f9 ADD	$0x8,%RDX

0x42b9fd CMP	%R8,%RDX

0x42ba00 JB	42b990

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 56 - 60

--------------------------------------------------------------------------------

56:       DO j=x_min,x_max+1

57:         vol_flux_x(j,k)=0.25_8*dt*xarea(j,k)                  &

58:           *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1))

59:         vol_flux_y(j,k)=0.25_8*dt*yarea(j,k)                  &

60:           *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k))

Coverage (%)	Name	Source Location	Module
►99.98+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P0, P1, P5,
Function	flux_calc_kernel_module_mp_flux_calc_kernel_.DIR.OMP.PARALLEL.2
Source	flux_calc_kernel.f90:56-60
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	4.00
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	1.00
P5 cycles	5.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	3.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	16.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	16.00
Nb FLOP add-sub	48.00
Nb FLOP mul	32.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	153.60
Bytes prefetched	0.00
Bytes loaded	640.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P0, P1, P5,
Function	flux_calc_kernel_module_mp_flux_calc_kernel_.DIR.OMP.PARALLEL.2
Source	flux_calc_kernel.f90:56-60
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	4.00
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	1.00
P5 cycles	5.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	3.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	16.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	16.00
Nb FLOP add-sub	48.00
Nb FLOP mul	32.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	153.60
Bytes prefetched	0.00
Bytes loaded	640.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	flux_calc_kernel_module_mp_flux_calc_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	flux_calc_kernel.f90:56-60
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:56-60.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use axHost or xHost
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

10 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 80 FP arithmetical operations:

48: addition or subtraction
32: multiply

The binary loop is loading 640 bytes (80 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !DIR$ UNROLL_AND_JAM(N), UNROLL_AND_JAM=N, UNROLL(N) or UNROLL=N

General properties

nb instructions	17
nb uops	16
loop length	114
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	3
nb stack references	0
ADD-SUB / MUL ratio	1.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.00	0.00	3.33	3.33	1.00	5.00	1.00	1.00	1.00	1.00	0.00	3.33
cycles	5.00	5.00	3.33	3.33	1.00	5.00	1.00	1.00	1.00	1.00	0.00	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.00
Dispatch	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

66% of peak load performance is reached (128.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (25.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42b990

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMULPD (%R11,%RDX,8),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD (%R13,%RDX,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RCX,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R12,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R14,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM5,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD (%RBX,%RDX,8),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD (%RAX,%RDX,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD -0x8(%RAX,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD -0x8(%R9,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R9,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM5,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 42b990 <flux_calc_kernel_module_mp_flux_calc_kernel_.DIR.OMP.PARALLEL.2+0x5e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	flux_calc_kernel_module_mp_flux_calc_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	flux_calc_kernel.f90:56-60
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:56-60.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use axHost or xHost
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

10 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 80 FP arithmetical operations:

48: addition or subtraction
32: multiply

The binary loop is loading 640 bytes (80 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !DIR$ UNROLL_AND_JAM(N), UNROLL_AND_JAM=N, UNROLL(N) or UNROLL=N

General properties

nb instructions	17
nb uops	16
loop length	114
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	3
nb stack references	0
ADD-SUB / MUL ratio	1.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.00	0.00	3.33	3.33	1.00	5.00	1.00	1.00	1.00	1.00	0.00	3.33
cycles	5.00	5.00	3.33	3.33	1.00	5.00	1.00	1.00	1.00	1.00	0.00	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.00
Dispatch	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

66% of peak load performance is reached (128.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (25.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42b990

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMULPD (%R11,%RDX,8),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD (%R13,%RDX,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RCX,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R12,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R14,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM5,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD (%RBX,%RDX,8),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD (%RAX,%RDX,8),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD -0x8(%RAX,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD -0x8(%R9,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R9,%RDX,8),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM5,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 42b990 <flux_calc_kernel_module_mp_flux_calc_kernel_.DIR.OMP.PARALLEL.2+0x5e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code