OV - exec - Loop 172

	Loop Id: 172	Module: exec	Source: field_summary_kernel.f90:58-71	Coverage: 0.19%

0x42a4e0 KXNORW	%K0,%K0,%K1

0x42a4e4 VMOVDQA64	%ZMM19,%ZMM22

0x42a4ea VXORPD	%XMM21,%XMM21,%XMM21

  (170) 0x42a4f0 VPSUBQ	%ZMM10,%ZMM22,%ZMM23

  (170) 0x42a4f6 VMOVQ	%XMM22,%R10

  (170) 0x42a4fc SUB	%R14,%R10

  (170) 0x42a4ff VMOVUPD	(%R8,%R10,8),%ZMM22{%K1}{z}

  (170) 0x42a506 VMOVUPD	(%RSI,%R10,8),%ZMM24{%K1}{z}

  (170) 0x42a50d VMULPD	%ZMM24,%ZMM24,%ZMM24

  (170) 0x42a513 VFMADD231PD	%ZMM22,%ZMM22,%ZMM24

  (170) 0x42a519 VFMADD231PD	%ZMM11,%ZMM24,%ZMM21

  (170) 0x42a51f VMOVAPD	%ZMM21,%ZMM20{%K1}

  (170) 0x42a525 VPCMPNEQQ	%ZMM18,%ZMM23,%K1{%K1}

  (170) 0x42a52c KORTESTB	%K1,%K1

  (170) 0x42a530 VMOVDQA64	%ZMM23,%ZMM22

  (170) 0x42a536 JNE	42a4f0

0x42a538 KXNORW	%K0,%K0,%K1

0x42a53c VMOVDQA64	%ZMM19,%ZMM22

0x42a542 NOPW	%CS:(%RAX,%RAX,1)

  (171) 0x42a550 VPSUBQ	%ZMM10,%ZMM22,%ZMM23

  (171) 0x42a556 VMOVQ	%XMM22,%R10

  (171) 0x42a55c SUB	%R14,%R10

  (171) 0x42a55f VMOVUPD	(%RBX,%R10,8),%ZMM22{%K1}{z}

  (171) 0x42a566 VMOVUPD	(%RAX,%R10,8),%ZMM24{%K1}{z}

  (171) 0x42a56d VMULPD	%ZMM24,%ZMM24,%ZMM24

  (171) 0x42a573 VFMADD231PD	%ZMM22,%ZMM22,%ZMM24

  (171) 0x42a579 VFMADD231PD	%ZMM11,%ZMM24,%ZMM20

  (171) 0x42a57f VMOVAPD	%ZMM20,%ZMM21{%K1}

  (171) 0x42a585 VPCMPNEQQ	%ZMM18,%ZMM23,%K1{%K1}

  (171) 0x42a58c KORTESTB	%K1,%K1

  (171) 0x42a590 VMOVDQA64	%ZMM23,%ZMM22

  (171) 0x42a596 JNE	42a550

0x42a598 LEA	(%RCX,%RDI,1),%R10

0x42a59c SUB	%R14,%R10

0x42a59f VMOVUPD	(%R12,%R10,8),%ZMM20

0x42a5a6 VMULPD	(%RDX,%R10,8),%ZMM20,%ZMM22

0x42a5ad VADDPD	%ZMM20,%ZMM13,%ZMM13

0x42a5b3 VADDPD	%ZMM22,%ZMM14,%ZMM14

0x42a5b9 VFMADD231PD	(%R15,%R10,8),%ZMM22,%ZMM15

0x42a5c0 VMULPD	%ZMM12,%ZMM22,%ZMM22

0x42a5c6 VFMADD231PD	%ZMM21,%ZMM22,%ZMM16

0x42a5cc VFMADD231PD	(%R13,%R10,8),%ZMM20,%ZMM17

0x42a5d4 ADD	$0x8,%RCX

0x42a5d8 VPADDQ	%ZMM9,%ZMM19,%ZMM19

0x42a5de VPADDQ	%ZMM9,%ZMM18,%ZMM18

0x42a5e4 CMP	-0x90(%RBP),%RCX

0x42a5eb JB	42a4e0

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 58 - 71

--------------------------------------------------------------------------------

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.22
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P0, P5,
Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source	field_summary_kernel.f90:58-58,field_summary_kernel.f90:62-62,field_summary_kernel.f90:65-71
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	5.50
Front-end cycles	3.83
P0 cycles	5.50
P1 cycles	3.50
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	0.00
P5 cycles	5.50
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.40
P11 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	20.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	14.55
Nb FLOP add-sub	16.00
Nb FLOP mul	16.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	264.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	94.23
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	75.00

Metric	Value
CQA speedup if no scalar integer	1.22
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P0, P5,
Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source	field_summary_kernel.f90:58-58,field_summary_kernel.f90:62-62,field_summary_kernel.f90:65-71
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	5.50
Front-end cycles	3.83
P0 cycles	5.50
P1 cycles	3.50
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	0.00
P5 cycles	5.50
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.40
P11 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	20.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	14.55
Nb FLOP add-sub	16.00
Nb FLOP mul	16.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	264.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	94.23
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	75.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	field_summary_kernel.f90:58-71
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:58-71.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:58,62,65-71.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 4.50 cycles (1.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is vectorized, but using 94% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.50 to 3.83 cycles (1.43x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 80 FP arithmetical operations:

40: addition or subtraction (24 inside FMA instructions)
40: multiply (24 inside FMA instructions)

The binary loop is loading 264 bytes (33 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	21
nb uops	20
loop length	129
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	12
nb stack references	1
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.83 cycles
front end	3.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	0.60	1.67	1.67	0.00	5.50	1.00	0.00	0.00	0.00	0.40	1.67
cycles	5.50	3.50	1.67	1.67	0.00	5.50	1.00	0.00	0.00	0.00	0.40	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	3.83
Dispatch	5.50
Data deps.	4.00
Overall L1	5.50

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	91%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	94%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

25% of peak load performance is reached (48.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a4e0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VMOVDQA64 %ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VMOVDQA64 %ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RCX,%RDI,1),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMOVUPD (%R12,%R10,8),%ZMM20	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD (%RDX,%R10,8),%ZMM20,%ZMM22	1	0.50	0	0.33	0.33	0.50	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM20,%ZMM13,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM22,%ZMM14,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD (%R15,%R10,8),%ZMM22,%ZMM15	1	0.50	0	0.33	0.33	0.50	0	0	0.33	4	0.50	vect (100.0%)
VMULPD %ZMM12,%ZMM22,%ZMM22	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM22,%ZMM16	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD (%R13,%R10,8),%ZMM20,%ZMM17	1	0.50	0	0.33	0.33	0.50	0	0	0.33	4	0.50	vect (100.0%)
ADD $0x8,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VPADDQ %ZMM9,%ZMM19,%ZMM19	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM9,%ZMM18,%ZMM18	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
CMP -0x90(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JB 42a4e0 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x4b0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	field_summary_kernel.f90:58-71
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 4.50 cycles (1.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is vectorized, but using 94% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 80 FP arithmetical operations:

40: addition or subtraction (24 inside FMA instructions)
40: multiply (24 inside FMA instructions)

The binary loop is loading 264 bytes (33 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	21
nb uops	20
loop length	129
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	12
nb stack references	1
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.83 cycles
front end	3.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	0.60	1.67	1.67	0.00	5.50	1.00	0.00	0.00	0.00	0.40	1.67
cycles	5.50	3.50	1.67	1.67	0.00	5.50	1.00	0.00	0.00	0.00	0.40	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	3.83
Dispatch	5.50
Data deps.	4.00
Overall L1	5.50

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	91%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	94%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

25% of peak load performance is reached (48.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a4e0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VMOVDQA64 %ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VMOVDQA64 %ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RCX,%RDI,1),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMOVUPD (%R12,%R10,8),%ZMM20	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD (%RDX,%R10,8),%ZMM20,%ZMM22	1	0.50	0	0.33	0.33	0.50	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM20,%ZMM13,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM22,%ZMM14,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD (%R15,%R10,8),%ZMM22,%ZMM15	1	0.50	0	0.33	0.33	0.50	0	0	0.33	4	0.50	vect (100.0%)
VMULPD %ZMM12,%ZMM22,%ZMM22	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM22,%ZMM16	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD (%R13,%R10,8),%ZMM20,%ZMM17	1	0.50	0	0.33	0.33	0.50	0	0	0.33	4	0.50	vect (100.0%)
ADD $0x8,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VPADDQ %ZMM9,%ZMM19,%ZMM19	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM9,%ZMM18,%ZMM18	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
CMP -0x90(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JB 42a4e0 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x4b0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code