OV - exec - Loop 118

	Loop Id: 118	Module: exec	Source: advec_mom_kernel.f90:81-241 [...]	Coverage: 4.48%

0x4218c0 VCMPPD	$0x1,%ZMM31,%ZMM16,%K2

0x4218c7 VCMPPD	$0x1,%ZMM30,%ZMM16,%K3

0x4218ce VPBLENDMD	%ZMM22,%ZMM21,%ZMM5{%K1}

0x4218d4 MOV	0x90(%RSP),%RAX    [8]

0x4218dc VMOVSD	(%RAX,%R10,8),%XMM8    [2]

0x4218e2 VANDPD	%ZMM11,%ZMM4,%ZMM4

0x4218e8 VANDPD	%ZMM11,%ZMM14,%ZMM13

0x4218ee VANDPD	%ZMM11,%ZMM9,%ZMM14

0x4218f4 VANDPD	%ZMM11,%ZMM7,%ZMM18

0x4218fa VBROADCASTSD	0xd6acc(%RIP),%ZMM0    [10]

0x421904 VSUBPD	%ZMM28,%ZMM0,%ZMM19

0x42190a VSUBPD	%ZMM29,%ZMM0,%ZMM10

0x421910 VMULPD	%ZMM10,%ZMM18,%ZMM10

0x421916 VMULPD	%ZMM19,%ZMM14,%ZMM19

0x42191c VMOVSD	0xd4a34(%RIP),%XMM0    [10]

0x421924 VDIVSD	%XMM8,%XMM0,%XMM0

0x421929 VBROADCASTSD	%XMM0,%ZMM0

0x42192f VMINPD	%ZMM14,%ZMM13,%ZMM17

0x421935 VFMADD213PD	%ZMM13,%ZMM28,%ZMM13

0x42193b VMINPD	%ZMM18,%ZMM4,%ZMM14

0x421941 VFMADD213PD	%ZMM4,%ZMM29,%ZMM4

0x421947 VEXTRACTI64X4	$0x1,%ZMM5,%YMM18

0x42194e VPMOVSXDQ	%YMM5,%ZMM5

0x421954 VPMOVSXDQ	%YMM18,%ZMM18

0x42195a VPSUBQ	%ZMM1,%ZMM18,%ZMM18

0x421960 VPSUBQ	%ZMM1,%ZMM5,%ZMM5

0x421966 VXORPD	%XMM6,%XMM6,%XMM6

0x42196a VGATHERQPD	(%RAX,%ZMM5,8),%ZMM6{%K3}    [2]

0x421971 VXORPD	%XMM5,%XMM5,%XMM5

0x421975 VGATHERQPD	(%RAX,%ZMM18,8),%ZMM5{%K2}    [2]

0x42197c VDIVPD	%ZMM6,%ZMM13,%ZMM6

0x421982 VDIVPD	%ZMM5,%ZMM4,%ZMM4

0x421988 VFMADD231PD	%ZMM19,%ZMM0,%ZMM6

0x42198e VFMADD231PD	%ZMM10,%ZMM0,%ZMM4

0x421994 VMULSD	0xd6a44(%RIP),%XMM8,%XMM0    [10]

0x42199c VBROADCASTSD	%XMM0,%ZMM0

0x4219a2 VMULPD	%ZMM4,%ZMM0,%ZMM4

0x4219a8 VMULPD	%ZMM6,%ZMM0,%ZMM0

0x4219ae VMINPD	%ZMM14,%ZMM4,%ZMM14

0x4219b4 VMINPD	%ZMM17,%ZMM0,%ZMM13

0x4219ba VFPCLASSPD	$0x56,%ZMM9,%K1

0x4219c1 VFPCLASSPD	$0x56,%ZMM7,%K2

0x4219c8 VBROADCASTSD	0xd6a06(%RIP),%ZMM0    [10]

0x4219d2 VXORPD	%ZMM0,%ZMM14,%ZMM14{%K2}

0x4219d8 VXORPD	%ZMM0,%ZMM13,%ZMM13{%K1}

0x4219de VCMPPD	$0x1,%ZMM30,%ZMM16,%K1

0x4219e5 VCMPPD	$0x1,%ZMM31,%ZMM16,%K2

0x4219ec VMOVAPD	%ZMM14,%ZMM0{%K2}{z}

0x4219f2 VMOVAPD	%ZMM13,%ZMM4{%K1}{z}

0x4219f8 VBROADCASTSD	0xd4956(%RIP),%ZMM6    [10]

0x421a02 VSUBPD	%ZMM29,%ZMM6,%ZMM5

0x421a08 VSUBPD	%ZMM28,%ZMM6,%ZMM6

0x421a0e VFMADD213PD	%ZMM26,%ZMM4,%ZMM6

0x421a14 VFMADD213PD	%ZMM27,%ZMM0,%ZMM5

0x421a1a VMULPD	%ZMM25,%ZMM5,%ZMM0

0x421a20 VMULPD	%ZMM24,%ZMM6,%ZMM4

0x421a26 VMOVUPD	%ZMM4,(%R9,%RSI,8)    [1]

0x421a2d VMOVUPD	%ZMM0,0x40(%R9,%RSI,8)    [1]

0x421a35 ADD	$0x10,%RSI

0x421a39 CMP	%RCX,%RSI

0x421a3c JA	421cc0

0x421a42 LEA	(%RBX,%RSI,1),%RAX

0x421a46 VMOVUPD	(%RDI,%RSI,8),%ZMM24    [9]

0x421a4d VMOVUPD	0x40(%RDI,%RSI,8),%ZMM25    [9]

0x421a55 VFPCLASSPD	$0x50,%ZMM24,%K0

0x421a5c VFPCLASSPD	$0x50,%ZMM25,%K1

0x421a63 KUNPCKBW	%K0,%K1,%K1

0x421a67 VPBLENDMD	%ZMM22,%ZMM23,%ZMM4{%K1}

0x421a6d VEXTRACTI64X4	$0x1,%ZMM4,%YMM7

0x421a74 VPMOVSXDQ	%YMM7,%ZMM7

0x421a7a VPSUBQ	%ZMM1,%ZMM7,%ZMM9

0x421a80 VPXOR	%XMM7,%XMM7,%XMM7

0x421a84 VPMULLQ	%ZMM9,%ZMM2,%ZMM7

0x421a8a VPMOVSXDQ	%YMM4,%ZMM4

0x421a90 VPSUBQ	%ZMM1,%ZMM4,%ZMM4

0x421a96 VPXOR	%XMM13,%XMM13,%XMM13

0x421a9b VPMULLQ	%ZMM4,%ZMM2,%ZMM13

0x421aa1 VPBROADCASTQ	%RAX,%ZMM14

0x421aa7 VPSUBQ	0x280(%RSP),%ZMM14,%ZMM14    [8]

0x421aaf VPSLLQ	$0x3,%ZMM14,%ZMM14

0x421ab6 VPADDQ	0xd7300(%RIP),%ZMM14,%ZMM26    [10]

0x421ac0 VPADDQ	%ZMM26,%ZMM12,%ZMM27

0x421ac6 VPADDQ	%ZMM13,%ZMM27,%ZMM13

0x421acc VXORPD	%XMM28,%XMM28,%XMM28

0x421ad2 KXNORW	%K0,%K0,%K2

0x421ad6 VGATHERQPD	(,%ZMM13,1),%ZMM28{%K2}    [3]

0x421ae1 VPADDQ	0xd7295(%RIP),%ZMM14,%ZMM13    [10]

0x421aeb VPADDQ	%ZMM13,%ZMM12,%ZMM14

0x421af1 VPADDQ	%ZMM7,%ZMM14,%ZMM14

0x421af7 VPXOR	%XMM7,%XMM7,%XMM7

0x421afb KXNORW	%K0,%K0,%K2

0x421aff VGATHERQPD	(,%ZMM14,1),%ZMM7{%K2}    [4]

0x421b0a VPMULLQ	%ZMM4,%ZMM3,%ZMM4

0x421b10 VPADDQ	%ZMM26,%ZMM15,%ZMM14

0x421b16 VPADDQ	%ZMM4,%ZMM14,%ZMM4

0x421b1c VPXORD	%XMM26,%XMM26,%XMM26

0x421b22 KXNORW	%K0,%K0,%K2

0x421b26 VGATHERQPD	(,%ZMM4,1),%ZMM26{%K2}    [13]

0x421b31 VPXOR	%XMM4,%XMM4,%XMM4

0x421b35 VPMULLQ	%ZMM9,%ZMM3,%ZMM4

0x421b3b VPADDQ	%ZMM13,%ZMM15,%ZMM9

0x421b41 VPADDQ	%ZMM4,%ZMM9,%ZMM4

0x421b47 VPXORD	%XMM27,%XMM27,%XMM27

0x421b4d KXNORW	%K0,%K0,%K2

0x421b51 VGATHERQPD	(,%ZMM4,1),%ZMM27{%K2}    [12]

0x421b5c VPBLENDMD	%ZMM20,%ZMM21,%ZMM4{%K1}

0x421b62 VEXTRACTI64X4	$0x1,%ZMM4,%YMM13

0x421b69 VPMOVSXDQ	%YMM13,%ZMM13

0x421b6f VPMOVSXDQ	%YMM4,%ZMM4

0x421b75 VPSUBQ	%ZMM1,%ZMM4,%ZMM4

0x421b7b VPMULLQ	%ZMM4,%ZMM3,%ZMM4

0x421b81 VPADDQ	%ZMM4,%ZMM14,%ZMM4

0x421b87 VXORPD	%XMM30,%XMM30,%XMM30

0x421b8d KXNORW	%K0,%K0,%K2

0x421b91 VGATHERQPD	(,%ZMM4,1),%ZMM30{%K2}    [11]

0x421b9c VPSUBQ	%ZMM1,%ZMM13,%ZMM4

0x421ba2 VPMULLQ	%ZMM4,%ZMM3,%ZMM4

0x421ba8 VPADDQ	%ZMM4,%ZMM9,%ZMM4

0x421bae VXORPD	%XMM31,%XMM31,%XMM31

0x421bb4 KXNORW	%K0,%K0,%K2

0x421bb8 VGATHERQPD	(,%ZMM4,1),%ZMM31{%K2}    [7]

0x421bc3 VPBLENDMD	%ZMM23,%ZMM22,%ZMM4{%K1}

0x421bc9 VANDPD	%ZMM11,%ZMM24,%ZMM29

0x421bcf VANDPD	%ZMM11,%ZMM25,%ZMM5

0x421bd5 VPXOR	%XMM13,%XMM13,%XMM13

0x421bda VDIVPD	%ZMM28,%ZMM29,%ZMM28

0x421be0 VEXTRACTI64X4	$0x1,%ZMM4,%YMM29

0x421be7 VPMOVSXDQ	%YMM29,%ZMM29

0x421bed VPMOVSXDQ	%YMM4,%ZMM4

0x421bf3 VPSUBQ	%ZMM1,%ZMM4,%ZMM4

0x421bf9 VPMULLQ	%ZMM4,%ZMM3,%ZMM4

0x421bff VPADDQ	%ZMM4,%ZMM14,%ZMM4

0x421c05 VXORPD	%XMM8,%XMM8,%XMM8

0x421c0a KXNORW	%K0,%K0,%K2

0x421c0e VGATHERQPD	(,%ZMM4,1),%ZMM8{%K2}    [6]

0x421c19 VPSUBQ	%ZMM1,%ZMM29,%ZMM4

0x421c1f VPMULLQ	%ZMM4,%ZMM3,%ZMM4

0x421c25 VPADDQ	%ZMM4,%ZMM9,%ZMM4

0x421c2b VPXOR	%XMM9,%XMM9,%XMM9

0x421c30 KXNORW	%K0,%K0,%K2

0x421c34 VGATHERQPD	(,%ZMM4,1),%ZMM9{%K2}    [5]

0x421c3f VDIVPD	%ZMM7,%ZMM5,%ZMM29

0x421c45 VSUBPD	%ZMM31,%ZMM27,%ZMM4

0x421c4b VSUBPD	%ZMM30,%ZMM26,%ZMM14

0x421c51 VSUBPD	%ZMM27,%ZMM9,%ZMM7

0x421c57 VSUBPD	%ZMM26,%ZMM8,%ZMM9

0x421c5d VMULPD	%ZMM14,%ZMM9,%ZMM30

0x421c63 VMULPD	%ZMM4,%ZMM7,%ZMM31

0x421c69 VCMPPD	$0x1,%ZMM31,%ZMM13,%K0

0x421c70 VCMPPD	$0x1,%ZMM30,%ZMM13,%K2

0x421c77 KORTESTB	%K0,%K2

0x421c7b JNE	4218c0

0x421c81 VXORPD	%XMM14,%XMM14,%XMM14

0x421c86 JMP	4219de

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 241

--------------------------------------------------------------------------------

81:     IF(mom_sweep.EQ.1)THEN ! x 1

[...]

215:           IF(node_flux(j,k).LT.0.0)THEN

[...]

227:           sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor))

228:           width=celldy(k)

229:           vdiffuw=vel1(j,donor)-vel1(j,upwind)

230:           vdiffdw=vel1(j,downwind)-vel1(j,donor)

231:           limiter=0.0

232:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

233:             auw=ABS(vdiffuw)

234:             adw=ABS(vdiffdw)

235:             wind=1.0_8

236:             IF(vdiffdw.LE.0.0) wind=-1.0_8

237:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw)

238:           ENDIF

239:           advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter

240:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

241:         ENDDO

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks
Function	advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2
Source	advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	70.75
CQA cycles if no scalar integer	65.75
CQA cycles if FP arith vectorized	70.56
CQA cycles if fully vectorized	68.94
Front-end cycles	34.08
P0 cycles	70.75
P1 cycles	8.75
P2 cycles	27.00
P3 cycles	27.00
P4 cycles	1.00
P5 cycles	70.75
P6 cycles	2.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	27.00
DIV/SQRT cycles	50.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	130.50
Nb uops	204.50
Nb loads	18.00
Nb stores	2.00
Nb stack references	1.50
FLOP/cycle	2.73
Nb FLOP add-sub	56.00
Nb FLOP mul	48.50
Nb FLOP fma	32.00
Nb FLOP div	24.50
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.11
Bytes prefetched	0.00
Bytes loaded	928.00
Bytes stored	128.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	8.50
Stride indirect	0.00
Vectorization ratio all	95.25
Vectorization ratio load	82.14
Vectorization ratio store	100.00
Vectorization ratio mul	97.06
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	90.00
Vectorization ratio other	93.60
Vector-efficiency ratio all	82.11
Vector-efficiency ratio load	84.38
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	97.43
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	91.25
Vector-efficiency ratio other	67.29

Metric	Value
CQA speedup if no scalar integer	1.09
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P0, P5,
Function	advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2
Source	advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	59.50
CQA cycles if no scalar integer	54.50
CQA cycles if FP arith vectorized	59.50
CQA cycles if fully vectorized	58.50
Front-end cycles	29.50
P0 cycles	59.50
P1 cycles	6.00
P2 cycles	23.33
P3 cycles	23.33
P4 cycles	1.00
P5 cycles	59.50
P6 cycles	2.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	23.33
DIV/SQRT cycles	32.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	109.00
Nb uops	177.00
Nb loads	14.00
Nb stores	2.00
Nb stack references	1.00
FLOP/cycle	2.15
Nb FLOP add-sub	48.00
Nb FLOP mul	32.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.27
Bytes prefetched	0.00
Bytes loaded	840.00
Bytes stored	128.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	97.85
Vectorization ratio load	92.86
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	95.65
Vector-efficiency ratio all	82.80
Vector-efficiency ratio load	93.75
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	65.22

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P0, P5,
Function	advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2
Source	advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	82.00
CQA cycles if no scalar integer	77.00
CQA cycles if FP arith vectorized	81.63
CQA cycles if fully vectorized	79.38
Front-end cycles	38.67
P0 cycles	82.00
P1 cycles	11.50
P2 cycles	30.67
P3 cycles	30.67
P4 cycles	1.00
P5 cycles	82.00
P6 cycles	2.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	30.67
DIV/SQRT cycles	68.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	152.00
Nb uops	232.00
Nb loads	22.00
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	3.15
Nb FLOP add-sub	64.00
Nb FLOP mul	65.00
Nb FLOP fma	48.00
Nb FLOP div	33.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.95
Bytes prefetched	0.00
Bytes loaded	1016.00
Bytes stored	128.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	9.00
Stride indirect	0.00
Vectorization ratio all	92.65
Vectorization ratio load	71.43
Vectorization ratio store	100.00
Vectorization ratio mul	94.12
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	80.00
Vectorization ratio other	91.55
Vector-efficiency ratio all	81.43
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	94.85
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	82.50
Vector-efficiency ratio other	69.37

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	advec_mom_kernel.f90:81-241
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:81,215,227-241.

It is main loop of related source loop which is unrolled by 16 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 82% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 70.75 to 68.94 cycles (1.03x speedup).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

82% of SSE/AVX loads are used in vector version.
97% of SSE/AVX multiply instructions are used in vector version.
90% of SSE/AVX divide and square root instructions are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use axHost or xHost
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
2. inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.
Use the LOOP COUNT directive

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 70.75 to 66.00 cycles (1.07x speedup).

Special instructions executing on a single port

1.39x slowdown from special instructions executing on a single port.

Details

KORTESTB: 0 occurrences
KUNPCKBW: 0 occurrences
KXNORW: 0 occurrences
VCMPPD: 0 occurrences
VEXTRACTI64X4: 0 occurrences
VFPCLASSPD: 0 occurrences
VGATHERQPD: 0 occurrences
VPBROADCASTQ: 0 occurrences
VPMOVSXDQ: 0 occurrences
VPSLLQ: 0 occurrences

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 0 occurrences
VGATHERQPD: 0 occurrences
VPMULLQ: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 0 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 30 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 193 FP arithmetical operations:

88: addition or subtraction (32 inside FMA instructions)
80.50: multiply (32 inside FMA instructions)
24.50: divide

The binary loop is loading 928 bytes (116 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	130.50
nb uops	204.50
loop length	823
used x86 registers	7.50
used mmx registers	0
used xmm registers	12
used ymm registers	5
used zmm registers	30
nb stack references	1.50
ADD-SUB / MUL ratio	1.19

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	34.08 cycles
front end	34.08 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	70.75	2.50	27.00	27.00	1.00	70.75	2.00	1.00	1.00	1.00	1.00	27.00
cycles	70.75	8.75	27.00	27.00	1.00	70.75	2.00	1.00	1.00	1.00	1.00	27.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	50.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	34.08
Dispatch	70.75
DIV/SQRT	50.00
Data deps.	0.00
Overall L1	70.75

Vectorization ratios

INT

all	98%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	95%

all	93%
load	78%
store	100%
mul	94%
add-sub	100%
fma	100%
div/sqrt	90%
other	92%

INT+FP

all	95%
load	82%
store	100%
mul	97%
add-sub	100%
fma	100%
div/sqrt	90%
other	93%

Vector efficiency ratios

INT

all	77%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	49%

all	86%
load	81%
store	100%
mul	95%
add-sub	100%
fma	100%
div/sqrt	91%
other	80%

INT+FP

all	82%
load	84%
store	100%
mul	97%
add-sub	100%
fma	100%
div/sqrt	91%
other	67%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 70.75 cycles. At this rate:

6% of peak load performance is reached (13.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	advec_mom_kernel.f90:81-241
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 59.50 to 54.50 cycles (1.09x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

92% of SSE/AVX loads are used in vector version.
95% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use axHost or xHost
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
2. inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.
Use the LOOP COUNT directive

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 59.50 to 56.50 cycles (1.05x speedup).

Special instructions executing on a single port

1.75x slowdown from special instructions executing on a single port.

Details

KORTESTB: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:81
KUNPCKBW: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
KXNORW: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VCMPPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
VEXTRACTI64X4: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VFPCLASSPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VPBROADCASTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
VPMOVSXDQ: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VPSLLQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VPMULLQ: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

20 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (16 inside FMA instructions)
48: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 840 bytes (105 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	109
nb uops	177
loop length	685
used x86 registers	7
used mmx registers	0
used xmm registers	11
used ymm registers	4
used zmm registers	28
nb stack references	1
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.50 cycles
front end	29.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	59.50	2.00	23.33	23.33	1.00	59.50	2.00	1.00	1.00	1.00	1.00	23.33
cycles	59.50	6.00	23.33	23.33	1.00	59.50	2.00	1.00	1.00	1.00	1.00	23.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	32.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	29.50
Dispatch	59.50
DIV/SQRT	32.00
Data deps.	0.00
Overall L1	59.50

Vectorization ratios

INT

all	98%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	95%

all	97%
load	90%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

INT+FP

all	97%
load	92%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

Vector efficiency ratios

INT

all	77%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	48%

all	88%
load	92%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	80%

INT+FP

all	82%
load	93%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	65%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 59.50 cycles. At this rate:

7% of peak load performance is reached (14.12 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.15 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421a42

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCMPPD $0x1,%ZMM30,%ZMM16,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x1,%ZMM31,%ZMM16,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVAPD %ZMM14,%ZMM0{%K2}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM13,%ZMM4{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VBROADCASTSD 0xd4956(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %ZMM29,%ZMM6,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM28,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD %ZMM26,%ZMM4,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM27,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM25,%ZMM5,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM6,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%R9,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,0x40(%R9,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x10,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JA 421cc0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2e60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RBX,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD (%RDI,%RSI,8),%ZMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RSI,8),%ZMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFPCLASSPD $0x50,%ZMM24,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VFPCLASSPD $0x50,%ZMM25,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
VPBLENDMD %ZMM22,%ZMM23,%ZMM4{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM4,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM7,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM1,%ZMM7,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPXOR %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPMULLQ %ZMM9,%ZMM2,%ZMM7	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMOVSXDQ %YMM4,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM1,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPXOR %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPMULLQ %ZMM4,%ZMM2,%ZMM13	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPBROADCASTQ %RAX,%ZMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ 0x280(%RSP),%ZMM14,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	0-1	0.67	vect (100.0%)
VPSLLQ $0x3,%ZMM14,%ZMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ 0xd7300(%RIP),%ZMM14,%ZMM26	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VPADDQ %ZMM26,%ZMM12,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM13,%ZMM27,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM28{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ 0xd7295(%RIP),%ZMM14,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VPADDQ %ZMM13,%ZMM12,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM14,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXOR %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM14,1),%ZMM7{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM26,%ZMM15,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM14,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXORD %XMM26,%XMM26,%XMM26	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM26{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPMULLQ %ZMM9,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM13,%ZMM15,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXORD %XMM27,%XMM27,%XMM27	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM27{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %ZMM20,%ZMM21,%ZMM4{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM4,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM13,%ZMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM4,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM1,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM14,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM30{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSUBQ %ZMM1,%ZMM13,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM31,%XMM31,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM31{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %ZMM23,%ZMM22,%ZMM4{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM11,%ZMM24,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM11,%ZMM25,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXOR %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VDIVPD %ZMM28,%ZMM29,%ZMM28	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM4,%YMM29	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM29,%ZMM29	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM4,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM1,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM14,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM8{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSUBQ %ZMM1,%ZMM29,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXOR %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM9{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM7,%ZMM5,%ZMM29	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM31,%ZMM27,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM30,%ZMM26,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM27,%ZMM9,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM26,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM9,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM7,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM31,%ZMM13,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x1,%ZMM30,%ZMM13,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KORTESTB %K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JNE 4218c0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2a60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4219de <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2b7e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	advec_mom_kernel.f90:81-241
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 82.00 to 77.00 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is highly vectorized. 81% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 82.00 to 79.37 cycles (1.03x speedup).

Details

92% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

71% of SSE/AVX loads are used in vector version.
94% of SSE/AVX multiply instructions are used in vector version.
80% of SSE/AVX divide and square root instructions are used in vector version.
91% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use axHost or xHost
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: compile with -align array64byte (remark: not affects arrays in COMMON blocks).
2. inform your compiler that your arrays are vector aligned: Append !DIR$ VECTOR ALIGNED to the loop if all accessed arrays are aligned, or !DIR$ ASSUME_ALIGNED FOO: 64 if only FOO is aligned.
Use the LOOP COUNT directive

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 82.00 to 75.50 cycles (1.09x speedup).

Special instructions executing on a single port

1.21x slowdown from special instructions executing on a single port.

Details

KORTESTB: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:81
KUNPCKBW: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
KXNORW: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VBROADCASTSD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
VCMPPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
VEXTRACTI64X4: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VFPCLASSPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
VGATHERQPD: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VPBROADCASTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
VPMOVSXDQ: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VPSLLQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 48 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
VGATHERQPD: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VPMULLQ: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 40 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 258 FP arithmetical operations:

112: addition or subtraction (48 inside FMA instructions)
113: multiply (48 inside FMA instructions)
33: divide

The binary loop is loading 1016 bytes (127 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	152
nb uops	232
loop length	961
used x86 registers	8
used mmx registers	0
used xmm registers	13
used ymm registers	6
used zmm registers	32
nb stack references	2
ADD-SUB / MUL ratio	0.89

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.67 cycles
front end	38.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	82.00	3.00	30.67	30.67	1.00	82.00	2.00	1.00	1.00	1.00	1.00	30.67
cycles	82.00	11.50	30.67	30.67	1.00	82.00	2.00	1.00	1.00	1.00	1.00	30.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	68.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	38.67
Dispatch	82.00
DIV/SQRT	68.00
Data deps.	0.00
Overall L1	82.00

Vectorization ratios

INT

all	98%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	96%

all	88%
load	66%
store	100%
mul	88%
add-sub	100%
fma	100%
div/sqrt	80%
other	88%

INT+FP

all	92%
load	71%
store	100%
mul	94%
add-sub	100%
fma	100%
div/sqrt	80%
other	91%

Vector efficiency ratios

INT

all	77%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	84%
load	70%
store	100%
mul	90%
add-sub	100%
fma	100%
div/sqrt	82%
other	80%

INT+FP

all	81%
load	75%
store	100%
mul	94%
add-sub	100%
fma	100%
div/sqrt	82%
other	69%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 82.00 cycles. At this rate:

6% of peak load performance is reached (12.39 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.56 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421a42

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCMPPD $0x1,%ZMM31,%ZMM16,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x1,%ZMM30,%ZMM16,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPBLENDMD %ZMM22,%ZMM21,%ZMM5{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
MOV 0x90(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RAX,%R10,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VANDPD %ZMM11,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM11,%ZMM14,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM11,%ZMM9,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM11,%ZMM7,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VBROADCASTSD 0xd6acc(%RIP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %ZMM28,%ZMM0,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM29,%ZMM0,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM10,%ZMM18,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM14,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVSD 0xd4a34(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD %XMM8,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VBROADCASTSD %XMM0,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMINPD %ZMM14,%ZMM13,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM13,%ZMM28,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM18,%ZMM4,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM4,%ZMM29,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM5,%YMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM5,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM18,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM1,%ZMM18,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM1,%ZMM5,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERQPD (%RAX,%ZMM5,8),%ZMM6{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERQPD (%RAX,%ZMM18,8),%ZMM5{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM6,%ZMM13,%ZMM6	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM5,%ZMM4,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM0,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM0,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULSD 0xd6a44(%RIP),%XMM8,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULPD %ZMM4,%ZMM0,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM14,%ZMM4,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM17,%ZMM0,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFPCLASSPD $0x56,%ZMM9,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VFPCLASSPD $0x56,%ZMM7,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VBROADCASTSD 0xd6a06(%RIP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VXORPD %ZMM0,%ZMM14,%ZMM14{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VXORPD %ZMM0,%ZMM13,%ZMM13{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM30,%ZMM16,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x1,%ZMM31,%ZMM16,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVAPD %ZMM14,%ZMM0{%K2}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVAPD %ZMM13,%ZMM4{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VBROADCASTSD 0xd4956(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %ZMM29,%ZMM6,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM28,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD %ZMM26,%ZMM4,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM27,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM25,%ZMM5,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM6,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%R9,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,0x40(%R9,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x10,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JA 421cc0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2e60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RBX,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD (%RDI,%RSI,8),%ZMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RSI,8),%ZMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFPCLASSPD $0x50,%ZMM24,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VFPCLASSPD $0x50,%ZMM25,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
VPBLENDMD %ZMM22,%ZMM23,%ZMM4{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM4,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM7,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM1,%ZMM7,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPXOR %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPMULLQ %ZMM9,%ZMM2,%ZMM7	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMOVSXDQ %YMM4,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM1,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPXOR %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPMULLQ %ZMM4,%ZMM2,%ZMM13	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPBROADCASTQ %RAX,%ZMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ 0x280(%RSP),%ZMM14,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	0-1	0.67	vect (100.0%)
VPSLLQ $0x3,%ZMM14,%ZMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ 0xd7300(%RIP),%ZMM14,%ZMM26	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VPADDQ %ZMM26,%ZMM12,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM13,%ZMM27,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM28{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ 0xd7295(%RIP),%ZMM14,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VPADDQ %ZMM13,%ZMM12,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM14,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXOR %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM14,1),%ZMM7{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM26,%ZMM15,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM14,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXORD %XMM26,%XMM26,%XMM26	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM26{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPMULLQ %ZMM9,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM13,%ZMM15,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXORD %XMM27,%XMM27,%XMM27	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM27{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %ZMM20,%ZMM21,%ZMM4{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM4,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM13,%ZMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM4,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM1,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM14,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM30{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSUBQ %ZMM1,%ZMM13,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM31,%XMM31,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM31{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPBLENDMD %ZMM23,%ZMM22,%ZMM4{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM11,%ZMM24,%ZMM29	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM11,%ZMM25,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXOR %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VDIVPD %ZMM28,%ZMM29,%ZMM28	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM4,%YMM29	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM29,%ZMM29	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM4,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPSUBQ %ZMM1,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM14,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM8{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSUBQ %ZMM1,%ZMM29,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPMULLQ %ZMM4,%ZMM3,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPXOR %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM9{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM7,%ZMM5,%ZMM29	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM31,%ZMM27,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM30,%ZMM26,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM27,%ZMM9,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM26,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM9,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM7,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM31,%ZMM13,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x1,%ZMM30,%ZMM13,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KORTESTB %K0,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JNE 4218c0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2a60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

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Expensive FP math instructions/calls

Special instructions executing on a single port

Details

Masked instructions

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Workaround

FMA

Workaround

Complex instructions

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Slow data structures access

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Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Special instructions executing on a single port

Details

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Special instructions executing on a single port

Details

Masked instructions

Details

Workaround

FMA

Workaround