| Loop Id: 116 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 0.01% |
|---|
| Loop Id: 116 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 0.01% |
|---|
0x421800 MOV 0x130(%RSP),%RCX |
0x421808 MOV 0x48(%RSP),%R9 |
0x42180d ADD %RCX,%R9 |
0x421810 MOV 0x170(%RSP),%RAX |
0x421818 MOV 0x88(%RSP),%RDI |
0x421820 ADD %RAX,%RDI |
0x421823 ADD %RCX,(%RSP) |
0x421827 ADD %RAX,0x18(%RSP) |
0x42182c MOV 0x20(%RSP),%RCX |
0x421831 CMP 0x10(%RSP),%RCX |
0x421836 LEA 0x1(%RCX),%RCX |
0x42183a MOV 0x38(%RSP),%RBX |
0x42183f JE 421700 |
0x421845 CMPQ $0,0x40(%RSP) |
0x42184b MOV %RDI,0x88(%RSP) |
0x421853 MOV %R9,0x48(%RSP) |
0x421858 MOV %RCX,0x20(%RSP) |
0x42185d JE 421d40 |
0x421863 MOV 0x58(%RSP),%RAX |
0x421868 LEA -0x1(%RAX,%RCX,1),%R8 |
0x42186d MOV %R8,%R10 |
0x421870 SUB %RDX,%R10 |
0x421873 MOV 0x108(%RSP),%RAX |
0x42187b LEA (%RAX,%RCX,1),%R14D |
0x42187f LEA 0x1(%RAX,%RCX,1),%ESI |
0x421883 MOV %ESI,0x60(%RSP) |
0x421887 VPBROADCASTD %ESI,%ZMM20 |
0x42188d LEA -0x2(%RAX,%RCX,1),%EAX |
0x421891 MOV %EAX,0x68(%RSP) |
0x421895 VPBROADCASTD %EAX,%ZMM21 |
0x42189b VPBROADCASTD %R14D,%ZMM22 |
0x4218a1 VPBROADCASTD %R8D,%ZMM23 |
0x4218a7 XOR %ESI,%ESI |
0x4218a9 MOV 0xb0(%RSP),%RCX |
0x4218b1 JMP 421a42 |
(118) 0x4218c0 VCMPPD $0x1,%ZMM31,%ZMM16,%K2 |
(118) 0x4218c7 VCMPPD $0x1,%ZMM30,%ZMM16,%K3 |
(118) 0x4218ce VPBLENDMD %ZMM22,%ZMM21,%ZMM5{%K1} |
(118) 0x4218d4 MOV 0x90(%RSP),%RAX |
(118) 0x4218dc VMOVSD (%RAX,%R10,8),%XMM8 |
(118) 0x4218e2 VANDPD %ZMM11,%ZMM4,%ZMM4 |
(118) 0x4218e8 VANDPD %ZMM11,%ZMM14,%ZMM13 |
(118) 0x4218ee VANDPD %ZMM11,%ZMM9,%ZMM14 |
(118) 0x4218f4 VANDPD %ZMM11,%ZMM7,%ZMM18 |
(118) 0x4218fa VBROADCASTSD 0xd6acc(%RIP),%ZMM0 |
(118) 0x421904 VSUBPD %ZMM28,%ZMM0,%ZMM19 |
(118) 0x42190a VSUBPD %ZMM29,%ZMM0,%ZMM10 |
(118) 0x421910 VMULPD %ZMM10,%ZMM18,%ZMM10 |
(118) 0x421916 VMULPD %ZMM19,%ZMM14,%ZMM19 |
(118) 0x42191c VMOVSD 0xd4a34(%RIP),%XMM0 |
(118) 0x421924 VDIVSD %XMM8,%XMM0,%XMM0 |
(118) 0x421929 VBROADCASTSD %XMM0,%ZMM0 |
(118) 0x42192f VMINPD %ZMM14,%ZMM13,%ZMM17 |
(118) 0x421935 VFMADD213PD %ZMM13,%ZMM28,%ZMM13 |
(118) 0x42193b VMINPD %ZMM18,%ZMM4,%ZMM14 |
(118) 0x421941 VFMADD213PD %ZMM4,%ZMM29,%ZMM4 |
(118) 0x421947 VEXTRACTI64X4 $0x1,%ZMM5,%YMM18 |
(118) 0x42194e VPMOVSXDQ %YMM5,%ZMM5 |
(118) 0x421954 VPMOVSXDQ %YMM18,%ZMM18 |
(118) 0x42195a VPSUBQ %ZMM1,%ZMM18,%ZMM18 |
(118) 0x421960 VPSUBQ %ZMM1,%ZMM5,%ZMM5 |
(118) 0x421966 VXORPD %XMM6,%XMM6,%XMM6 |
(118) 0x42196a VGATHERQPD (%RAX,%ZMM5,8),%ZMM6{%K3} |
(118) 0x421971 VXORPD %XMM5,%XMM5,%XMM5 |
(118) 0x421975 VGATHERQPD (%RAX,%ZMM18,8),%ZMM5{%K2} |
(118) 0x42197c VDIVPD %ZMM6,%ZMM13,%ZMM6 |
(118) 0x421982 VDIVPD %ZMM5,%ZMM4,%ZMM4 |
(118) 0x421988 VFMADD231PD %ZMM19,%ZMM0,%ZMM6 |
(118) 0x42198e VFMADD231PD %ZMM10,%ZMM0,%ZMM4 |
(118) 0x421994 VMULSD 0xd6a44(%RIP),%XMM8,%XMM0 |
(118) 0x42199c VBROADCASTSD %XMM0,%ZMM0 |
(118) 0x4219a2 VMULPD %ZMM4,%ZMM0,%ZMM4 |
(118) 0x4219a8 VMULPD %ZMM6,%ZMM0,%ZMM0 |
(118) 0x4219ae VMINPD %ZMM14,%ZMM4,%ZMM14 |
(118) 0x4219b4 VMINPD %ZMM17,%ZMM0,%ZMM13 |
(118) 0x4219ba VFPCLASSPD $0x56,%ZMM9,%K1 |
(118) 0x4219c1 VFPCLASSPD $0x56,%ZMM7,%K2 |
(118) 0x4219c8 VBROADCASTSD 0xd6a06(%RIP),%ZMM0 |
(118) 0x4219d2 VXORPD %ZMM0,%ZMM14,%ZMM14{%K2} |
(118) 0x4219d8 VXORPD %ZMM0,%ZMM13,%ZMM13{%K1} |
(118) 0x4219de VCMPPD $0x1,%ZMM30,%ZMM16,%K1 |
(118) 0x4219e5 VCMPPD $0x1,%ZMM31,%ZMM16,%K2 |
(118) 0x4219ec VMOVAPD %ZMM14,%ZMM0{%K2}{z} |
(118) 0x4219f2 VMOVAPD %ZMM13,%ZMM4{%K1}{z} |
(118) 0x4219f8 VBROADCASTSD 0xd4956(%RIP),%ZMM6 |
(118) 0x421a02 VSUBPD %ZMM29,%ZMM6,%ZMM5 |
(118) 0x421a08 VSUBPD %ZMM28,%ZMM6,%ZMM6 |
(118) 0x421a0e VFMADD213PD %ZMM26,%ZMM4,%ZMM6 |
(118) 0x421a14 VFMADD213PD %ZMM27,%ZMM0,%ZMM5 |
(118) 0x421a1a VMULPD %ZMM25,%ZMM5,%ZMM0 |
(118) 0x421a20 VMULPD %ZMM24,%ZMM6,%ZMM4 |
(118) 0x421a26 VMOVUPD %ZMM4,(%R9,%RSI,8) |
(118) 0x421a2d VMOVUPD %ZMM0,0x40(%R9,%RSI,8) |
(118) 0x421a35 ADD $0x10,%RSI |
(118) 0x421a39 CMP %RCX,%RSI |
(118) 0x421a3c JA 421cc0 |
(118) 0x421a42 LEA (%RBX,%RSI,1),%RAX |
(118) 0x421a46 VMOVUPD (%RDI,%RSI,8),%ZMM24 |
(118) 0x421a4d VMOVUPD 0x40(%RDI,%RSI,8),%ZMM25 |
(118) 0x421a55 VFPCLASSPD $0x50,%ZMM24,%K0 |
(118) 0x421a5c VFPCLASSPD $0x50,%ZMM25,%K1 |
(118) 0x421a63 KUNPCKBW %K0,%K1,%K1 |
(118) 0x421a67 VPBLENDMD %ZMM22,%ZMM23,%ZMM4{%K1} |
(118) 0x421a6d VEXTRACTI64X4 $0x1,%ZMM4,%YMM7 |
(118) 0x421a74 VPMOVSXDQ %YMM7,%ZMM7 |
(118) 0x421a7a VPSUBQ %ZMM1,%ZMM7,%ZMM9 |
(118) 0x421a80 VPXOR %XMM7,%XMM7,%XMM7 |
(118) 0x421a84 VPMULLQ %ZMM9,%ZMM2,%ZMM7 |
(118) 0x421a8a VPMOVSXDQ %YMM4,%ZMM4 |
(118) 0x421a90 VPSUBQ %ZMM1,%ZMM4,%ZMM4 |
(118) 0x421a96 VPXOR %XMM13,%XMM13,%XMM13 |
(118) 0x421a9b VPMULLQ %ZMM4,%ZMM2,%ZMM13 |
(118) 0x421aa1 VPBROADCASTQ %RAX,%ZMM14 |
(118) 0x421aa7 VPSUBQ 0x280(%RSP),%ZMM14,%ZMM14 |
(118) 0x421aaf VPSLLQ $0x3,%ZMM14,%ZMM14 |
(118) 0x421ab6 VPADDQ 0xd7300(%RIP),%ZMM14,%ZMM26 |
(118) 0x421ac0 VPADDQ %ZMM26,%ZMM12,%ZMM27 |
(118) 0x421ac6 VPADDQ %ZMM13,%ZMM27,%ZMM13 |
(118) 0x421acc VXORPD %XMM28,%XMM28,%XMM28 |
(118) 0x421ad2 KXNORW %K0,%K0,%K2 |
(118) 0x421ad6 VGATHERQPD (,%ZMM13,1),%ZMM28{%K2} |
(118) 0x421ae1 VPADDQ 0xd7295(%RIP),%ZMM14,%ZMM13 |
(118) 0x421aeb VPADDQ %ZMM13,%ZMM12,%ZMM14 |
(118) 0x421af1 VPADDQ %ZMM7,%ZMM14,%ZMM14 |
(118) 0x421af7 VPXOR %XMM7,%XMM7,%XMM7 |
(118) 0x421afb KXNORW %K0,%K0,%K2 |
(118) 0x421aff VGATHERQPD (,%ZMM14,1),%ZMM7{%K2} |
(118) 0x421b0a VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(118) 0x421b10 VPADDQ %ZMM26,%ZMM15,%ZMM14 |
(118) 0x421b16 VPADDQ %ZMM4,%ZMM14,%ZMM4 |
(118) 0x421b1c VPXORD %XMM26,%XMM26,%XMM26 |
(118) 0x421b22 KXNORW %K0,%K0,%K2 |
(118) 0x421b26 VGATHERQPD (,%ZMM4,1),%ZMM26{%K2} |
(118) 0x421b31 VPXOR %XMM4,%XMM4,%XMM4 |
(118) 0x421b35 VPMULLQ %ZMM9,%ZMM3,%ZMM4 |
(118) 0x421b3b VPADDQ %ZMM13,%ZMM15,%ZMM9 |
(118) 0x421b41 VPADDQ %ZMM4,%ZMM9,%ZMM4 |
(118) 0x421b47 VPXORD %XMM27,%XMM27,%XMM27 |
(118) 0x421b4d KXNORW %K0,%K0,%K2 |
(118) 0x421b51 VGATHERQPD (,%ZMM4,1),%ZMM27{%K2} |
(118) 0x421b5c VPBLENDMD %ZMM20,%ZMM21,%ZMM4{%K1} |
(118) 0x421b62 VEXTRACTI64X4 $0x1,%ZMM4,%YMM13 |
(118) 0x421b69 VPMOVSXDQ %YMM13,%ZMM13 |
(118) 0x421b6f VPMOVSXDQ %YMM4,%ZMM4 |
(118) 0x421b75 VPSUBQ %ZMM1,%ZMM4,%ZMM4 |
(118) 0x421b7b VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(118) 0x421b81 VPADDQ %ZMM4,%ZMM14,%ZMM4 |
(118) 0x421b87 VXORPD %XMM30,%XMM30,%XMM30 |
(118) 0x421b8d KXNORW %K0,%K0,%K2 |
(118) 0x421b91 VGATHERQPD (,%ZMM4,1),%ZMM30{%K2} |
(118) 0x421b9c VPSUBQ %ZMM1,%ZMM13,%ZMM4 |
(118) 0x421ba2 VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(118) 0x421ba8 VPADDQ %ZMM4,%ZMM9,%ZMM4 |
(118) 0x421bae VXORPD %XMM31,%XMM31,%XMM31 |
(118) 0x421bb4 KXNORW %K0,%K0,%K2 |
(118) 0x421bb8 VGATHERQPD (,%ZMM4,1),%ZMM31{%K2} |
(118) 0x421bc3 VPBLENDMD %ZMM23,%ZMM22,%ZMM4{%K1} |
(118) 0x421bc9 VANDPD %ZMM11,%ZMM24,%ZMM29 |
(118) 0x421bcf VANDPD %ZMM11,%ZMM25,%ZMM5 |
(118) 0x421bd5 VPXOR %XMM13,%XMM13,%XMM13 |
(118) 0x421bda VDIVPD %ZMM28,%ZMM29,%ZMM28 |
(118) 0x421be0 VEXTRACTI64X4 $0x1,%ZMM4,%YMM29 |
(118) 0x421be7 VPMOVSXDQ %YMM29,%ZMM29 |
(118) 0x421bed VPMOVSXDQ %YMM4,%ZMM4 |
(118) 0x421bf3 VPSUBQ %ZMM1,%ZMM4,%ZMM4 |
(118) 0x421bf9 VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(118) 0x421bff VPADDQ %ZMM4,%ZMM14,%ZMM4 |
(118) 0x421c05 VXORPD %XMM8,%XMM8,%XMM8 |
(118) 0x421c0a KXNORW %K0,%K0,%K2 |
(118) 0x421c0e VGATHERQPD (,%ZMM4,1),%ZMM8{%K2} |
(118) 0x421c19 VPSUBQ %ZMM1,%ZMM29,%ZMM4 |
(118) 0x421c1f VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(118) 0x421c25 VPADDQ %ZMM4,%ZMM9,%ZMM4 |
(118) 0x421c2b VPXOR %XMM9,%XMM9,%XMM9 |
(118) 0x421c30 KXNORW %K0,%K0,%K2 |
(118) 0x421c34 VGATHERQPD (,%ZMM4,1),%ZMM9{%K2} |
(118) 0x421c3f VDIVPD %ZMM7,%ZMM5,%ZMM29 |
(118) 0x421c45 VSUBPD %ZMM31,%ZMM27,%ZMM4 |
(118) 0x421c4b VSUBPD %ZMM30,%ZMM26,%ZMM14 |
(118) 0x421c51 VSUBPD %ZMM27,%ZMM9,%ZMM7 |
(118) 0x421c57 VSUBPD %ZMM26,%ZMM8,%ZMM9 |
(118) 0x421c5d VMULPD %ZMM14,%ZMM9,%ZMM30 |
(118) 0x421c63 VMULPD %ZMM4,%ZMM7,%ZMM31 |
(118) 0x421c69 VCMPPD $0x1,%ZMM31,%ZMM13,%K0 |
(118) 0x421c70 VCMPPD $0x1,%ZMM30,%ZMM13,%K2 |
(118) 0x421c77 KORTESTB %K0,%K2 |
(118) 0x421c7b JNE 4218c0 |
(118) 0x421c81 VXORPD %XMM14,%XMM14,%XMM14 |
(118) 0x421c86 JMP 4219de |
0x421cc0 MOV %R10,0x8(%RSP) |
0x421cc5 MOV 0x40(%RSP),%RCX |
0x421cca MOV %RCX,%RAX |
0x421ccd CMP %RCX,0x80(%RSP) |
0x421cd5 VMOVDDUP 0xd4473(%RIP),%XMM8 |
0x421cdd VXORPD %XMM10,%XMM10,%XMM10 |
0x421ce2 VMOVAPD 0x150(%RSP),%XMM14 |
0x421ceb VMOVSD 0xd66db(%RIP),%XMM17 |
0x421cf5 VMOVDDUP 0xd66d9(%RIP),%XMM18 |
0x421cff VMOVSD 0xd464f(%RIP),%XMM19 |
0x421d09 JNE 421d73 |
0x421d0b JMP 421800 |
0x421d40 MOV 0x58(%RSP),%RAX |
0x421d45 LEA -0x1(%RAX,%RCX,1),%R8 |
0x421d4a MOV %R8,%RAX |
0x421d4d SUB %RDX,%RAX |
0x421d50 MOV %RAX,0x8(%RSP) |
0x421d55 MOV 0x108(%RSP),%RAX |
0x421d5d LEA (%RAX,%RCX,1),%R14D |
0x421d61 LEA 0x1(%RAX,%RCX,1),%ESI |
0x421d65 MOV %ESI,0x60(%RSP) |
0x421d69 LEA -0x2(%RAX,%RCX,1),%EAX |
0x421d6d MOV %EAX,0x68(%RSP) |
0x421d71 XOR %EAX,%EAX |
0x421d73 MOV 0x118(%RSP),%RSI |
0x421d7b SUB %RAX,%RSI |
0x421d7e MOV 0x100(%RSP),%RCX |
0x421d86 LEA (%RCX,%RAX,1),%R10 |
0x421d8a MOV (%RSP),%RCX |
0x421d8e LEA (%RCX,%R10,8),%R15 |
0x421d92 ADD 0x120(%RSP),%RAX |
0x421d9a MOV 0x128(%RSP),%RCX |
0x421da2 LEA (%RCX,%RAX,8),%RDI |
0x421da6 MOV 0xd8(%RSP),%RCX |
0x421dae LEA (%RCX,%RAX,8),%RCX |
0x421db2 MOV 0x18(%RSP),%RAX |
0x421db7 LEA (%RAX,%R10,8),%R10 |
0x421dbb XOR %EAX,%EAX |
0x421dbd JMP 421de4 |
(117) 0x421dc0 VSUBSD %XMM7,%XMM19,%XMM0 |
(117) 0x421dc6 VFMADD213SD %XMM21,%XMM9,%XMM0 |
(117) 0x421dcc VMULSD %XMM20,%XMM0,%XMM0 |
(117) 0x421dd2 VMOVSD %XMM0,(%R15,%RAX,8) |
(117) 0x421dd8 INC %RAX |
(117) 0x421ddb CMP %RAX,%RSI |
(117) 0x421dde JE 421800 |
(117) 0x421de4 VMOVSD (%R10,%RAX,8),%XMM20 |
(117) 0x421deb VXORPD %XMM9,%XMM9,%XMM9 |
(117) 0x421df0 VUCOMISD %XMM20,%XMM9 |
(117) 0x421df6 MOV 0x68(%RSP),%R9D |
(117) 0x421dfb CMOVA 0x60(%RSP),%R9D |
(117) 0x421e01 MOV %R8D,%R12D |
(117) 0x421e04 CMOVA %R14D,%R12D |
(117) 0x421e08 MOV %R14D,%R13D |
(117) 0x421e0b CMOVA %R8D,%R13D |
(117) 0x421e0f VANDPD %XMM8,%XMM20,%XMM0 |
(117) 0x421e15 MOVSXD %R12D,%R12 |
(117) 0x421e18 SUB %RDX,%R12 |
(117) 0x421e1b MOV 0x28(%RSP),%RBX |
(117) 0x421e20 IMUL %R12,%RBX |
(117) 0x421e24 ADD %RCX,%RBX |
(117) 0x421e27 VDIVSD (%RBX,%RAX,8),%XMM0,%XMM7 |
(117) 0x421e2c IMUL %R11,%R12 |
(117) 0x421e30 ADD %RDI,%R12 |
(117) 0x421e33 VMOVSD (%R12,%RAX,8),%XMM21 |
(117) 0x421e3a MOVSXD %R9D,%R9 |
(117) 0x421e3d SUB %RDX,%R9 |
(117) 0x421e40 IMUL %R11,%R9 |
(117) 0x421e44 ADD %RDI,%R9 |
(117) 0x421e47 VSUBSD (%R9,%RAX,8),%XMM21,%XMM22 |
(117) 0x421e4e MOVSXD %R13D,%R9 |
(117) 0x421e51 SUB %RDX,%R9 |
(117) 0x421e54 IMUL %R11,%R9 |
(117) 0x421e58 ADD %RDI,%R9 |
(117) 0x421e5b VMOVSD (%R9,%RAX,8),%XMM0 |
(117) 0x421e61 VSUBSD %XMM21,%XMM0,%XMM13 |
(117) 0x421e67 VMULSD %XMM22,%XMM13,%XMM0 |
(117) 0x421e6d VUCOMISD %XMM9,%XMM0 |
(117) 0x421e72 JBE 421dc0 |
(117) 0x421e78 VUCOMISD %XMM20,%XMM10 |
(117) 0x421e7e MOV 0x68(%RSP),%R9D |
(117) 0x421e83 CMOVA %R14D,%R9D |
(117) 0x421e87 MOV 0x90(%RSP),%RBX |
(117) 0x421e8f MOV 0x8(%RSP),%R12 |
(117) 0x421e94 VMOVSD (%RBX,%R12,8),%XMM0 |
(117) 0x421e9a VANDPD %XMM14,%XMM22,%XMM4 |
(117) 0x421ea0 VANDPD %XMM14,%XMM13,%XMM5 |
(117) 0x421ea5 VSUBSD %XMM7,%XMM17,%XMM6 |
(117) 0x421eab VMULSD %XMM6,%XMM5,%XMM6 |
(117) 0x421eaf VDIVSD %XMM0,%XMM6,%XMM6 |
(117) 0x421eb3 VMINSD %XMM5,%XMM4,%XMM5 |
(117) 0x421eb7 VFMADD213SD %XMM4,%XMM7,%XMM4 |
(117) 0x421ebc MOVSXD %R9D,%R9 |
(117) 0x421ebf SUB %RDX,%R9 |
(117) 0x421ec2 VDIVSD (%RBX,%R9,8),%XMM4,%XMM4 |
(117) 0x421ec8 VADDSD %XMM6,%XMM4,%XMM4 |
(117) 0x421ecc VMULSD 0xd650c(%RIP),%XMM0,%XMM0 |
(117) 0x421ed4 VMULSD %XMM4,%XMM0,%XMM0 |
(117) 0x421ed8 VMINSD %XMM5,%XMM0,%XMM9 |
(117) 0x421edc VXORPD %XMM18,%XMM9,%XMM0 |
(117) 0x421ee2 VCMPSD $0x2,%XMM10,%XMM13,%K1 |
(117) 0x421ee9 VMOVSD %XMM0,%XMM9,%XMM9{%K1} |
(117) 0x421eef JMP 421dc0 |
/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 241 |
-------------------------------------------------------------------------------- |
81: IF(mom_sweep.EQ.1)THEN ! x 1 |
[...] |
214: DO j=x_min,x_max+1 |
215: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
227: sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor)) |
228: width=celldy(k) |
229: vdiffuw=vel1(j,donor)-vel1(j,upwind) |
230: vdiffdw=vel1(j,downwind)-vel1(j,donor) |
231: limiter=0.0 |
232: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
233: auw=ABS(vdiffuw) |
234: adw=ABS(vdiffdw) |
235: wind=1.0_8 |
236: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
237: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw) |
238: ENDIF |
239: advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter |
240: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
241: ENDDO |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_invoke_task_func | libiomp5.so |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.17 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 12.08 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.31 |
| Bottlenecks | micro-operation queue, |
| Function | advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:214-215,advec_mom_kernel.f90:241-241 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 12.67 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 12.67 |
| CQA cycles if fully vectorized | 1.05 |
| Front-end cycles | 12.67 |
| P0 cycles | 5.10 |
| P1 cycles | 8.60 |
| P2 cycles | 9.67 |
| P3 cycles | 9.67 |
| P4 cycles | 5.50 |
| P5 cycles | 5.00 |
| P6 cycles | 4.90 |
| P7 cycles | 5.50 |
| P8 cycles | 5.50 |
| P9 cycles | 5.50 |
| P10 cycles | 5.00 |
| P11 cycles | 9.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 74.00 |
| Nb uops | 76.00 |
| Nb loads | 29.00 |
| Nb stores | 11.00 |
| Nb stack references | 23.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 24.63 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 240.00 |
| Bytes stored | 72.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 6.25 |
| Vectorization ratio load | 7.14 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 11.11 |
| Vector-efficiency ratio all | 11.52 |
| Vector-efficiency ratio load | 13.39 |
| Vector-efficiency ratio store | 10.23 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 10.42 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.17 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 12.08 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.31 |
| Bottlenecks | micro-operation queue, |
| Function | advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:214-215,advec_mom_kernel.f90:241-241 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 12.67 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 12.67 |
| CQA cycles if fully vectorized | 1.05 |
| Front-end cycles | 12.67 |
| P0 cycles | 5.10 |
| P1 cycles | 8.60 |
| P2 cycles | 9.67 |
| P3 cycles | 9.67 |
| P4 cycles | 5.50 |
| P5 cycles | 5.00 |
| P6 cycles | 4.90 |
| P7 cycles | 5.50 |
| P8 cycles | 5.50 |
| P9 cycles | 5.50 |
| P10 cycles | 5.00 |
| P11 cycles | 9.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 74.00 |
| Nb uops | 76.00 |
| Nb loads | 29.00 |
| Nb stores | 11.00 |
| Nb stack references | 23.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 24.63 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 240.00 |
| Bytes stored | 72.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 6.25 |
| Vectorization ratio load | 7.14 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 11.11 |
| Vector-efficiency ratio all | 11.52 |
| Vector-efficiency ratio load | 13.39 |
| Vector-efficiency ratio store | 10.23 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 10.42 |
| Path / |
| Function | advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-241 |
| Module | exec |
| nb instructions | 74 |
| nb uops | 76 |
| loop length | 389 |
| used x86 registers | 12 |
| used mmx registers | 0 |
| used xmm registers | 6 |
| used ymm registers | 0 |
| used zmm registers | 4 |
| nb stack references | 23 |
| micro-operation queue | 12.67 cycles |
| front end | 12.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 5.10 | 6.00 | 9.67 | 9.67 | 5.50 | 5.00 | 4.90 | 5.50 | 5.50 | 5.50 | 5.00 | 9.67 |
| cycles | 5.10 | 8.60 | 9.67 | 9.67 | 5.50 | 5.00 | 4.90 | 5.50 | 5.50 | 5.50 | 5.00 | 9.67 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 12.67 |
| Dispatch | 9.67 |
| Overall L1 | 12.67 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 33% |
| load | 20% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 6% |
| load | 7% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 11% |
| all | 10% |
| load | 12% |
| store | 10% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 8% |
| all | 16% |
| load | 15% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 11% |
| load | 13% |
| store | 10% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 10% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x130(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x48(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| ADD %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| MOV 0x170(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x88(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| ADD %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| ADD %RCX,(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 | scal (12.5%) |
| ADD %RAX,0x18(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 | scal (12.5%) |
| MOV 0x20(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| CMP 0x10(%RSP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| LEA 0x1(%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x38(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JE 421700 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x28a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| CMPQ $0,0x40(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %RDI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| JE 421d40 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2ee0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV 0x58(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA -0x1(%RAX,%RCX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SUB %RDX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x108(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RAX,%RCX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| LEA 0x1(%RAX,%RCX,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %ESI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VPBROADCASTD %ESI,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| LEA -0x2(%RAX,%RCX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %EAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VPBROADCASTD %EAX,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| VPBROADCASTD %R14D,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| VPBROADCASTD %R8D,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (6.3%) |
| MOV 0xb0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| JMP 421a42 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2be2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| MOV %R10,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV 0x40(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RCX,0x80(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVDDUP 0xd4473(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VXORPD %XMM10,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VMOVAPD 0x150(%RSP),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| VMOVSD 0xd66db(%RIP),%XMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVDDUP 0xd66d9(%RIP),%XMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVSD 0xd464f(%RIP),%XMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JNE 421d73 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2f13> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| JMP 421800 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x29a0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| MOV 0x58(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA -0x1(%RAX,%RCX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SUB %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %RAX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV 0x108(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RAX,%RCX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| LEA 0x1(%RAX,%RCX,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %ESI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA -0x2(%RAX,%RCX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %EAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x118(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| MOV 0x100(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RCX,%RAX,1),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV (%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RCX,%R10,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| ADD 0x120(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x128(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RCX,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0xd8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RCX,%RAX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x18(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RAX,%R10,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JMP 421de4 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2f84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 | N/A |
| Function | advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-241 |
| Module | exec |
| nb instructions | 74 |
| nb uops | 76 |
| loop length | 389 |
| used x86 registers | 12 |
| used mmx registers | 0 |
| used xmm registers | 6 |
| used ymm registers | 0 |
| used zmm registers | 4 |
| nb stack references | 23 |
| micro-operation queue | 12.67 cycles |
| front end | 12.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 5.10 | 6.00 | 9.67 | 9.67 | 5.50 | 5.00 | 4.90 | 5.50 | 5.50 | 5.50 | 5.00 | 9.67 |
| cycles | 5.10 | 8.60 | 9.67 | 9.67 | 5.50 | 5.00 | 4.90 | 5.50 | 5.50 | 5.50 | 5.00 | 9.67 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 12.67 |
| Dispatch | 9.67 |
| Overall L1 | 12.67 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 33% |
| load | 20% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 6% |
| load | 7% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 11% |
| all | 10% |
| load | 12% |
| store | 10% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 8% |
| all | 16% |
| load | 15% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 11% |
| load | 13% |
| store | 10% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 10% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x130(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x48(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| ADD %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| MOV 0x170(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x88(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| ADD %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| ADD %RCX,(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 | scal (12.5%) |
| ADD %RAX,0x18(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 | scal (12.5%) |
| MOV 0x20(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| CMP 0x10(%RSP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| LEA 0x1(%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x38(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JE 421700 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x28a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| CMPQ $0,0x40(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %RDI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| JE 421d40 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2ee0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV 0x58(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA -0x1(%RAX,%RCX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SUB %RDX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x108(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RAX,%RCX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| LEA 0x1(%RAX,%RCX,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %ESI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VPBROADCASTD %ESI,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| LEA -0x2(%RAX,%RCX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %EAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VPBROADCASTD %EAX,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| VPBROADCASTD %R14D,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| VPBROADCASTD %R8D,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (6.3%) |
| MOV 0xb0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| JMP 421a42 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2be2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| MOV %R10,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV 0x40(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RCX,0x80(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVDDUP 0xd4473(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VXORPD %XMM10,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VMOVAPD 0x150(%RSP),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| VMOVSD 0xd66db(%RIP),%XMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVDDUP 0xd66d9(%RIP),%XMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVSD 0xd464f(%RIP),%XMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JNE 421d73 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2f13> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| JMP 421800 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x29a0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| MOV 0x58(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA -0x1(%RAX,%RCX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SUB %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %RAX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV 0x108(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RAX,%RCX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| LEA 0x1(%RAX,%RCX,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %ESI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA -0x2(%RAX,%RCX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %EAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x118(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| MOV 0x100(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RCX,%RAX,1),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV (%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RCX,%R10,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| ADD 0x120(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x128(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RCX,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0xd8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RCX,%RAX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x18(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RAX,%R10,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JMP 421de4 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2f84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 | N/A |
