OV - exec - Function field_summary_kernel_module_mp_field_summary_kernel

	Function: field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2	Module: exec	Source: field_summary_kernel.f90:54-74	Coverage (incl. loops): 0.29% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 54 - 74

--------------------------------------------------------------------------------

54:     !$OMP PARALLEL

55:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

56:     DO k=y_min,y_max

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

72:       ENDDO

73:     ENDDO

74:   !$OMP END DO

0x42a030 PUSH	%RBP

0x42a031 MOV	%RSP,%RBP

0x42a034 PUSH	%R15

0x42a036 PUSH	%R14

0x42a038 PUSH	%R13

0x42a03a PUSH	%R12

0x42a03c PUSH	%RBX

0x42a03d SUB	$0x98,%RSP

0x42a044 MOV	%RCX,%R15

0x42a047 MOV	0x70(%RBP),%ECX

0x42a04a MOV	0x68(%RBP),%EAX

0x42a04d SUB	%ECX,%EAX

0x42a04f MOVL	$0,-0x4c(%RBP)

0x42a056 JS	42aa19

0x42a05c MOV	%R9,%R14

0x42a05f MOV	%RDI,-0x30(%RBP)

0x42a063 MOV	(%RDI),%ESI

0x42a065 MOVL	$0,-0x3c(%RBP)

0x42a06c MOV	%EAX,-0x38(%RBP)

0x42a06f MOVL	$0x1,-0x48(%RBP)

0x42a076 SUB	$0x8,%RSP

0x42a07a LEA	-0x48(%RBP),%RAX

0x42a07e LEA	-0x4c(%RBP),%RCX

0x42a082 LEA	-0x3c(%RBP),%R8

0x42a086 LEA	-0x38(%RBP),%R9

0x42a08a MOV	$0x53a5b0,%EDI

0x42a08f MOV	%ESI,-0x40(%RBP)

0x42a092 MOV	$0x22,%EDX

0x42a097 PUSH	$0x1

0x42a099 PUSH	$0x1

0x42a09b PUSH	%RAX

0x42a09c CALL	404850 <__kmpc_for_static_init_4@plt>

0x42a0a1 ADD	$0x20,%RSP

0x42a0a5 MOV	-0x3c(%RBP),%R8D

0x42a0a9 MOV	-0x38(%RBP),%R10D

0x42a0ad VXORPD	%XMM1,%XMM1,%XMM1

0x42a0b1 VXORPD	%XMM3,%XMM3,%XMM3

0x42a0b5 VXORPD	%XMM0,%XMM0,%XMM0

0x42a0b9 VXORPD	%XMM5,%XMM5,%XMM5

0x42a0bd VXORPD	%XMM7,%XMM7,%XMM7

0x42a0c1 CMP	%R10D,%R8D

0x42a0c4 JBE	42a1c0

0x42a0ca MOV	0x30(%RBP),%R15

0x42a0ce MOV	0x28(%RBP),%R14

0x42a0d2 MOV	0x20(%RBP),%R12

0x42a0d6 MOV	0x18(%RBP),%RBX

0x42a0da MOV	0x10(%RBP),%R13

0x42a0de VMOVSD	%XMM7,-0x78(%RBP)

0x42a0e3 VMOVSD	%XMM5,-0x70(%RBP)

0x42a0e8 VMOVSD	%XMM0,-0x68(%RBP)

0x42a0ed VMOVSD	%XMM3,-0x60(%RBP)

0x42a0f2 VMOVSD	%XMM1,-0x58(%RBP)

0x42a0f7 MOV	$0x53a5d0,%EDI

0x42a0fc MOV	-0x40(%RBP),%ESI

0x42a0ff VZEROUPPER

0x42a102 CALL	404070 <__kmpc_for_static_fini@plt>

0x42a107 MOV	-0x30(%RBP),%RAX

0x42a10b MOV	(%RAX),%ESI

0x42a10d SUB	$0x8,%RSP

0x42a111 MOV	$0x593220,%RAX

0x42a118 LEA	-0x78(%RBP),%R8

0x42a11c MOV	$0x53a690,%EDI

0x42a121 MOV	$0x429fe0,%R9D

0x42a127 MOV	$0x5,%EDX

0x42a12c MOV	$0x28,%ECX

0x42a131 PUSH	%RAX

0x42a132 CALL	4045b0 <__kmpc_reduce@plt>

0x42a137 ADD	$0x10,%RSP

0x42a13b CMP	$0x2,%EAX

0x42a13e JGE	42a980

0x42a144 CMP	$0x1,%EAX

0x42a147 MOV	-0x30(%RBP),%RDI

0x42a14b JNE	42aa19

0x42a151 VMOVSD	-0x78(%RBP),%XMM0

0x42a156 VADDSD	(%R15),%XMM0,%XMM0

0x42a15b VMOVSD	%XMM0,(%R15)

0x42a160 VMOVSD	-0x70(%RBP),%XMM0

0x42a165 VADDSD	(%R14),%XMM0,%XMM0

0x42a16a VMOVSD	%XMM0,(%R14)

0x42a16f VMOVSD	-0x68(%RBP),%XMM0

0x42a174 VADDSD	(%R13),%XMM0,%XMM0

0x42a17a VMOVSD	%XMM0,(%R13)

0x42a180 VMOVSD	-0x60(%RBP),%XMM0

0x42a185 VADDSD	(%R12),%XMM0,%XMM0

0x42a18b VMOVSD	%XMM0,(%R12)

0x42a191 VMOVSD	-0x58(%RBP),%XMM0

0x42a196 VADDSD	(%RBX),%XMM0,%XMM0

0x42a19a VMOVSD	%XMM0,(%RBX)

0x42a19e MOV	(%RDI),%ESI

0x42a1a0 MOV	$0x593220,%RDX

0x42a1a7 MOV	$0x53a6b0,%EDI

0x42a1ac JMP	42aa10

0x42a1b1 NOPW	%CS:(%RAX,%RAX,1)

0x42a1c0 MOV	0x80(%RBP),%RAX

0x42a1c7 MOV	0x78(%RBP),%RCX

0x42a1cb MOVSXD	(%RAX),%RAX

0x42a1ce MOV	(%RCX),%ECX

0x42a1d0 SUB	%EAX,%ECX

0x42a1d2 ADD	$-0x2,%R14D

0x42a1d6 MOVSXD	%R14D,%R14

0x42a1d9 ADD	$-0x2,%R15D

0x42a1dd MOVSXD	%R15D,%RDX

0x42a1e0 MOV	%RDX,-0xb0(%RBP)

0x42a1e7 MOV	%RCX,-0xb8(%RBP)

0x42a1ee INC	%ECX

0x42a1f0 LEA	0x2(%RAX),%RDX

0x42a1f4 CMP	$0x2,%ECX

0x42a1f7 MOV	$0x1,%ESI

0x42a1fc MOV	%ECX,-0x44(%RBP)

0x42a1ff CMOVGE	%ECX,%ESI

0x42a202 MOV	%RDX,-0xa8(%RBP)

0x42a209 VPBROADCASTQ	%RDX,%ZMM0

0x42a20f VPMOVSXBQ	0xcc147(%RIP),%ZMM2

0x42a219 VPADDQ	%ZMM2,%ZMM0,%ZMM4

0x42a21f VPBROADCASTQ	%RAX,%ZMM0

0x42a225 VPADDQ	%ZMM2,%ZMM0,%ZMM6

0x42a22b MOV	%RSI,-0x80(%RBP)

0x42a22f AND	$0x7ffffff8,%ESI

0x42a235 VPBROADCASTQ	%R14,%ZMM8

0x42a23b VPXOR	%XMM0,%XMM0,%XMM0

0x42a23f VPBROADCASTQ	0xd15bf(%RIP),%ZMM9

0x42a249 VPTERNLOGD	$-0x1,%ZMM10,%ZMM10,%ZMM10

0x42a250 VBROADCASTSD	0xcc86e(%RIP),%ZMM11

0x42a25a VBROADCASTSD	0xcce9c(%RIP),%ZMM12

0x42a264 LEA	0x2(%RAX,%RSI,1),%RCX

0x42a269 MOV	%RCX,-0xa0(%RBP)

0x42a270 MOV	%RAX,%RDI

0x42a273 MOV	%RSI,-0x90(%RBP)

0x42a27a ADD	%RSI,%RAX

0x42a27d MOV	%RAX,-0x98(%RBP)

0x42a284 MOV	%R10D,-0x34(%RBP)

0x42a288 JMP	42a3d0

0x42a28d NOPW	%CS:(%RAX,%RAX,1)

0x42a29c NOPW	%CS:(%RAX,%RAX,1)

0x42a2ab NOPW	%CS:(%RAX,%RAX,1)

0x42a2ba NOPW	(%RAX,%RAX,1)

(169) 0x42a2c0 VEXTRACTF64X4	$0x1,%ZMM20,%YMM15

(169) 0x42a2c7 VADDPD	%ZMM15,%ZMM20,%ZMM15

(169) 0x42a2cd VMOVAPD	%XMM15,%XMM16

(169) 0x42a2d3 VEXTRACTF128	$0x1,%YMM15,%XMM15

(169) 0x42a2d9 VADDPD	%XMM15,%XMM16,%XMM15

(169) 0x42a2df VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

(169) 0x42a2e6 VADDSD	%XMM16,%XMM15,%XMM15

(169) 0x42a2ec VADDSD	%XMM0,%XMM15,%XMM0

(169) 0x42a2f0 VEXTRACTF64X4	$0x1,%ZMM19,%YMM15

(169) 0x42a2f7 VADDPD	%ZMM15,%ZMM19,%ZMM15

(169) 0x42a2fd VMOVAPD	%XMM15,%XMM16

(169) 0x42a303 VEXTRACTF128	$0x1,%YMM15,%XMM15

(169) 0x42a309 VADDPD	%XMM15,%XMM16,%XMM15

(169) 0x42a30f VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

(169) 0x42a316 VADDSD	%XMM16,%XMM15,%XMM15

(169) 0x42a31c VADDSD	%XMM1,%XMM15,%XMM1

(169) 0x42a320 VEXTRACTF64X4	$0x1,%ZMM17,%YMM15

(169) 0x42a327 VADDPD	%ZMM15,%ZMM17,%ZMM15

(169) 0x42a32d VMOVAPD	%XMM15,%XMM16

(169) 0x42a333 VEXTRACTF128	$0x1,%YMM15,%XMM15

(169) 0x42a339 VADDPD	%XMM15,%XMM16,%XMM15

(169) 0x42a33f VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

(169) 0x42a346 VADDSD	%XMM16,%XMM15,%XMM15

(169) 0x42a34c VADDSD	%XMM3,%XMM15,%XMM3

(169) 0x42a350 VEXTRACTF64X4	$0x1,%ZMM14,%YMM15

(169) 0x42a357 VADDPD	%ZMM15,%ZMM14,%ZMM14

(169) 0x42a35d VMOVAPD	%XMM14,%XMM15

(169) 0x42a362 VEXTRACTF128	$0x1,%YMM14,%XMM14

(169) 0x42a368 VADDPD	%XMM14,%XMM15,%XMM14

(169) 0x42a36d VSHUFPD	$0x1,%XMM14,%XMM14,%XMM15

(169) 0x42a373 VADDSD	%XMM15,%XMM14,%XMM14

(169) 0x42a378 VADDSD	%XMM5,%XMM14,%XMM5

(169) 0x42a37c VEXTRACTF64X4	$0x1,%ZMM13,%YMM14

(169) 0x42a383 VADDPD	%ZMM14,%ZMM13,%ZMM13

(169) 0x42a389 VMOVAPD	%XMM13,%XMM14

(169) 0x42a38e VEXTRACTF128	$0x1,%YMM13,%XMM13

(169) 0x42a394 VADDPD	%XMM13,%XMM14,%XMM13

(169) 0x42a399 VSHUFPD	$0x1,%XMM13,%XMM13,%XMM14

(169) 0x42a39f VADDSD	%XMM14,%XMM13,%XMM13

(169) 0x42a3a4 VADDSD	%XMM7,%XMM13,%XMM7

(169) 0x42a3a8 MOV	-0x88(%RBP),%R8

(169) 0x42a3af MOV	-0x34(%RBP),%R10D

(169) 0x42a3b3 JMP	42a3c0

0x42a3b5 NOPW	%CS:(%RAX,%RAX,1)

(169) 0x42a3c0 LEA	0x1(%R8),%EAX

(169) 0x42a3c4 CMP	%R10D,%R8D

(169) 0x42a3c7 MOV	%EAX,%R8D

(169) 0x42a3ca JE	42a0ca

(169) 0x42a3d0 CMPL	$0,-0xb8(%RBP)

(169) 0x42a3d7 JS	42a3c0

(169) 0x42a3d9 MOV	0x70(%RBP),%EAX

(169) 0x42a3dc ADD	%R8D,%EAX

(169) 0x42a3df MOVSXD	%EAX,%R9

(169) 0x42a3e2 SUB	-0xb0(%RBP),%R9

(169) 0x42a3e9 MOV	0x98(%RBP),%RAX

(169) 0x42a3f0 MOV	(%RAX),%R12

(169) 0x42a3f3 IMUL	%R9,%R12

(169) 0x42a3f7 ADD	0x60(%RBP),%R12

(169) 0x42a3fb MOV	0xa0(%RBP),%RAX

(169) 0x42a402 MOV	(%RAX),%RDX

(169) 0x42a405 IMUL	%R9,%RDX

(169) 0x42a409 ADD	0x58(%RBP),%RDX

(169) 0x42a40d MOV	0xa8(%RBP),%RAX

(169) 0x42a414 MOV	(%RAX),%R15

(169) 0x42a417 IMUL	%R9,%R15

(169) 0x42a41b ADD	0x50(%RBP),%R15

(169) 0x42a41f MOV	0xb0(%RBP),%RAX

(169) 0x42a426 MOV	(%RAX),%R13

(169) 0x42a429 IMUL	%R9,%R13

(169) 0x42a42d ADD	0x48(%RBP),%R13

(169) 0x42a431 MOV	0x88(%RBP),%RAX

(169) 0x42a438 MOV	(%RAX),%R11

(169) 0x42a43b MOV	0x90(%RBP),%RAX

(169) 0x42a442 MOV	(%RAX),%RCX

(169) 0x42a445 CMPL	$0x8,-0x44(%RBP)

(169) 0x42a449 MOV	%R8,-0x88(%RBP)

(169) 0x42a450 MOV	%RCX,-0xc0(%RBP)

(169) 0x42a457 JGE	42a480

(169) 0x42a459 XOR	%ESI,%ESI

(169) 0x42a45b MOV	-0xa8(%RBP),%RAX

(169) 0x42a462 MOV	%RDI,%RCX

(169) 0x42a465 JMP	42a70c

0x42a46a NOPW	%CS:(%RAX,%RAX,1)

0x42a479 NOPL	(%RAX)

(169) 0x42a480 MOV	%R11,%RSI

(169) 0x42a483 IMUL	%R9,%RSI

(169) 0x42a487 MOV	0x40(%RBP),%RAX

(169) 0x42a48b ADD	%RAX,%RSI

(169) 0x42a48e MOV	%RCX,%R8

(169) 0x42a491 IMUL	%R9,%R8

(169) 0x42a495 MOV	0x38(%RBP),%R10

(169) 0x42a499 ADD	%R10,%R8

(169) 0x42a49c LEA	0x1(%R9),%RBX

(169) 0x42a4a0 MOV	%R11,%RAX

(169) 0x42a4a3 IMUL	%RBX,%RAX

(169) 0x42a4a7 ADD	0x40(%RBP),%RAX

(169) 0x42a4ab IMUL	%RCX,%RBX

(169) 0x42a4af ADD	%R10,%RBX

(169) 0x42a4b2 VXORPD	%XMM17,%XMM17,%XMM17

(169) 0x42a4b8 XOR	%ECX,%ECX

(169) 0x42a4ba VMOVDQA64	%ZMM4,%ZMM18

(169) 0x42a4c0 VMOVDQA64	%ZMM6,%ZMM19

(169) 0x42a4c6 VXORPD	%XMM16,%XMM16,%XMM16

(169) 0x42a4cc VXORPD	%XMM15,%XMM15,%XMM15

(169) 0x42a4d1 VXORPD	%XMM14,%XMM14,%XMM14

(169) 0x42a4d6 VXORPD	%XMM13,%XMM13,%XMM13

(169) 0x42a4db NOPL	(%RAX,%RAX,1)

  (172) 0x42a4e0 KXNORW	%K0,%K0,%K1

  (172) 0x42a4e4 VMOVDQA64	%ZMM19,%ZMM22

  (172) 0x42a4ea VXORPD	%XMM21,%XMM21,%XMM21

    (170) 0x42a4f0 VPSUBQ	%ZMM10,%ZMM22,%ZMM23

    (170) 0x42a4f6 VMOVQ	%XMM22,%R10

    (170) 0x42a4fc SUB	%R14,%R10

    (170) 0x42a4ff VMOVUPD	(%R8,%R10,8),%ZMM22{%K1}{z}

    (170) 0x42a506 VMOVUPD	(%RSI,%R10,8),%ZMM24{%K1}{z}

    (170) 0x42a50d VMULPD	%ZMM24,%ZMM24,%ZMM24

    (170) 0x42a513 VFMADD231PD	%ZMM22,%ZMM22,%ZMM24

    (170) 0x42a519 VFMADD231PD	%ZMM11,%ZMM24,%ZMM21

    (170) 0x42a51f VMOVAPD	%ZMM21,%ZMM20{%K1}

    (170) 0x42a525 VPCMPNEQQ	%ZMM18,%ZMM23,%K1{%K1}

    (170) 0x42a52c KORTESTB	%K1,%K1

    (170) 0x42a530 VMOVDQA64	%ZMM23,%ZMM22

    (170) 0x42a536 JNE	42a4f0

  (172) 0x42a538 KXNORW	%K0,%K0,%K1

  (172) 0x42a53c VMOVDQA64	%ZMM19,%ZMM22

  (172) 0x42a542 NOPW	%CS:(%RAX,%RAX,1)

    (171) 0x42a550 VPSUBQ	%ZMM10,%ZMM22,%ZMM23

    (171) 0x42a556 VMOVQ	%XMM22,%R10

    (171) 0x42a55c SUB	%R14,%R10

    (171) 0x42a55f VMOVUPD	(%RBX,%R10,8),%ZMM22{%K1}{z}

    (171) 0x42a566 VMOVUPD	(%RAX,%R10,8),%ZMM24{%K1}{z}

    (171) 0x42a56d VMULPD	%ZMM24,%ZMM24,%ZMM24

    (171) 0x42a573 VFMADD231PD	%ZMM22,%ZMM22,%ZMM24

    (171) 0x42a579 VFMADD231PD	%ZMM11,%ZMM24,%ZMM20

    (171) 0x42a57f VMOVAPD	%ZMM20,%ZMM21{%K1}

    (171) 0x42a585 VPCMPNEQQ	%ZMM18,%ZMM23,%K1{%K1}

    (171) 0x42a58c KORTESTB	%K1,%K1

    (171) 0x42a590 VMOVDQA64	%ZMM23,%ZMM22

    (171) 0x42a596 JNE	42a550

  (172) 0x42a598 LEA	(%RCX,%RDI,1),%R10

  (172) 0x42a59c SUB	%R14,%R10

  (172) 0x42a59f VMOVUPD	(%R12,%R10,8),%ZMM20

  (172) 0x42a5a6 VMULPD	(%RDX,%R10,8),%ZMM20,%ZMM22

  (172) 0x42a5ad VADDPD	%ZMM20,%ZMM13,%ZMM13

  (172) 0x42a5b3 VADDPD	%ZMM22,%ZMM14,%ZMM14

  (172) 0x42a5b9 VFMADD231PD	(%R15,%R10,8),%ZMM22,%ZMM15

  (172) 0x42a5c0 VMULPD	%ZMM12,%ZMM22,%ZMM22

  (172) 0x42a5c6 VFMADD231PD	%ZMM21,%ZMM22,%ZMM16

  (172) 0x42a5cc VFMADD231PD	(%R13,%R10,8),%ZMM20,%ZMM17

  (172) 0x42a5d4 ADD	$0x8,%RCX

  (172) 0x42a5d8 VPADDQ	%ZMM9,%ZMM19,%ZMM19

  (172) 0x42a5de VPADDQ	%ZMM9,%ZMM18,%ZMM18

  (172) 0x42a5e4 CMP	-0x90(%RBP),%RCX

  (172) 0x42a5eb JB	42a4e0

(169) 0x42a5f1 VEXTRACTF64X4	$0x1,%ZMM17,%YMM18

(169) 0x42a5f8 VADDPD	%ZMM18,%ZMM17,%ZMM17

(169) 0x42a5fe VMOVAPD	%XMM17,%XMM18

(169) 0x42a604 VEXTRACTF32X4	$0x1,%YMM17,%XMM17

(169) 0x42a60b VADDPD	%XMM17,%XMM18,%XMM17

(169) 0x42a611 VSHUFPD	$0x1,%XMM17,%XMM17,%XMM18

(169) 0x42a618 VADDSD	%XMM18,%XMM17,%XMM17

(169) 0x42a61e VADDSD	%XMM17,%XMM0,%XMM0

(169) 0x42a624 VEXTRACTF64X4	$0x1,%ZMM16,%YMM17

(169) 0x42a62b VADDPD	%ZMM17,%ZMM16,%ZMM16

(169) 0x42a631 VMOVAPD	%XMM16,%XMM17

(169) 0x42a637 VEXTRACTF32X4	$0x1,%YMM16,%XMM16

(169) 0x42a63e VADDPD	%XMM16,%XMM17,%XMM16

(169) 0x42a644 VSHUFPD	$0x1,%XMM16,%XMM16,%XMM17

(169) 0x42a64b VADDSD	%XMM17,%XMM16,%XMM16

(169) 0x42a651 VADDSD	%XMM16,%XMM1,%XMM1

(169) 0x42a657 VEXTRACTF64X4	$0x1,%ZMM15,%YMM16

(169) 0x42a65e VADDPD	%ZMM16,%ZMM15,%ZMM15

(169) 0x42a664 VMOVAPD	%XMM15,%XMM16

(169) 0x42a66a VEXTRACTF128	$0x1,%YMM15,%XMM15

(169) 0x42a670 VADDPD	%XMM15,%XMM16,%XMM15

(169) 0x42a676 VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

(169) 0x42a67d VADDSD	%XMM16,%XMM15,%XMM15

(169) 0x42a683 VADDSD	%XMM3,%XMM15,%XMM3

(169) 0x42a687 VEXTRACTF64X4	$0x1,%ZMM14,%YMM15

(169) 0x42a68e VADDPD	%ZMM15,%ZMM14,%ZMM14

(169) 0x42a694 VMOVAPD	%XMM14,%XMM15

(169) 0x42a699 VEXTRACTF128	$0x1,%YMM14,%XMM14

(169) 0x42a69f VADDPD	%XMM14,%XMM15,%XMM14

(169) 0x42a6a4 VSHUFPD	$0x1,%XMM14,%XMM14,%XMM15

(169) 0x42a6aa VADDSD	%XMM15,%XMM14,%XMM14

(169) 0x42a6af VADDSD	%XMM5,%XMM14,%XMM5

(169) 0x42a6b3 VEXTRACTF64X4	$0x1,%ZMM13,%YMM14

(169) 0x42a6ba VADDPD	%ZMM14,%ZMM13,%ZMM13

(169) 0x42a6c0 VMOVAPD	%XMM13,%XMM14

(169) 0x42a6c5 VEXTRACTF128	$0x1,%YMM13,%XMM13

(169) 0x42a6cb VADDPD	%XMM13,%XMM14,%XMM13

(169) 0x42a6d0 VSHUFPD	$0x1,%XMM13,%XMM13,%XMM14

(169) 0x42a6d6 VADDSD	%XMM14,%XMM13,%XMM13

(169) 0x42a6db VADDSD	%XMM7,%XMM13,%XMM7

(169) 0x42a6df MOV	-0x90(%RBP),%R8

(169) 0x42a6e6 MOV	%R8,%RSI

(169) 0x42a6e9 MOV	-0xa0(%RBP),%RAX

(169) 0x42a6f0 MOV	-0x98(%RBP),%RCX

(169) 0x42a6f7 CMP	-0x80(%RBP),%R8D

(169) 0x42a6fb MOV	-0x34(%RBP),%R10D

(169) 0x42a6ff MOV	-0x88(%RBP),%R8

(169) 0x42a706 JE	42a3c0

(169) 0x42a70c VPBROADCASTQ	%RAX,%ZMM13

(169) 0x42a712 VPADDQ	%ZMM2,%ZMM13,%ZMM15

(169) 0x42a718 VPBROADCASTQ	%RCX,%ZMM13

(169) 0x42a71e VPADDQ	%ZMM2,%ZMM13,%ZMM16

(169) 0x42a724 MOV	-0x80(%RBP),%RAX

(169) 0x42a728 SUB	%RSI,%RAX

(169) 0x42a72b VPBROADCASTQ	%RAX,%ZMM18

(169) 0x42a731 MOV	%R11,%RBX

(169) 0x42a734 IMUL	%R9,%RBX

(169) 0x42a738 MOV	0x40(%RBP),%RAX

(169) 0x42a73c ADD	%RAX,%RBX

(169) 0x42a73f MOV	-0xc0(%RBP),%R10

(169) 0x42a746 MOV	%R10,%R8

(169) 0x42a749 IMUL	%R9,%R8

(169) 0x42a74d MOV	0x38(%RBP),%RCX

(169) 0x42a751 ADD	%RCX,%R8

(169) 0x42a754 INC	%R9

(169) 0x42a757 IMUL	%R9,%R11

(169) 0x42a75b ADD	%RAX,%R11

(169) 0x42a75e IMUL	%R10,%R9

(169) 0x42a762 ADD	%RCX,%R9

(169) 0x42a765 ADD	%RDI,%RSI

(169) 0x42a768 VXORPD	%XMM20,%XMM20,%XMM20

(169) 0x42a76e VMOVDQA64	%ZMM2,%ZMM21

(169) 0x42a774 VPXORD	%XMM19,%XMM19,%XMM19

(169) 0x42a77a VXORPD	%XMM17,%XMM17,%XMM17

(169) 0x42a780 VXORPD	%XMM14,%XMM14,%XMM14

(169) 0x42a785 VPXOR	%XMM13,%XMM13,%XMM13

(169) 0x42a78a JMP	42a801

0x42a78c NOPW	%CS:(%RAX,%RAX,1)

0x42a79b NOPW	%CS:(%RAX,%RAX,1)

0x42a7aa NOPW	%CS:(%RAX,%RAX,1)

0x42a7b9 NOPL	(%RAX)

  (173) 0x42a7c0 VMOVAPD	%ZMM23,%ZMM13{%K1}

  (173) 0x42a7c6 VMOVAPD	%ZMM24,%ZMM14{%K1}

  (173) 0x42a7cc VMOVAPD	%ZMM25,%ZMM17{%K1}

  (173) 0x42a7d2 VMOVAPD	%ZMM22,%ZMM19{%K1}

  (173) 0x42a7d8 VMOVAPD	%ZMM26,%ZMM20{%K1}

  (173) 0x42a7de VMOVDQA64	%ZMM27,%ZMM16{%K1}

  (173) 0x42a7e4 VMOVDQA64	%ZMM28,%ZMM15{%K1}

  (173) 0x42a7ea VPADDQ	%ZMM9,%ZMM21,%ZMM21

  (173) 0x42a7f0 VPCMPLTUQ	%ZMM18,%ZMM21,%K0

  (173) 0x42a7f7 KORTESTB	%K0,%K0

  (173) 0x42a7fb JE	42a2c0

  (173) 0x42a801 VPCMPLTUQ	%ZMM18,%ZMM21,%K1

  (173) 0x42a808 KORTESTB	%K1,%K1

  (173) 0x42a80c VPXORD	%XMM23,%XMM23,%XMM23

  (173) 0x42a812 VXORPD	%XMM24,%XMM24,%XMM24

  (173) 0x42a818 VXORPD	%XMM25,%XMM25,%XMM25

  (173) 0x42a81e VXORPD	%XMM22,%XMM22,%XMM22

  (173) 0x42a824 VXORPD	%XMM26,%XMM26,%XMM26

  (173) 0x42a82a VXORPD	%XMM27,%XMM27,%XMM27

  (173) 0x42a830 VPXORD	%XMM28,%XMM28,%XMM28

  (173) 0x42a836 JE	42a7c0

  (173) 0x42a838 KXNORW	%K0,%K0,%K2

  (173) 0x42a83c VMOVDQA64	%ZMM16,%ZMM24

  (173) 0x42a842 NOPW	%CS:(%RAX,%RAX,1)

    (174) 0x42a850 VPSUBQ	%ZMM8,%ZMM24,%ZMM25

    (174) 0x42a856 VPSUBQ	%ZMM10,%ZMM24,%ZMM24

    (174) 0x42a85c KANDB	%K2,%K1,%K3

    (174) 0x42a860 KMOVQ	%K3,%K4

    (174) 0x42a865 VXORPD	%XMM26,%XMM26,%XMM26

    (174) 0x42a86b VGATHERQPD	(%R8,%ZMM25,8),%ZMM26{%K4}

    (174) 0x42a872 VXORPD	%XMM27,%XMM27,%XMM27

    (174) 0x42a878 VGATHERQPD	(%RBX,%ZMM25,8),%ZMM27{%K3}

    (174) 0x42a87f VMULPD	%ZMM27,%ZMM27,%ZMM25

    (174) 0x42a885 VFMADD231PD	%ZMM26,%ZMM26,%ZMM25

    (174) 0x42a88b VFMADD231PD	%ZMM11,%ZMM25,%ZMM22

    (174) 0x42a891 VMOVAPD	%ZMM22,%ZMM23{%K2}

    (174) 0x42a897 VPCMPNEQQ	%ZMM15,%ZMM24,%K2{%K2}

    (174) 0x42a89e KTESTB	%K1,%K2

    (174) 0x42a8a2 JNE	42a850

  (173) 0x42a8a4 KXNORW	%K0,%K0,%K2

  (173) 0x42a8a8 VMOVDQA64	%ZMM16,%ZMM24

  (173) 0x42a8ae XCHG	%AX,%AX

    (175) 0x42a8b0 VPSUBQ	%ZMM8,%ZMM24,%ZMM25

    (175) 0x42a8b6 VPSUBQ	%ZMM10,%ZMM24,%ZMM24

    (175) 0x42a8bc KANDB	%K2,%K1,%K3

    (175) 0x42a8c0 KMOVQ	%K3,%K4

    (175) 0x42a8c5 VXORPD	%XMM26,%XMM26,%XMM26

    (175) 0x42a8cb VGATHERQPD	(%R9,%ZMM25,8),%ZMM26{%K4}

    (175) 0x42a8d2 VXORPD	%XMM27,%XMM27,%XMM27

    (175) 0x42a8d8 VGATHERQPD	(%R11,%ZMM25,8),%ZMM27{%K3}

    (175) 0x42a8df VMULPD	%ZMM27,%ZMM27,%ZMM25

    (175) 0x42a8e5 VFMADD231PD	%ZMM26,%ZMM26,%ZMM25

    (175) 0x42a8eb VFMADD231PD	%ZMM11,%ZMM25,%ZMM23

    (175) 0x42a8f1 VMOVAPD	%ZMM23,%ZMM22{%K2}

    (175) 0x42a8f7 VPCMPNEQQ	%ZMM15,%ZMM24,%K2{%K2}

    (175) 0x42a8fe KTESTB	%K1,%K2

    (175) 0x42a902 JNE	42a8b0

  (173) 0x42a904 VMOVQ	%XMM21,%RAX

  (173) 0x42a90a ADD	%RSI,%RAX

  (173) 0x42a90d SUB	%R14,%RAX

  (173) 0x42a910 VMOVUPD	(%R12,%RAX,8),%ZMM27{%K1}{z}

  (173) 0x42a917 VMOVUPD	(%RDX,%RAX,8),%ZMM23{%K1}{z}

  (173) 0x42a91e VMULPD	%ZMM27,%ZMM23,%ZMM26

  (173) 0x42a924 VADDPD	%ZMM27,%ZMM13,%ZMM23

  (173) 0x42a92a VADDPD	%ZMM26,%ZMM14,%ZMM24

  (173) 0x42a930 VMOVUPD	(%R15,%RAX,8),%ZMM25{%K1}{z}

  (173) 0x42a937 VFMADD213PD	%ZMM17,%ZMM26,%ZMM25

  (173) 0x42a93d VMULPD	%ZMM12,%ZMM26,%ZMM26

  (173) 0x42a943 VFMADD213PD	%ZMM19,%ZMM26,%ZMM22

  (173) 0x42a949 VMOVUPD	(%R13,%RAX,8),%ZMM26{%K1}{z}

  (173) 0x42a951 VFMADD213PD	%ZMM20,%ZMM27,%ZMM26

  (173) 0x42a957 VPADDQ	%ZMM9,%ZMM16,%ZMM27

  (173) 0x42a95d VPADDQ	%ZMM9,%ZMM15,%ZMM28

  (173) 0x42a963 JMP	42a7c0

0x42a968 NOPW	%CS:(%RAX,%RAX,1)

0x42a977 NOPW	(%RAX,%RAX,1)

0x42a980 MOV	-0x30(%RBP),%RDI

0x42a984 JNE	42aa19

0x42a98a VMOVSD	-0x78(%RBP),%XMM0

0x42a98f MOV	(%RDI),%ESI

0x42a991 MOV	$0x53a5f0,%EDI

0x42a996 MOV	%R15,%RDX

0x42a999 CALL	404150 <__kmpc_atomic_float8_add@plt>

0x42a99e VMOVSD	-0x70(%RBP),%XMM0

0x42a9a3 MOV	-0x30(%RBP),%RAX

0x42a9a7 MOV	(%RAX),%ESI

0x42a9a9 MOV	$0x53a610,%EDI

0x42a9ae MOV	%R14,%RDX

0x42a9b1 CALL	404150 <__kmpc_atomic_float8_add@plt>

0x42a9b6 VMOVSD	-0x68(%RBP),%XMM0

0x42a9bb MOV	-0x30(%RBP),%RAX

0x42a9bf MOV	(%RAX),%ESI

0x42a9c1 MOV	$0x53a630,%EDI

0x42a9c6 MOV	%R13,%RDX

0x42a9c9 CALL	404150 <__kmpc_atomic_float8_add@plt>

0x42a9ce VMOVSD	-0x60(%RBP),%XMM0

0x42a9d3 MOV	-0x30(%RBP),%RAX

0x42a9d7 MOV	(%RAX),%ESI

0x42a9d9 MOV	$0x53a650,%EDI

0x42a9de MOV	%R12,%RDX

0x42a9e1 CALL	404150 <__kmpc_atomic_float8_add@plt>

0x42a9e6 VMOVSD	-0x58(%RBP),%XMM0

0x42a9eb MOV	-0x30(%RBP),%RAX

0x42a9ef MOV	(%RAX),%ESI

0x42a9f1 MOV	$0x53a670,%EDI

0x42a9f6 MOV	%RBX,%RDX

0x42a9f9 CALL	404150 <__kmpc_atomic_float8_add@plt>

0x42a9fe MOV	-0x30(%RBP),%RAX

0x42aa02 MOV	(%RAX),%ESI

0x42aa04 MOV	$0x593220,%RDX

0x42aa0b MOV	$0x53a6d0,%EDI

0x42aa10 CALL	404170 <__kmpc_end_reduce@plt>

0x42aa15 MOV	-0x30(%RBP),%RDI

0x42aa19 MOV	(%RDI),%ESI

0x42aa1b MOV	$0x53a6f0,%EDI

0x42aa20 CALL	4047c0 <__kmpc_barrier@plt>

0x42aa25 ADD	$0x98,%RSP

0x42aa2c POP	%RBX

0x42aa2d POP	%R12

0x42aa2f POP	%R13

0x42aa31 POP	%R14

0x42aa33 POP	%R15

0x42aa35 POP	%RBP

0x42aa36 RET

0x42aa37 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2

Source file and lines	field_summary_kernel.f90:54-74
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-74.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.33 to 9.67 cycles (3.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 34.33 to 25.85 cycles (1.33x speedup).

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

4% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
28% of SSE/AVX addition or subtraction instructions are used in vector version.
27% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_atomic_float8_add@plt: 5 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:57
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:60
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 348 bytes (43 double precision FP elements). The binary function is storing 172 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	194
nb uops	206
loop length	957
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	9
nb stack references	29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	34.33 cycles
front end	34.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.90	10.80	19.67	19.67	22.50	10.80	10.70	22.50	22.50	22.50	10.80	19.67
cycles	10.90	10.80	19.67	19.67	22.50	10.80	10.70	22.50	22.50	22.50	10.80	19.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	34.33
Dispatch	22.50
Overall L1	34.33

Vectorization ratios

INT

all	14%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	15%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	14%
load	4%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Vector efficiency ratios

INT

all	16%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	15%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.33 cycles. At this rate:

5% of peak load performance is reached (10.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.01 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 34.33 to 22.50 cycles (1.53x speedup).

ASM code

In the binary file, the address of the function is: 42a030

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x70(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,-0x4c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 42aa19 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9e9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x4c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x53a5b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x3c(%RBP),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x38(%RBP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R10D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 42a1c0 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM7,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM5,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x53a5d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x593220,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x78(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x53a690,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x429fe0,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x28,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4045b0 <__kmpc_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42a980 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x950>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 42aa19 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9e9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x78(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R15),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R14),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x68(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R13),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x60(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R12),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x58(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%RBX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x593220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x53a6b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 42aa10 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $-0x2,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R14D,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD $-0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R15D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %RDX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMOVGE %ECX,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RDX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPMOVSXBQ 0xcc147(%RIP),%ZMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPADDQ %ZMM2,%ZMM0,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %ZMM2,%ZMM0,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
MOV %RSI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffff8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %R14,%ZMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPBROADCASTQ 0xd15bf(%RIP),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPTERNLOGD $-0x1,%ZMM10,%ZMM10,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VBROADCASTSD 0xcc86e(%RIP),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0xcce9c(%RIP),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
LEA 0x2(%RAX,%RSI,1),%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10D,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 42a3d0 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x3a0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 42aa19 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9e9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x78(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a5f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a610,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x68(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a630,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x60(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a650,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x58(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a670,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x593220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x53a6d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404170 <__kmpc_end_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a6f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4047c0 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2

Source file and lines	field_summary_kernel.f90:54-74
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.33 to 9.67 cycles (3.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

4% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
28% of SSE/AVX addition or subtraction instructions are used in vector version.
27% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_atomic_float8_add@plt: 5 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:57
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:60
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:74

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 348 bytes (43 double precision FP elements). The binary function is storing 172 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	194
nb uops	206
loop length	957
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	9
nb stack references	29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	34.33 cycles
front end	34.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.90	10.80	19.67	19.67	22.50	10.80	10.70	22.50	22.50	22.50	10.80	19.67
cycles	10.90	10.80	19.67	19.67	22.50	10.80	10.70	22.50	22.50	22.50	10.80	19.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	34.33
Dispatch	22.50
Overall L1	34.33

Vectorization ratios

INT

all	14%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	15%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	14%
load	4%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Vector efficiency ratios

INT

all	16%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	15%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.33 cycles. At this rate:

5% of peak load performance is reached (10.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.01 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42a030

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x70(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,-0x4c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 42aa19 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9e9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x4c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x53a5b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x3c(%RBP),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x38(%RBP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R10D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 42a1c0 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM7,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM5,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x53a5d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x593220,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x78(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x53a690,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x429fe0,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x28,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4045b0 <__kmpc_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42a980 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x950>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 42aa19 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9e9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x78(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R15),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R14),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x68(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R13),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x60(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R12),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x58(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%RBX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x593220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x53a6b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 42aa10 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $-0x2,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R14D,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD $-0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R15D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %RDX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMOVGE %ECX,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RDX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPMOVSXBQ 0xcc147(%RIP),%ZMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPADDQ %ZMM2,%ZMM0,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %ZMM2,%ZMM0,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
MOV %RSI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7ffffff8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %R14,%ZMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPBROADCASTQ 0xd15bf(%RIP),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPTERNLOGD $-0x1,%ZMM10,%ZMM10,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VBROADCASTSD 0xcc86e(%RIP),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0xcce9c(%RIP),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
LEA 0x2(%RAX,%RSI,1),%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10D,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 42a3d0 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x3a0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 42aa19 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x9e9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x78(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a5f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a610,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x68(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a630,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x60(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a650,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x58(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a670,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x593220,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x53a6d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404170 <__kmpc_end_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53a6f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4047c0 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2–	0.29	0.11
▼Loop 169 - field_summary_kernel.f90:56-71 - exec–	0.00	0.00
▼Loop 172 - field_summary_kernel.f90:58-71 - exec–	0.19	0.07
○Loop 171 - field_summary_kernel.f90:62-63 - exec	0.10	0.04
○Loop 170 - field_summary_kernel.f90:62-63 - exec	0.01	0.01
▼Loop 173 - field_summary_kernel.f90:58-71 - exec–	0.00	0.00
○Loop 175 - field_summary_kernel.f90:62-63 - exec	0.00	0.00
○Loop 174 - field_summary_kernel.f90:62-63 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code