| Function: calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 | Coverage (incl. loops): 3.32% | (excl. loops): 0.00% |
|---|
| Function: calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 | Coverage (incl. loops): 3.32% | (excl. loops): 0.00% |
|---|
/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 133 |
-------------------------------------------------------------------------------- |
89: !$OMP PARALLEL |
90: |
91: !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val) |
92: DO k=y_min,y_max |
93: !$OMP SIMD |
94: DO j=x_min,x_max |
95: |
96: dsx=celldx(j) |
97: dsy=celldy(k) |
98: |
99: cc=soundspeed(j,k)*soundspeed(j,k) |
100: cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k) |
101: cc=MAX(SQRT(cc),g_small) |
102: |
103: dtct=dtc_safe*MIN(dsx,dsy)/cc |
104: |
105: div=0.0 |
106: |
107: dv1=(xvel0(j ,k)+xvel0(j ,k+1))*xarea(j ,k) |
108: dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k) |
109: |
110: div=div+dv2-dv1 |
111: |
112: dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
113: |
114: dv1=(yvel0(j,k )+yvel0(j+1,k ))*yarea(j,k ) |
115: dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1) |
116: |
117: div=div+dv2-dv1 |
118: |
119: dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
120: |
121: div=div/(2.0_8*volume(j,k)) |
122: |
123: IF(div.LT.-g_small)THEN |
124: dtdivt=dtdiv_safe*(-1.0_8/div) |
125: ELSE |
126: dtdivt=g_big |
127: ENDIF |
128: |
129: dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt) |
130: |
131: ENDDO |
132: ENDDO |
133: !$OMP END DO |
0x4270b0 PUSH %RBP |
0x4270b1 MOV %RSP,%RBP |
0x4270b4 PUSH %R15 |
0x4270b6 PUSH %R14 |
0x4270b8 PUSH %R13 |
0x4270ba PUSH %R12 |
0x4270bc PUSH %RBX |
0x4270bd AND $-0x40,%RSP |
0x4270c1 SUB $0x280,%RSP |
0x4270c8 MOV 0xa0(%RBP),%R14D |
0x4270cf MOV 0x98(%RBP),%EAX |
0x4270d5 SUB %R14D,%EAX |
0x4270d8 MOVL $0,0x4c(%RSP) |
0x4270e0 JS 4271df |
0x4270e6 MOV %RCX,%R15 |
0x4270e9 MOV %R9,%RBX |
0x4270ec MOV %RDI,0x60(%RSP) |
0x4270f1 MOV (%RDI),%ESI |
0x4270f3 MOVL $0,0x1c(%RSP) |
0x4270fb MOV %EAX,0x18(%RSP) |
0x4270ff MOVL $0x1,0x48(%RSP) |
0x427107 SUB $0x8,%RSP |
0x42710b LEA 0x50(%RSP),%RAX |
0x427110 LEA 0x54(%RSP),%RCX |
0x427115 LEA 0x24(%RSP),%R8 |
0x42711a LEA 0x20(%RSP),%R9 |
0x42711f MOV $0x53a3d0,%EDI |
0x427124 MOV %ESI,0x40(%RSP) |
0x427128 MOV $0x22,%EDX |
0x42712d PUSH $0x1 |
0x42712f PUSH $0x1 |
0x427131 PUSH %RAX |
0x427132 CALL 404850 <__kmpc_for_static_init_4@plt> |
0x427137 ADD $0x20,%RSP |
0x42713b MOV 0x1c(%RSP),%ESI |
0x42713f MOV 0x18(%RSP),%EAX |
0x427143 SUB %ESI,%EAX |
0x427145 MOV %EAX,0x40(%RSP) |
0x427149 JAE 427200 |
0x42714f VMOVSD 0xd3c01(%RIP),%XMM13 |
0x427157 VMOVSD %XMM13,0x88(%RSP) |
0x427160 MOV $0x53a3f0,%EDI |
0x427165 MOV 0x38(%RSP),%ESI |
0x427169 VZEROUPPER |
0x42716c CALL 404070 <__kmpc_for_static_fini@plt> |
0x427171 MOV 0x60(%RSP),%RBX |
0x427176 MOV (%RBX),%ESI |
0x427178 SUB $0x8,%RSP |
0x42717c MOV $0x593220,%RAX |
0x427183 LEA 0x90(%RSP),%R8 |
0x42718b MOV $0x53a410,%EDI |
0x427190 MOV $0x4270a0,%R9D |
0x427196 MOV $0x1,%EDX |
0x42719b MOV $0x8,%ECX |
0x4271a0 PUSH %RAX |
0x4271a1 CALL 4045b0 <__kmpc_reduce@plt> |
0x4271a6 MOV %RBX,%RDI |
0x4271a9 ADD $0x10,%RSP |
0x4271ad CMP $0x1,%EAX |
0x4271b0 JNE 4271df |
0x4271b2 MOV 0x10(%RBP),%RAX |
0x4271b6 VMOVSD 0x88(%RSP),%XMM0 |
0x4271bf VMINSD (%RAX),%XMM0,%XMM0 |
0x4271c3 VMOVSD %XMM0,(%RAX) |
0x4271c7 MOV (%RDI),%ESI |
0x4271c9 MOV $0x593220,%RDX |
0x4271d0 MOV $0x53a430,%EDI |
0x4271d5 CALL 404170 <__kmpc_end_reduce@plt> |
0x4271da MOV 0x60(%RSP),%RDI |
0x4271df MOV (%RDI),%ESI |
0x4271e1 MOV $0x53a450,%EDI |
0x4271e6 CALL 4047c0 <__kmpc_barrier@plt> |
0x4271eb LEA -0x28(%RBP),%RSP |
0x4271ef POP %RBX |
0x4271f0 POP %R12 |
0x4271f2 POP %R13 |
0x4271f4 POP %R14 |
0x4271f6 POP %R15 |
0x4271f8 POP %RBP |
0x4271f9 RET |
0x4271fa NOPW (%RAX,%RAX,1) |
0x427200 MOV 0xb0(%RBP),%RAX |
0x427207 MOV 0xa8(%RBP),%RCX |
0x42720e MOVSXD (%RAX),%RDI |
0x427211 MOV (%RCX),%ECX |
0x427213 SUB %EDI,%ECX |
0x427215 ADD %R14D,%ESI |
0x427218 LEA -0x2(%R15),%EAX |
0x42721c CLTQ |
0x42721e MOV %RAX,0x198(%RSP) |
0x427226 MOV %RCX,0x1a8(%RSP) |
0x42722e LEA 0x1(%RCX),%EAX |
0x427231 CMP $0x2,%EAX |
0x427234 MOV $0x1,%ECX |
0x427239 MOV %EAX,0x3c(%RSP) |
0x42723d CMOVGE %EAX,%ECX |
0x427240 MOV %ECX,%EAX |
0x427242 AND $0x7ffffff0,%EAX |
0x427247 MOV %RAX,0x190(%RSP) |
0x42724f MOV %RCX,0x80(%RSP) |
0x427257 VMOVQ %RCX,%XMM0 |
0x42725c VMOVAPD %ZMM0,0x200(%RSP) |
0x427264 MOVSXD %EBX,%RDX |
0x427267 MOVSXD %R15D,%RCX |
0x42726a MOV %RDI,0x78(%RSP) |
0x42726f LEA (,%RDI,8),%RAX |
0x427277 LEA -0x2(%RDX),%RDI |
0x42727b MOV %RDI,0x70(%RSP) |
0x427280 SAL $0x3,%RDX |
0x427284 SUB %RDX,%RAX |
0x427287 MOV $0x3,%EDI |
0x42728c SUB %RCX,%RDI |
0x42728f MOV %RDI,0x188(%RSP) |
0x427297 MOV $0x18,%EDI |
0x42729c SUB %RDX,%RDI |
0x42729f MOV $0x10,%R8D |
0x4272a5 SUB %RDX,%R8 |
0x4272a8 MOV $0x2,%EDX |
0x4272ad SUB %RCX,%RDX |
0x4272b0 MOV %RDX,0x180(%RSP) |
0x4272b8 ADD $-0x2,%RCX |
0x4272bc MOV %RCX,0x68(%RSP) |
0x4272c1 MOV 0x60(%RBP),%RCX |
0x4272c5 MOV 0x58(%RBP),%RDX |
0x4272c9 MOV 0x50(%RBP),%R9 |
0x4272cd MOV 0x40(%RBP),%R10 |
0x4272d1 MOV 0x38(%RBP),%R11 |
0x4272d5 MOV 0x30(%RBP),%RBX |
0x4272d9 MOV 0x28(%RBP),%R14 |
0x4272dd MOV 0x20(%RBP),%R15 |
0x4272e1 MOV 0x18(%RBP),%R12 |
0x4272e5 LEA 0x18(%R12,%RAX,1),%R13 |
0x4272ea MOV %R13,0xf8(%RSP) |
0x4272f2 LEA 0x18(%RCX,%RAX,1),%R13 |
0x4272f7 MOV %R13,0xf0(%RSP) |
0x4272ff LEA 0x18(%R15,%RAX,1),%R13 |
0x427304 MOV %R13,0xe8(%RSP) |
0x42730c LEA 0x10(%RDX,%RAX,1),%R13 |
0x427311 MOV %R13,0xe0(%RSP) |
0x427319 LEA 0x10(%R10,%RAX,1),%R13 |
0x42731e MOV %R13,0xd8(%RSP) |
0x427326 LEA 0x10(%R11,%RAX,1),%R13 |
0x42732b MOV %R13,0xd0(%RSP) |
0x427333 LEA 0x10(%RBX,%RAX,1),%R13 |
0x427338 MOV %R13,0xc8(%RSP) |
0x427340 LEA 0x10(%R14,%RAX,1),%R13 |
0x427345 MOV %R13,0xc0(%RSP) |
0x42734d LEA 0x10(%R9,%RAX,1),%RAX |
0x427352 MOV %RAX,0x1b8(%RSP) |
0x42735a LEA (%R12,%RDI,1),%RAX |
0x42735e MOV %RAX,0x168(%RSP) |
0x427366 LEA (%RCX,%RDI,1),%RAX |
0x42736a MOV %RAX,0x160(%RSP) |
0x427372 ADD %R15,%RDI |
0x427375 MOV %RDI,0x178(%RSP) |
0x42737d LEA (%RDX,%R8,1),%RAX |
0x427381 MOV %RAX,0x158(%RSP) |
0x427389 LEA (%R10,%R8,1),%RAX |
0x42738d MOV %RAX,0x150(%RSP) |
0x427395 LEA (%R11,%R8,1),%RAX |
0x427399 MOV %RAX,0x148(%RSP) |
0x4273a1 LEA (%RBX,%R8,1),%RAX |
0x4273a5 MOV %RAX,0x140(%RSP) |
0x4273ad LEA (%R14,%R8,1),%RAX |
0x4273b1 MOV %RAX,0x138(%RSP) |
0x4273b9 ADD %R9,%R8 |
0x4273bc MOV %R8,0x170(%RSP) |
0x4273c4 VMOVSD 0xd398c(%RIP),%XMM13 |
0x4273cc VMOVDDUP 0xd1004(%RIP),%XMM10 |
0x4273d4 VBROADCASTSD 0xced72(%RIP),%ZMM5 |
0x4273de XOR %EDX,%EDX |
0x4273e0 MOV %RSI,0x1a0(%RSP) |
0x4273e8 MOV %ESI,%ECX |
0x4273ea JMP 4274ed |
0x4273ef NOPW %CS:(%RAX,%RAX,1) |
0x4273fe XCHG %AX,%AX |
(159) 0x427400 VPXOR %XMM0,%XMM0,%XMM0 |
(159) 0x427404 VXORPD %XMM2,%XMM2,%XMM2 |
(159) 0x427408 VBLENDMPD %ZMM0,%ZMM13,%ZMM0{%K2} |
(159) 0x42740e VMOVAPD %ZMM2,%ZMM13{%K1} |
(159) 0x427414 VMINPD %ZMM0,%ZMM13,%ZMM1 |
(159) 0x42741a VCMPPD $0x3,%ZMM0,%ZMM0,%K1 |
(159) 0x427421 VMOVAPD %ZMM13,%ZMM1{%K1} |
(159) 0x427427 VMOVAPD %YMM1,%YMM0 |
(159) 0x42742b VEXTRACTF32X4 $0x2,%ZMM1,%XMM2 |
(159) 0x427432 VEXTRACTF32X4 $0x3,%ZMM1,%XMM3 |
(159) 0x427439 VSHUFPD $0x1,%XMM1,%XMM1,%XMM4 |
(159) 0x42743e VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(159) 0x427445 VMINSD %XMM1,%XMM4,%XMM1 |
(159) 0x427449 VMOVSD %XMM4,%XMM1,%XMM1{%K1} |
(159) 0x42744f VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(159) 0x427456 VEXTRACTF128 $0x1,%YMM0,%XMM0 |
(159) 0x42745c VMINSD %XMM1,%XMM0,%XMM1 |
(159) 0x427460 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(159) 0x427466 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(159) 0x42746d VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(159) 0x427472 VMINSD %XMM1,%XMM0,%XMM1 |
(159) 0x427476 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(159) 0x42747c VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(159) 0x427483 VMINSD %XMM1,%XMM2,%XMM0 |
(159) 0x427487 VMOVSD %XMM2,%XMM0,%XMM0{%K1} |
(159) 0x42748d VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x427494 VSHUFPD $0x1,%XMM2,%XMM2,%XMM1 |
(159) 0x427499 VMINSD %XMM0,%XMM1,%XMM0 |
(159) 0x42749d VMOVSD %XMM1,%XMM0,%XMM0{%K1} |
(159) 0x4274a3 VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x4274aa VMINSD %XMM0,%XMM3,%XMM0 |
(159) 0x4274ae VMOVSD %XMM3,%XMM0,%XMM0{%K1} |
(159) 0x4274b4 VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x4274bb VSHUFPD $0x1,%XMM3,%XMM3,%XMM1 |
(159) 0x4274c0 VMINSD %XMM0,%XMM1,%XMM13 |
(159) 0x4274c4 VMOVSD %XMM1,%XMM13,%XMM13{%K1} |
(159) 0x4274ca NOPW (%RAX,%RAX,1) |
(159) 0x4274d0 MOV 0x1b0(%RSP),%RDX |
(159) 0x4274d8 LEA 0x1(%RDX),%EAX |
(159) 0x4274db MOV 0x44(%RSP),%ECX |
(159) 0x4274df INC %ECX |
(159) 0x4274e1 CMP 0x40(%RSP),%EDX |
(159) 0x4274e5 MOV %EAX,%EDX |
(159) 0x4274e7 JE 427157 |
(159) 0x4274ed CMPL $0,0x1a8(%RSP) |
(159) 0x4274f5 MOV %ECX,0x44(%RSP) |
(159) 0x4274f9 MOV %RDX,0x1b0(%RSP) |
(159) 0x427501 JS 4274d0 |
(159) 0x427503 MOVSXD %ECX,%R11 |
(159) 0x427506 MOV 0x188(%RSP),%RAX |
(159) 0x42750e LEA (%RAX,%R11,1),%R8 |
(159) 0x427512 ADD 0x180(%RSP),%R11 |
(159) 0x42751a MOV 0x1a0(%RSP),%RAX |
(159) 0x427522 ADD %EDX,%EAX |
(159) 0x427524 MOVSXD %EAX,%RDI |
(159) 0x427527 MOV %RDI,%RAX |
(159) 0x42752a SUB 0x198(%RSP),%RAX |
(159) 0x427532 MOV 0x48(%RBP),%RCX |
(159) 0x427536 VMOVSD (%RCX,%RAX,8),%XMM20 |
(159) 0x42753d MOV 0xb8(%RBP),%RAX |
(159) 0x427544 MOV (%RAX),%R13 |
(159) 0x427547 MOV 0xc0(%RBP),%RAX |
(159) 0x42754e MOV (%RAX),%RCX |
(159) 0x427551 MOV 0xc8(%RBP),%RAX |
(159) 0x427558 MOV (%RAX),%R9 |
(159) 0x42755b MOV 0x90(%RBP),%RAX |
(159) 0x427562 VMOVSD (%RAX),%XMM11 |
(159) 0x427566 MOV 0x80(%RBP),%RAX |
(159) 0x42756d VMOVSD (%RAX),%XMM22 |
(159) 0x427573 MOV 0xd0(%RBP),%RAX |
(159) 0x42757a MOV (%RAX),%RAX |
(159) 0x42757d MOV %RAX,0x30(%RSP) |
(159) 0x427582 MOV 0xd8(%RBP),%RAX |
(159) 0x427589 MOV (%RAX),%RSI |
(159) 0x42758c MOV 0x78(%RBP),%RAX |
(159) 0x427590 VMOVSD (%RAX),%XMM21 |
(159) 0x427596 MOV 0xe0(%RBP),%RAX |
(159) 0x42759d MOV (%RAX),%R15 |
(159) 0x4275a0 MOV 0xe8(%RBP),%RAX |
(159) 0x4275a7 MOV (%RAX),%R12 |
(159) 0x4275aa MOV 0xf0(%RBP),%RAX |
(159) 0x4275b1 MOV (%RAX),%R14 |
(159) 0x4275b4 MOV 0x70(%RBP),%RAX |
(159) 0x4275b8 VMOVSD (%RAX),%XMM19 |
(159) 0x4275be VXORPD %XMM10,%XMM11,%XMM12 |
(159) 0x4275c3 MOV 0x190(%RSP),%RBX |
(159) 0x4275cb TEST %RBX,%RBX |
(159) 0x4275ce JE 427600 |
(159) 0x4275d0 MOV %RCX,0x1c0(%RSP) |
(159) 0x4275d8 MOV %R13,0x20(%RSP) |
(159) 0x4275dd CMPL $0x4,0x3c(%RSP) |
(159) 0x4275e2 MOV %R9,0x28(%RSP) |
(159) 0x4275e7 JG 427640 |
(159) 0x4275e9 MOV %R11,%R9 |
(159) 0x4275ec MOV %R8,%R11 |
(159) 0x4275ef MOV %RSI,%RBX |
(159) 0x4275f2 XOR %R10D,%R10D |
(159) 0x4275f5 JMP 427c35 |
0x4275fa NOPW (%RAX,%RAX,1) |
(159) 0x427600 XOR %R10D,%R10D |
(159) 0x427603 JMP 427bf8 |
0x427608 NOPW %CS:(%RAX,%RAX,1) |
0x427617 NOPW %CS:(%RAX,%RAX,1) |
0x427626 NOPW %CS:(%RAX,%RAX,1) |
0x427635 NOPW %CS:(%RAX,%RAX,1) |
(159) 0x427640 MOV %RDI,0x130(%RSP) |
(159) 0x427648 VBROADCASTSD %XMM13,%ZMM13 |
(159) 0x42764e VBROADCASTSD %XMM11,%ZMM14 |
(159) 0x427654 VMOVAPD %XMM20,0xb0(%RSP) |
(159) 0x42765c VBROADCASTSD %XMM20,%ZMM15 |
(159) 0x427662 VMOVAPD %XMM22,0x90(%RSP) |
(159) 0x42766a VBROADCASTSD %XMM22,%ZMM16 |
(159) 0x427670 VMOVAPD %XMM21,0xa0(%RSP) |
(159) 0x427678 VBROADCASTSD %XMM21,%ZMM17 |
(159) 0x42767e VMOVAPD %XMM19,0x50(%RSP) |
(159) 0x427686 VBROADCASTSD %XMM19,%ZMM18 |
(159) 0x42768c VBROADCASTSD %XMM12,%ZMM19 |
(159) 0x427692 MOV %R12,%R10 |
(159) 0x427695 IMUL %R8,%R10 |
(159) 0x427699 MOV 0xf8(%RSP),%RAX |
(159) 0x4276a1 ADD %RAX,%R10 |
(159) 0x4276a4 MOV %R12,0x120(%RSP) |
(159) 0x4276ac IMUL %R11,%R12 |
(159) 0x4276b0 ADD %RAX,%R12 |
(159) 0x4276b3 MOV %RSI,0x110(%RSP) |
(159) 0x4276bb MOV %RSI,%RCX |
(159) 0x4276be IMUL %R11,%RCX |
(159) 0x4276c2 ADD 0xf0(%RSP),%RCX |
(159) 0x4276ca MOV %R15,%R13 |
(159) 0x4276cd MOV 0x30(%RSP),%RAX |
(159) 0x4276d2 MOV %RAX,%R15 |
(159) 0x4276d5 IMUL %R11,%R15 |
(159) 0x4276d9 MOV 0xe8(%RSP),%RDX |
(159) 0x4276e1 ADD %RDX,%R15 |
(159) 0x4276e4 IMUL %R8,%RAX |
(159) 0x4276e8 ADD %RDX,%RAX |
(159) 0x4276eb MOV %R14,%RDI |
(159) 0x4276ee MOV %R8,0x108(%RSP) |
(159) 0x4276f6 IMUL %R8,%RDI |
(159) 0x4276fa MOV 0xe0(%RSP),%RDX |
(159) 0x427702 ADD %RDX,%RDI |
(159) 0x427705 MOV %R14,0x128(%RSP) |
(159) 0x42770d IMUL %R11,%R14 |
(159) 0x427711 ADD %RDX,%R14 |
(159) 0x427714 MOV %R13,0x118(%RSP) |
(159) 0x42771c IMUL %R11,%R13 |
(159) 0x427720 ADD 0xd8(%RSP),%R13 |
(159) 0x427728 MOV %R9,%RSI |
(159) 0x42772b IMUL %R11,%RSI |
(159) 0x42772f ADD 0xd0(%RSP),%RSI |
(159) 0x427737 MOV 0x1c0(%RSP),%RDX |
(159) 0x42773f IMUL %R11,%RDX |
(159) 0x427743 ADD 0xc8(%RSP),%RDX |
(159) 0x42774b MOV 0x20(%RSP),%R9 |
(159) 0x427750 MOV %R11,0x100(%RSP) |
(159) 0x427758 IMUL %R11,%R9 |
(159) 0x42775c ADD 0xc0(%RSP),%R9 |
(159) 0x427764 XOR %R11D,%R11D |
(159) 0x427767 VMOVAPD %ZMM13,%ZMM20 |
(159) 0x42776d JMP 427923 |
0x427772 NOPW %CS:(%RAX,%RAX,1) |
(161) 0x427780 VBROADCASTSD 0xd0c4e(%RIP),%ZMM1 |
(161) 0x42778a MOV 0x68(%RBP),%R8 |
(161) 0x42778e VXORPD (%R8){1to8},%ZMM1,%ZMM6 |
(161) 0x427794 VDIVPD %ZMM0,%ZMM6,%ZMM0 |
(161) 0x42779a VDIVPD %ZMM4,%ZMM6,%ZMM4 |
(161) 0x4277a0 MOV 0x1b8(%RSP),%R8 |
(161) 0x4277a8 VMOVUPD (%R8,%R11,8),%ZMM6 |
(161) 0x4277af VMOVUPD 0x40(%R8,%R11,8),%ZMM1 |
(161) 0x4277b7 VMOVUPD (%R9,%R11,8),%ZMM7 |
(161) 0x4277be VMOVUPD 0x40(%R9,%R11,8),%ZMM8 |
(161) 0x4277c6 VMOVUPD (%RDX,%R11,8),%ZMM9 |
(161) 0x4277cd VMOVUPD 0x40(%RDX,%R11,8),%ZMM10 |
(161) 0x4277d5 VADDPD %ZMM9,%ZMM9,%ZMM9 |
(161) 0x4277db VADDPD %ZMM10,%ZMM10,%ZMM10 |
(161) 0x4277e1 VDIVPD 0x40(%RSI,%R11,8),%ZMM10,%ZMM10 |
(161) 0x4277e9 VDIVPD (%RSI,%R11,8),%ZMM9,%ZMM9 |
(161) 0x4277f0 VFMADD231PD %ZMM7,%ZMM7,%ZMM9 |
(161) 0x4277f6 VFMADD231PD %ZMM8,%ZMM8,%ZMM10 |
(161) 0x4277fc VSQRTPD %ZMM10,%ZMM7 |
(161) 0x427802 VSQRTPD %ZMM9,%ZMM8 |
(161) 0x427808 VMAXPD %ZMM14,%ZMM8,%ZMM8 |
(161) 0x42780e VMINPD %ZMM15,%ZMM6,%ZMM6 |
(161) 0x427814 VMULPD %ZMM6,%ZMM16,%ZMM6 |
(161) 0x42781a VDIVPD %ZMM8,%ZMM6,%ZMM6 |
(161) 0x427820 VMAXPD %ZMM14,%ZMM7,%ZMM7 |
(161) 0x427826 VMINPD %ZMM15,%ZMM1,%ZMM1 |
(161) 0x42782c VMULPD %ZMM1,%ZMM16,%ZMM1 |
(161) 0x427832 VDIVPD %ZMM7,%ZMM1,%ZMM1 |
(161) 0x427838 VMULPD %ZMM17,%ZMM22,%ZMM7 |
(161) 0x42783e VMULPD %ZMM17,%ZMM21,%ZMM8 |
(161) 0x427844 VANDPD %ZMM5,%ZMM27,%ZMM9 |
(161) 0x42784a VANDPD %ZMM5,%ZMM24,%ZMM10 |
(161) 0x427850 VANDPD %ZMM5,%ZMM31,%ZMM24 |
(161) 0x427856 VANDPD %ZMM5,%ZMM28,%ZMM27 |
(161) 0x42785c VMULPD %ZMM14,%ZMM29,%ZMM28 |
(161) 0x427862 VMAXPD %ZMM28,%ZMM27,%ZMM27 |
(161) 0x427868 VMAXPD %ZMM27,%ZMM9,%ZMM9 |
(161) 0x42786e VDIVPD %ZMM9,%ZMM8,%ZMM8 |
(161) 0x427874 VMULPD %ZMM14,%ZMM23,%ZMM9 |
(161) 0x42787a VMAXPD %ZMM9,%ZMM24,%ZMM23 |
(161) 0x427880 VMAXPD %ZMM23,%ZMM10,%ZMM10 |
(161) 0x427886 VDIVPD %ZMM10,%ZMM7,%ZMM7 |
(161) 0x42788c VMULPD %ZMM18,%ZMM22,%ZMM10 |
(161) 0x427892 VMULPD %ZMM18,%ZMM21,%ZMM21 |
(161) 0x427898 VANDPD %ZMM5,%ZMM25,%ZMM22 |
(161) 0x42789e VANDPD %ZMM5,%ZMM26,%ZMM23 |
(161) 0x4278a4 VANDPD %ZMM5,%ZMM2,%ZMM2 |
(161) 0x4278aa VANDPD %ZMM5,%ZMM30,%ZMM24 |
(161) 0x4278b0 VMAXPD %ZMM28,%ZMM24,%ZMM24 |
(161) 0x4278b6 VMAXPD %ZMM24,%ZMM22,%ZMM22 |
(161) 0x4278bc VDIVPD %ZMM22,%ZMM21,%ZMM21 |
(161) 0x4278c2 VMAXPD %ZMM9,%ZMM2,%ZMM2 |
(161) 0x4278c8 VMAXPD %ZMM2,%ZMM23,%ZMM2 |
(161) 0x4278ce VDIVPD %ZMM2,%ZMM10,%ZMM2 |
(161) 0x4278d4 VBROADCASTSD %XMM3,%ZMM3 |
(161) 0x4278da VBLENDMPD %ZMM0,%ZMM3,%ZMM0{%K2} |
(161) 0x4278e0 VMINPD %ZMM0,%ZMM21,%ZMM0 |
(161) 0x4278e6 VMINPD %ZMM0,%ZMM8,%ZMM0 |
(161) 0x4278ec VMINPD %ZMM0,%ZMM1,%ZMM0 |
(161) 0x4278f2 VMINPD %ZMM0,%ZMM20,%ZMM20 |
(161) 0x4278f8 VMOVAPD %ZMM4,%ZMM3{%K1} |
(161) 0x4278fe VMINPD %ZMM3,%ZMM2,%ZMM0 |
(161) 0x427904 VMINPD %ZMM0,%ZMM7,%ZMM0 |
(161) 0x42790a VMINPD %ZMM0,%ZMM6,%ZMM0 |
(161) 0x427910 VMINPD %ZMM0,%ZMM13,%ZMM13 |
(161) 0x427916 ADD $0x10,%R11 |
(161) 0x42791a CMP %RBX,%R11 |
(161) 0x42791d JAE 427ac0 |
(161) 0x427923 VMOVUPD -0x8(%RAX,%R11,8),%ZMM0 |
(161) 0x42792e VMOVUPD (%RAX,%R11,8),%ZMM2 |
(161) 0x427935 VMOVUPD 0x38(%RAX,%R11,8),%ZMM3 |
(161) 0x427940 VMOVUPD 0x40(%RAX,%R11,8),%ZMM4 |
(161) 0x427948 VADDPD 0x38(%R15,%R11,8),%ZMM3,%ZMM3 |
(161) 0x427953 VADDPD -0x8(%R15,%R11,8),%ZMM0,%ZMM0 |
(161) 0x42795e VMULPD -0x8(%RCX,%R11,8),%ZMM0,%ZMM24 |
(161) 0x427969 VMULPD 0x38(%RCX,%R11,8),%ZMM3,%ZMM27 |
(161) 0x427974 VADDPD (%R15,%R11,8),%ZMM2,%ZMM0 |
(161) 0x42797b VADDPD 0x40(%R15,%R11,8),%ZMM4,%ZMM2 |
(161) 0x427983 VMULPD 0x40(%RCX,%R11,8),%ZMM2,%ZMM28 |
(161) 0x42798b VMULPD (%RCX,%R11,8),%ZMM0,%ZMM31 |
(161) 0x427992 VMOVUPD (%R13,%R11,8),%ZMM23 |
(161) 0x42799a VMOVUPD 0x40(%R13,%R11,8),%ZMM29 |
(161) 0x4279a2 VADDPD %ZMM29,%ZMM29,%ZMM21 |
(161) 0x4279a8 VADDPD %ZMM23,%ZMM23,%ZMM22 |
(161) 0x4279ae VMOVUPD (%R12,%R11,8),%ZMM0 |
(161) 0x4279b5 VMOVUPD 0x40(%R12,%R11,8),%ZMM2 |
(161) 0x4279bd VADDPD -0x8(%R12,%R11,8),%ZMM0,%ZMM0 |
(161) 0x4279c8 VADDPD 0x38(%R12,%R11,8),%ZMM2,%ZMM2 |
(161) 0x4279d3 VMULPD 0x40(%R14,%R11,8),%ZMM2,%ZMM25 |
(161) 0x4279db VMULPD (%R14,%R11,8),%ZMM0,%ZMM26 |
(161) 0x4279e2 VMOVUPD (%R10,%R11,8),%ZMM0 |
(161) 0x4279e9 VMOVUPD 0x40(%R10,%R11,8),%ZMM2 |
(161) 0x4279f1 VADDPD -0x8(%R10,%R11,8),%ZMM0,%ZMM0 |
(161) 0x4279fc VADDPD 0x38(%R10,%R11,8),%ZMM2,%ZMM2 |
(161) 0x427a07 VMULPD 0x40(%RDI,%R11,8),%ZMM2,%ZMM30 |
(161) 0x427a0f VMULPD (%RDI,%R11,8),%ZMM0,%ZMM2 |
(161) 0x427a16 VADDPD %ZMM26,%ZMM24,%ZMM0 |
(161) 0x427a1c VADDPD %ZMM25,%ZMM27,%ZMM3 |
(161) 0x427a22 VSUBPD %ZMM3,%ZMM28,%ZMM3 |
(161) 0x427a28 VSUBPD %ZMM0,%ZMM31,%ZMM0 |
(161) 0x427a2e VADDPD %ZMM2,%ZMM0,%ZMM4 |
(161) 0x427a34 VADDPD %ZMM30,%ZMM3,%ZMM0 |
(161) 0x427a3a VDIVPD %ZMM21,%ZMM0,%ZMM0 |
(161) 0x427a40 VDIVPD %ZMM22,%ZMM4,%ZMM4 |
(161) 0x427a46 VCMPPD $0x1,%ZMM19,%ZMM4,%K1 |
(161) 0x427a4d VCMPPD $0x1,%ZMM19,%ZMM0,%K2 |
(161) 0x427a54 KUNPCKBW %K1,%K2,%K0 |
(161) 0x427a58 KORTESTW %K0,%K0 |
(161) 0x427a5c JB 427a6a |
(161) 0x427a5e MOV 0x88(%RBP),%R8 |
(161) 0x427a65 VMOVSD (%R8),%XMM3 |
(161) 0x427a6a KORTESTB %K2,%K1 |
(161) 0x427a6e JNE 427780 |
(161) 0x427a74 VXORPD %XMM4,%XMM4,%XMM4 |
(161) 0x427a78 VXORPD %XMM0,%XMM0,%XMM0 |
(161) 0x427a7c JMP 4277a0 |
0x427a81 NOPW %CS:(%RAX,%RAX,1) |
0x427a90 NOPW %CS:(%RAX,%RAX,1) |
0x427a9f NOPW %CS:(%RAX,%RAX,1) |
0x427aae NOPW %CS:(%RAX,%RAX,1) |
0x427abd NOPL (%RAX) |
(159) 0x427ac0 VMINPD %ZMM13,%ZMM20,%ZMM0 |
(159) 0x427ac6 VCMPPD $0x3,%ZMM13,%ZMM13,%K1 |
(159) 0x427acd VMOVAPD %ZMM20,%ZMM0{%K1} |
(159) 0x427ad3 VMOVAPD %YMM0,%YMM1 |
(159) 0x427ad7 VEXTRACTF32X4 $0x2,%ZMM0,%XMM2 |
(159) 0x427ade VEXTRACTF32X4 $0x3,%ZMM0,%XMM3 |
(159) 0x427ae5 VSHUFPD $0x1,%XMM0,%XMM0,%XMM4 |
(159) 0x427aea VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x427af1 VMINSD %XMM0,%XMM4,%XMM0 |
(159) 0x427af5 VMOVSD %XMM4,%XMM0,%XMM0{%K1} |
(159) 0x427afb VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x427b02 VEXTRACTF128 $0x1,%YMM1,%XMM1 |
(159) 0x427b08 VMINSD %XMM0,%XMM1,%XMM0 |
(159) 0x427b0c VMOVSD %XMM1,%XMM0,%XMM0{%K1} |
(159) 0x427b12 VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x427b19 VSHUFPD $0x1,%XMM1,%XMM1,%XMM1 |
(159) 0x427b1e VMINSD %XMM0,%XMM1,%XMM0 |
(159) 0x427b22 VMOVSD %XMM1,%XMM0,%XMM0{%K1} |
(159) 0x427b28 VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x427b2f VMINSD %XMM0,%XMM2,%XMM0 |
(159) 0x427b33 VMOVSD %XMM2,%XMM0,%XMM0{%K1} |
(159) 0x427b39 VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x427b40 VSHUFPD $0x1,%XMM2,%XMM2,%XMM1 |
(159) 0x427b45 VMINSD %XMM0,%XMM1,%XMM0 |
(159) 0x427b49 VMOVSD %XMM1,%XMM0,%XMM0{%K1} |
(159) 0x427b4f VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x427b56 VMINSD %XMM0,%XMM3,%XMM0 |
(159) 0x427b5a VMOVSD %XMM3,%XMM0,%XMM0{%K1} |
(159) 0x427b60 VCMPSD $0x3,%XMM0,%XMM0,%K1 |
(159) 0x427b67 VSHUFPD $0x1,%XMM3,%XMM3,%XMM1 |
(159) 0x427b6c VMINSD %XMM0,%XMM1,%XMM13 |
(159) 0x427b70 VMOVSD %XMM1,%XMM13,%XMM13{%K1} |
(159) 0x427b76 MOV %RBX,%R10 |
(159) 0x427b79 CMP 0x80(%RSP),%EBX |
(159) 0x427b80 VMOVDDUP 0xd0850(%RIP),%XMM10 |
(159) 0x427b88 VMOVAPD 0x50(%RSP),%XMM19 |
(159) 0x427b90 VMOVAPD 0xb0(%RSP),%XMM20 |
(159) 0x427b98 VMOVAPD 0xa0(%RSP),%XMM21 |
(159) 0x427ba0 VMOVAPD 0x90(%RSP),%XMM22 |
(159) 0x427ba8 MOV 0x28(%RSP),%R9 |
(159) 0x427bad MOV 0x1c0(%RSP),%RCX |
(159) 0x427bb5 MOV 0x20(%RSP),%R13 |
(159) 0x427bba MOV 0x130(%RSP),%RDI |
(159) 0x427bc2 MOV 0x128(%RSP),%R14 |
(159) 0x427bca MOV 0x120(%RSP),%R12 |
(159) 0x427bd2 MOV 0x118(%RSP),%R15 |
(159) 0x427bda MOV 0x110(%RSP),%RSI |
(159) 0x427be2 MOV 0x108(%RSP),%R8 |
(159) 0x427bea MOV 0x100(%RSP),%R11 |
(159) 0x427bf2 JE 4274d0 |
(159) 0x427bf8 VMOVD %R10D,%XMM0 |
(159) 0x427bfd VMOVDQA64 0x200(%RSP),%ZMM1 |
(159) 0x427c05 VPSUBQ %ZMM0,%ZMM1,%ZMM0 |
(159) 0x427c0b VMOVQ %XMM0,%RAX |
(159) 0x427c10 CMP $0x5,%RAX |
(159) 0x427c14 JAE 427f00 |
(159) 0x427c1a MOV %RCX,0x1c0(%RSP) |
(159) 0x427c22 MOV %R13,0x20(%RSP) |
(159) 0x427c27 MOV %R9,0x28(%RSP) |
(159) 0x427c2c MOV %R11,%R9 |
(159) 0x427c2f MOV %R8,%R11 |
(159) 0x427c32 MOV %RSI,%RBX |
(159) 0x427c35 SUB 0x68(%RSP),%RDI |
(159) 0x427c3a MOV %R12,%RAX |
(159) 0x427c3d IMUL %RDI,%RAX |
(159) 0x427c41 MOV 0x18(%RBP),%RSI |
(159) 0x427c45 ADD %RSI,%RAX |
(159) 0x427c48 MOV 0x78(%RSP),%RCX |
(159) 0x427c4d LEA (%R10,%RCX,1),%R13 |
(159) 0x427c51 MOV %R13,%RCX |
(159) 0x427c54 SUB 0x70(%RSP),%RCX |
(159) 0x427c59 VMOVSD (%RAX,%RCX,8),%XMM14 |
(159) 0x427c5e LEA 0x1(%RDI),%RAX |
(159) 0x427c62 MOV %R12,%RDX |
(159) 0x427c65 IMUL %RAX,%RDX |
(159) 0x427c69 ADD %RSI,%RDX |
(159) 0x427c6c VMOVSD (%RDX,%RCX,8),%XMM15 |
(159) 0x427c71 MOV 0x30(%RSP),%R8 |
(159) 0x427c76 IMUL %R8,%RAX |
(159) 0x427c7a MOV 0x20(%RBP),%RDX |
(159) 0x427c7e ADD %RDX,%RAX |
(159) 0x427c81 VMOVSD (%RAX,%RCX,8),%XMM0 |
(159) 0x427c86 MOV %R8,%RAX |
(159) 0x427c89 IMUL %RDI,%RAX |
(159) 0x427c8d ADD %RDX,%RAX |
(159) 0x427c90 VADDSD (%RAX,%RCX,8),%XMM0,%XMM0 |
(159) 0x427c95 MOV %RBX,%RSI |
(159) 0x427c98 IMUL %RBX,%RDI |
(159) 0x427c9c ADD 0x60(%RBP),%RDI |
(159) 0x427ca0 VMULSD (%RDI,%RCX,8),%XMM0,%XMM16 |
(159) 0x427ca7 MOV 0x80(%RSP),%RAX |
(159) 0x427caf SUB %R10,%RAX |
(159) 0x427cb2 MOV %RAX,0x50(%RSP) |
(159) 0x427cb7 MOV %R12,%RCX |
(159) 0x427cba MOV %R11,%R10 |
(159) 0x427cbd IMUL %R11,%RCX |
(159) 0x427cc1 IMUL %R9,%R12 |
(159) 0x427cc5 IMUL %R9,%RSI |
(159) 0x427cc9 MOV %R8,%RDI |
(159) 0x427ccc IMUL %R11,%RDI |
(159) 0x427cd0 IMUL %R9,%R8 |
(159) 0x427cd4 IMUL %R14,%R10 |
(159) 0x427cd8 IMUL %R9,%R14 |
(159) 0x427cdc IMUL %R9,%R15 |
(159) 0x427ce0 MOV 0x28(%RSP),%RAX |
(159) 0x427ce5 IMUL %R9,%RAX |
(159) 0x427ce9 MOV 0x1c0(%RSP),%RBX |
(159) 0x427cf1 IMUL %R9,%RBX |
(159) 0x427cf5 MOV 0x20(%RSP),%R11 |
(159) 0x427cfa IMUL %R9,%R11 |
(159) 0x427cfe LEA (%RCX,%R13,8),%RCX |
(159) 0x427d02 LEA (%R12,%R13,8),%RDX |
(159) 0x427d06 LEA (%RSI,%R13,8),%RSI |
(159) 0x427d0a LEA (%RDI,%R13,8),%RDI |
(159) 0x427d0e LEA (%R8,%R13,8),%R8 |
(159) 0x427d12 LEA (%R10,%R13,8),%R9 |
(159) 0x427d16 LEA (%R14,%R13,8),%R10 |
(159) 0x427d1a MOV %R11,%R12 |
(159) 0x427d1d LEA (%R15,%R13,8),%R11 |
(159) 0x427d21 LEA (%RAX,%R13,8),%R14 |
(159) 0x427d25 LEA (%RBX,%R13,8),%R15 |
(159) 0x427d29 LEA (%R12,%R13,8),%R12 |
(159) 0x427d2d MOV 0x170(%RSP),%RBX |
(159) 0x427d35 LEA (%RBX,%R13,8),%R13 |
(159) 0x427d39 MOV 0x168(%RSP),%RBX |
(159) 0x427d41 ADD %RBX,%RCX |
(159) 0x427d44 ADD %RBX,%RDX |
(159) 0x427d47 ADD 0x160(%RSP),%RSI |
(159) 0x427d4f MOV 0x178(%RSP),%RBX |
(159) 0x427d57 ADD %RBX,%RDI |
(159) 0x427d5a ADD %RBX,%R8 |
(159) 0x427d5d MOV 0x158(%RSP),%RBX |
(159) 0x427d65 ADD %RBX,%R9 |
(159) 0x427d68 ADD %RBX,%R10 |
(159) 0x427d6b ADD 0x150(%RSP),%R11 |
(159) 0x427d73 ADD 0x148(%RSP),%R14 |
(159) 0x427d7b ADD 0x140(%RSP),%R15 |
(159) 0x427d83 ADD 0x138(%RSP),%R12 |
(159) 0x427d8b XOR %EBX,%EBX |
(159) 0x427d8d JMP 427e72 |
0x427d92 NOPW %CS:(%RAX,%RAX,1) |
0x427da1 NOPW %CS:(%RAX,%RAX,1) |
0x427db0 NOPW %CS:(%RAX,%RAX,1) |
0x427dbf NOP |
(160) 0x427dc0 MOV 0x88(%RBP),%RAX |
(160) 0x427dc7 VMOVSD (%RAX),%XMM18 |
(160) 0x427dcd VMOVSD (%R13,%RBX,8),%XMM1 |
(160) 0x427dd4 VMOVSD (%R12,%RBX,8),%XMM6 |
(160) 0x427dda VMOVSD (%R15,%RBX,8),%XMM7 |
(160) 0x427de0 VADDSD %XMM7,%XMM7,%XMM7 |
(160) 0x427de4 VDIVSD (%R14,%RBX,8),%XMM7,%XMM7 |
(160) 0x427dea VFMADD231SD %XMM6,%XMM6,%XMM7 |
(160) 0x427def VSQRTSD %XMM7,%XMM7,%XMM6 |
(160) 0x427df3 VMAXSD %XMM11,%XMM6,%XMM6 |
(160) 0x427df8 VMINSD %XMM20,%XMM1,%XMM1 |
(160) 0x427dfe VMULSD %XMM1,%XMM22,%XMM1 |
(160) 0x427e04 VDIVSD %XMM6,%XMM1,%XMM1 |
(160) 0x427e08 VMULSD %XMM21,%XMM17,%XMM6 |
(160) 0x427e0e VMOVDDUP 0xce33a(%RIP),%XMM7 |
(160) 0x427e16 VANDPD %XMM7,%XMM16,%XMM8 |
(160) 0x427e1c VANDPD %XMM7,%XMM2,%XMM9 |
(160) 0x427e20 VMULSD %XMM3,%XMM11,%XMM3 |
(160) 0x427e24 VMAXSD %XMM3,%XMM9,%XMM9 |
(160) 0x427e28 VMAXSD %XMM9,%XMM8,%XMM8 |
(160) 0x427e2d VDIVSD %XMM8,%XMM6,%XMM6 |
(160) 0x427e32 VMULSD %XMM19,%XMM17,%XMM8 |
(160) 0x427e38 VANDPD %XMM7,%XMM0,%XMM0 |
(160) 0x427e3c VANDPD %XMM7,%XMM4,%XMM4 |
(160) 0x427e40 VMAXSD %XMM3,%XMM4,%XMM3 |
(160) 0x427e44 VMAXSD %XMM3,%XMM0,%XMM0 |
(160) 0x427e48 VDIVSD %XMM0,%XMM8,%XMM0 |
(160) 0x427e4c VMINSD %XMM18,%XMM0,%XMM0 |
(160) 0x427e52 VMINSD %XMM0,%XMM6,%XMM0 |
(160) 0x427e56 VMINSD %XMM0,%XMM1,%XMM0 |
(160) 0x427e5a VMINSD %XMM0,%XMM13,%XMM13 |
(160) 0x427e5e INC %RBX |
(160) 0x427e61 VMOVAPD %XMM2,%XMM16 |
(160) 0x427e67 CMP %RBX,0x50(%RSP) |
(160) 0x427e6c JE 4274d0 |
(160) 0x427e72 VMOVSD (%RDI,%RBX,8),%XMM0 |
(160) 0x427e77 VADDSD (%R8,%RBX,8),%XMM0,%XMM0 |
(160) 0x427e7d VMOVAPD %XMM15,%XMM1 |
(160) 0x427e81 VMOVAPD %XMM14,%XMM4 |
(160) 0x427e85 VMULSD (%RSI,%RBX,8),%XMM0,%XMM2 |
(160) 0x427e8a VMOVSD (%R11,%RBX,8),%XMM3 |
(160) 0x427e90 VMOVSD (%RDX,%RBX,8),%XMM14 |
(160) 0x427e95 VADDSD %XMM4,%XMM14,%XMM0 |
(160) 0x427e99 VMULSD (%R10,%RBX,8),%XMM0,%XMM0 |
(160) 0x427e9f VMOVSD (%RCX,%RBX,8),%XMM15 |
(160) 0x427ea4 VADDSD %XMM1,%XMM15,%XMM1 |
(160) 0x427ea8 VMULSD (%R9,%RBX,8),%XMM1,%XMM4 |
(160) 0x427eae VADDSD %XMM3,%XMM3,%XMM17 |
(160) 0x427eb4 VADDSD %XMM0,%XMM16,%XMM1 |
(160) 0x427eba VSUBSD %XMM1,%XMM2,%XMM1 |
(160) 0x427ebe VADDSD %XMM4,%XMM1,%XMM1 |
(160) 0x427ec2 VDIVSD %XMM17,%XMM1,%XMM18 |
(160) 0x427ec8 VUCOMISD %XMM18,%XMM12 |
(160) 0x427ece JBE 427dc0 |
(160) 0x427ed4 MOV 0x68(%RBP),%RAX |
(160) 0x427ed8 VMOVSD (%RAX),%XMM1 |
(160) 0x427edc VXORPD %XMM1,%XMM10,%XMM1 |
(160) 0x427ee0 VDIVSD %XMM18,%XMM1,%XMM18 |
(160) 0x427ee6 JMP 427dcd |
0x427eeb NOPW %CS:(%RAX,%RAX,1) |
0x427efa NOPW (%RAX,%RAX,1) |
(159) 0x427f00 VPBROADCASTQ %XMM0,%ZMM0 |
(159) 0x427f06 VBROADCASTSD %XMM13,%ZMM13 |
(159) 0x427f0c VPCMPNLEUQ 0xd2e69(%RIP),%ZMM0,%K1 |
(159) 0x427f17 VPCMPNLEUQ 0xd2e9e(%RIP),%ZMM0,%K2 |
(159) 0x427f22 KORTESTB %K1,%K2 |
(159) 0x427f26 JE 427400 |
(159) 0x427f2c MOV %RCX,%R11 |
(159) 0x427f2f VMOVAPD %XMM22,0x90(%RSP) |
(159) 0x427f37 VMOVAPD %XMM21,0xa0(%RSP) |
(159) 0x427f3f VMOVAPD %XMM20,0xb0(%RSP) |
(159) 0x427f47 VMOVAPD %XMM19,0x50(%RSP) |
(159) 0x427f4f ADD 0x78(%RSP),%R10 |
(159) 0x427f54 SUB 0x70(%RSP),%R10 |
(159) 0x427f59 SUB 0x68(%RSP),%RDI |
(159) 0x427f5e LEA 0x1(%RDI),%RAX |
(159) 0x427f62 MOV 0x30(%RSP),%R8 |
(159) 0x427f67 MOV %R8,%RCX |
(159) 0x427f6a IMUL %RAX,%RCX |
(159) 0x427f6e MOV 0x20(%RBP),%RDX |
(159) 0x427f72 ADD %RDX,%RCX |
(159) 0x427f75 VMOVUPD (%RCX,%R10,8),%ZMM22{%K2}{z} |
(159) 0x427f7c VMOVUPD 0x40(%RCX,%R10,8),%ZMM16{%K1}{z} |
(159) 0x427f84 VMOVUPD 0x48(%RCX,%R10,8),%ZMM3{%K1}{z} |
(159) 0x427f8f VMOVUPD 0x8(%RCX,%R10,8),%ZMM4{%K2}{z} |
(159) 0x427f9a IMUL %RDI,%R8 |
(159) 0x427f9e ADD %RDX,%R8 |
(159) 0x427fa1 VMOVUPD (%R8,%R10,8),%ZMM0{%K2}{z} |
(159) 0x427fa8 VMOVUPD 0x40(%R8,%R10,8),%ZMM1{%K1}{z} |
(159) 0x427fb0 VMOVUPD 0x48(%R8,%R10,8),%ZMM6{%K1}{z} |
(159) 0x427fbb VMOVUPD 0x8(%R8,%R10,8),%ZMM7{%K2}{z} |
(159) 0x427fc6 IMUL %RDI,%RSI |
(159) 0x427fca ADD 0x60(%RBP),%RSI |
(159) 0x427fce VMOVUPD 0x40(%RSI,%R10,8),%ZMM8{%K1}{z} |
(159) 0x427fd6 VMOVUPD (%RSI,%R10,8),%ZMM9{%K2}{z} |
(159) 0x427fdd VMOVUPD 0x8(%RSI,%R10,8),%ZMM10{%K2}{z} |
(159) 0x427fe8 VMOVUPD 0x48(%RSI,%R10,8),%ZMM17{%K1}{z} |
(159) 0x427ff3 IMUL %RDI,%R15 |
(159) 0x427ff7 ADD 0x40(%RBP),%R15 |
(159) 0x427ffb VMOVUPD (%R15,%R10,8),%ZMM23{%K2}{z} |
(159) 0x428002 VMOVUPD 0x40(%R15,%R10,8),%ZMM2{%K1}{z} |
(159) 0x42800a MOV %R12,%RCX |
(159) 0x42800d IMUL %RDI,%RCX |
(159) 0x428011 MOV 0x18(%RBP),%RSI |
(159) 0x428015 ADD %RSI,%RCX |
(159) 0x428018 VMOVUPD 0x48(%RCX,%R10,8),%ZMM18{%K1}{z} |
(159) 0x428023 VMOVUPD 0x8(%RCX,%R10,8),%ZMM19{%K2}{z} |
(159) 0x42802e VMOVUPD 0x40(%RCX,%R10,8),%ZMM20{%K1}{z} |
(159) 0x428036 VMOVUPD (%RCX,%R10,8),%ZMM21{%K2}{z} |
(159) 0x42803d MOV %R14,%RCX |
(159) 0x428040 IMUL %RDI,%RCX |
(159) 0x428044 MOV 0x58(%RBP),%RDX |
(159) 0x428048 ADD %RDX,%RCX |
(159) 0x42804b VMOVUPD (%RCX,%R10,8),%ZMM26{%K2}{z} |
(159) 0x428052 VMOVUPD 0x40(%RCX,%R10,8),%ZMM27{%K1}{z} |
(159) 0x42805a IMUL %RAX,%R12 |
(159) 0x42805e ADD %RSI,%R12 |
(159) 0x428061 VMOVUPD 0x48(%R12,%R10,8),%ZMM28{%K1}{z} |
(159) 0x42806c VMOVUPD 0x8(%R12,%R10,8),%ZMM29{%K2}{z} |
(159) 0x428077 VMOVUPD 0x40(%R12,%R10,8),%ZMM30{%K1}{z} |
(159) 0x42807f VMOVUPD (%R12,%R10,8),%ZMM31{%K2}{z} |
(159) 0x428086 IMUL %RAX,%R14 |
(159) 0x42808a ADD %RDX,%R14 |
(159) 0x42808d VMOVUPD (%R14,%R10,8),%ZMM14{%K2}{z} |
(159) 0x428094 VMOVUPD 0x40(%R14,%R10,8),%ZMM15{%K1}{z} |
(159) 0x42809c VADDPD %ZMM0,%ZMM22,%ZMM0 |
(159) 0x4280a2 VADDPD %ZMM1,%ZMM16,%ZMM1 |
(159) 0x4280a8 VMULPD %ZMM1,%ZMM8,%ZMM24 |
(159) 0x4280ae VMULPD %ZMM0,%ZMM9,%ZMM22 |
(159) 0x4280b4 VADDPD %ZMM6,%ZMM3,%ZMM0 |
(159) 0x4280ba VADDPD %ZMM7,%ZMM4,%ZMM1 |
(159) 0x4280c0 VMULPD %ZMM10,%ZMM1,%ZMM25 |
(159) 0x4280c6 VMOVAPD %ZMM23,%ZMM10 |
(159) 0x4280cc VMULPD %ZMM17,%ZMM0,%ZMM23 |
(159) 0x4280d2 VADDPD %ZMM20,%ZMM18,%ZMM0 |
(159) 0x4280d8 VADDPD %ZMM21,%ZMM19,%ZMM1 |
(159) 0x4280de VMULPD %ZMM1,%ZMM26,%ZMM17 |
(159) 0x4280e4 VMULPD %ZMM0,%ZMM27,%ZMM18 |
(159) 0x4280ea VMOVAPD %ZMM2,0x1c0(%RSP) |
(159) 0x4280f2 VADDPD %ZMM2,%ZMM2,%ZMM20 |
(159) 0x4280f8 VADDPD %ZMM30,%ZMM28,%ZMM0 |
(159) 0x4280fe VADDPD %ZMM10,%ZMM10,%ZMM21 |
(159) 0x428104 VADDPD %ZMM31,%ZMM29,%ZMM1 |
(159) 0x42810a VMULPD %ZMM14,%ZMM1,%ZMM16 |
(159) 0x428110 VMULPD %ZMM15,%ZMM0,%ZMM19 |
(159) 0x428116 VADDPD %ZMM17,%ZMM22,%ZMM0 |
(159) 0x42811c VADDPD %ZMM18,%ZMM24,%ZMM1 |
(159) 0x428122 VSUBPD %ZMM1,%ZMM23,%ZMM1 |
(159) 0x428128 VSUBPD %ZMM0,%ZMM25,%ZMM0 |
(159) 0x42812e VADDPD %ZMM16,%ZMM0,%ZMM0 |
(159) 0x428134 VADDPD %ZMM19,%ZMM1,%ZMM1 |
(159) 0x42813a VDIVPD %ZMM20,%ZMM1,%ZMM2 |
(159) 0x428140 VDIVPD %ZMM21,%ZMM0,%ZMM0 |
(159) 0x428146 KUNPCKBW %K2,%K1,%K0 |
(159) 0x42814a VBROADCASTSD %XMM12,%ZMM3 |
(159) 0x428150 VCMPPD $0x5,%ZMM3,%ZMM0,%K3 |
(159) 0x428157 VCMPPD $0x5,%ZMM3,%ZMM2,%K4 |
(159) 0x42815e KUNPCKBW %K3,%K4,%K3 |
(159) 0x428162 KTESTW %K3,%K0 |
(159) 0x428166 JE 428173 |
(159) 0x428168 MOV 0x88(%RBP),%RAX |
(159) 0x42816f VMOVSD (%RAX),%XMM12 |
(159) 0x428173 VCMPPD $0x1,%ZMM3,%ZMM0,%K3 |
(159) 0x42817a VCMPPD $0x1,%ZMM3,%ZMM2,%K4 |
(159) 0x428181 KUNPCKBW %K3,%K4,%K3 |
(159) 0x428185 KANDW %K3,%K0,%K3 |
(159) 0x428189 KORTESTW %K3,%K3 |
(159) 0x42818d JE 4281c0 |
(159) 0x42818f VBROADCASTSD 0xd023f(%RIP),%ZMM1 |
(159) 0x428199 MOV 0x68(%RBP),%RAX |
(159) 0x42819d VXORPD (%RAX){1to8},%ZMM1,%ZMM1 |
(159) 0x4281a3 VDIVPD %ZMM2,%ZMM1,%ZMM27 |
(159) 0x4281a9 VDIVPD %ZMM0,%ZMM1,%ZMM26 |
(159) 0x4281af JMP 4281cc |
0x4281b1 NOPW %CS:(%RAX,%RAX,1) |
(159) 0x4281c0 VXORPD %XMM26,%XMM26,%XMM26 |
(159) 0x4281c6 VXORPD %XMM27,%XMM27,%XMM27 |
(159) 0x4281cc MOV 0x50(%RBP),%RAX |
(159) 0x4281d0 VMOVUPD (%RAX,%R10,8),%ZMM0{%K2}{z} |
(159) 0x4281d7 VMOVUPD 0x40(%RAX,%R10,8),%ZMM1{%K1}{z} |
(159) 0x4281df IMUL %RDI,%R13 |
(159) 0x4281e3 ADD 0x28(%RBP),%R13 |
(159) 0x4281e7 VMOVUPD 0x40(%R13,%R10,8),%ZMM2{%K1}{z} |
(159) 0x4281ef VMOVUPD (%R13,%R10,8),%ZMM3{%K2}{z} |
(159) 0x4281f7 IMUL %RDI,%R11 |
(159) 0x4281fb ADD 0x30(%RBP),%R11 |
(159) 0x4281ff VMOVUPD 0x40(%R11,%R10,8),%ZMM4{%K1}{z} |
(159) 0x428207 VMOVUPD (%R11,%R10,8),%ZMM6{%K2}{z} |
(159) 0x42820e VBROADCASTSD 0xceef0(%RIP),%ZMM9 |
(159) 0x428218 VMOVAPD %ZMM9,%ZMM7 |
(159) 0x42821e IMUL %RDI,%R9 |
(159) 0x428222 ADD 0x38(%RBP),%R9 |
(159) 0x428226 VMOVUPD (%R9,%R10,8),%ZMM8{%K2}{z} |
(159) 0x42822d VADDPD %ZMM6,%ZMM6,%ZMM7{%K2} |
(159) 0x428233 VMOVAPD %ZMM9,%ZMM6 |
(159) 0x428239 VDIVPD %ZMM8,%ZMM7,%ZMM7 |
(159) 0x42823f VMOVUPD 0x40(%R9,%R10,8),%ZMM8{%K1}{z} |
(159) 0x428247 VADDPD %ZMM4,%ZMM4,%ZMM6{%K1} |
(159) 0x42824d VDIVPD %ZMM8,%ZMM6,%ZMM4 |
(159) 0x428253 VFMADD231PD %ZMM3,%ZMM3,%ZMM7 |
(159) 0x428259 VFMADD231PD %ZMM2,%ZMM2,%ZMM4 |
(159) 0x42825f VSQRTPD %ZMM4,%ZMM2 |
(159) 0x428265 VSQRTPD %ZMM7,%ZMM3 |
(159) 0x42826b VBROADCASTSD %XMM11,%ZMM4 |
(159) 0x428271 VMAXPD %ZMM4,%ZMM3,%ZMM3 |
(159) 0x428277 VMAXPD %ZMM4,%ZMM2,%ZMM2 |
(159) 0x42827d VBROADCASTSD 0xb0(%RSP),%ZMM6 |
(159) 0x428285 VMINPD %ZMM6,%ZMM1,%ZMM1 |
(159) 0x42828b VMINPD %ZMM6,%ZMM0,%ZMM0 |
(159) 0x428291 VBROADCASTSD 0x90(%RSP),%ZMM6 |
(159) 0x428299 VMULPD %ZMM0,%ZMM6,%ZMM0 |
(159) 0x42829f VDIVPD %ZMM3,%ZMM0,%ZMM0 |
(159) 0x4282a5 VMULPD %ZMM1,%ZMM6,%ZMM1 |
(159) 0x4282ab VDIVPD %ZMM2,%ZMM1,%ZMM1 |
(159) 0x4282b1 VBROADCASTSD 0xa0(%RSP),%ZMM2 |
(159) 0x4282b9 VMULPD %ZMM2,%ZMM21,%ZMM3 |
(159) 0x4282bf VMULPD %ZMM2,%ZMM20,%ZMM2 |
(159) 0x4282c5 VXORPD %XMM6,%XMM6,%XMM6 |
(159) 0x4282c9 VANDPD %ZMM5,%ZMM24,%ZMM6{%K1} |
(159) 0x4282cf VXORPD %XMM7,%XMM7,%XMM7 |
(159) 0x4282d3 VANDPD %ZMM5,%ZMM22,%ZMM7{%K2} |
(159) 0x4282d9 VXORPD %XMM8,%XMM8,%XMM8 |
(159) 0x4282de VANDPD %ZMM5,%ZMM25,%ZMM8{%K2} |
(159) 0x4282e4 VXORPD %XMM9,%XMM9,%XMM9 |
(159) 0x4282e9 VANDPD %ZMM5,%ZMM23,%ZMM9{%K1} |
(159) 0x4282ef VMULPD %ZMM4,%ZMM10,%ZMM10 |
(159) 0x4282f5 VMULPD 0x1c0(%RSP),%ZMM4,%ZMM4 |
(159) 0x4282fd VMAXPD %ZMM4,%ZMM9,%ZMM9 |
(159) 0x428303 VMAXPD %ZMM9,%ZMM6,%ZMM6 |
(159) 0x428309 VDIVPD %ZMM6,%ZMM2,%ZMM2 |
(159) 0x42830f VMAXPD %ZMM10,%ZMM8,%ZMM6 |
(159) 0x428315 VMAXPD %ZMM6,%ZMM7,%ZMM6 |
(159) 0x42831b VDIVPD %ZMM6,%ZMM3,%ZMM3 |
(159) 0x428321 VBROADCASTSD 0x50(%RSP),%ZMM6 |
(159) 0x428329 VMULPD %ZMM6,%ZMM21,%ZMM7 |
(159) 0x42832f VMULPD %ZMM6,%ZMM20,%ZMM6 |
(159) 0x428335 VXORPD %XMM8,%XMM8,%XMM8 |
(159) 0x42833a VANDPD %ZMM5,%ZMM18,%ZMM8{%K1} |
(159) 0x428340 VXORPD %XMM9,%XMM9,%XMM9 |
(159) 0x428345 VANDPD %ZMM5,%ZMM17,%ZMM9{%K2} |
(159) 0x42834b VXORPD %XMM11,%XMM11,%XMM11 |
(159) 0x428350 VXORPD %XMM14,%XMM14,%XMM14 |
(159) 0x428355 VANDPD %ZMM5,%ZMM19,%ZMM14{%K1} |
(159) 0x42835b VMAXPD %ZMM4,%ZMM14,%ZMM4 |
(159) 0x428361 VMAXPD %ZMM4,%ZMM8,%ZMM4 |
(159) 0x428367 VDIVPD %ZMM4,%ZMM6,%ZMM4 |
(159) 0x42836d VANDPD %ZMM5,%ZMM16,%ZMM11{%K2} |
(159) 0x428373 VMAXPD %ZMM10,%ZMM11,%ZMM6 |
(159) 0x428379 VMAXPD %ZMM6,%ZMM9,%ZMM6 |
(159) 0x42837f VDIVPD %ZMM6,%ZMM7,%ZMM6 |
(159) 0x428385 VBROADCASTSD %XMM12,%ZMM7 |
(159) 0x42838b KSHIFTRW $0x8,%K3,%K4 |
(159) 0x428391 VBLENDMPD %ZMM27,%ZMM7,%ZMM8{%K4} |
(159) 0x428397 VMINPD %ZMM8,%ZMM4,%ZMM4 |
(159) 0x42839d VMINPD %ZMM4,%ZMM2,%ZMM2 |
(159) 0x4283a3 VMINPD %ZMM2,%ZMM1,%ZMM1 |
(159) 0x4283a9 VMOVAPD %ZMM26,%ZMM7{%K3} |
(159) 0x4283af VMINPD %ZMM7,%ZMM6,%ZMM2 |
(159) 0x4283b5 VMINPD %ZMM2,%ZMM3,%ZMM2 |
(159) 0x4283bb VMINPD %ZMM2,%ZMM0,%ZMM0 |
(159) 0x4283c1 VMINPD %ZMM1,%ZMM13,%ZMM2 |
(159) 0x4283c7 VMINPD %ZMM0,%ZMM13,%ZMM0 |
(159) 0x4283cd VMOVDDUP 0xd0003(%RIP),%XMM10 |
(159) 0x4283d5 JMP 427408 |
0x4283da NOPW %CS:(%RAX,%RAX,1) |
0x4283e4 NOPW %CS:(%RAX,%RAX,1) |
0x4283ee NOPW %CS:(%RAX,%RAX,1) |
0x4283f8 NOPL (%RAX,%RAX,1) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_invoke_task_func | libiomp5.so |
| Path / |
The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2
| Source file and lines | calc_dt_kernel.f90:89-133 |
| Module | exec |
| nb instructions | 198 |
| nb uops | 204 |
| loop length | 1107 |
| used x86 registers | 16 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 2 |
| nb stack references | 58 |
| micro-operation queue | 34.00 cycles |
| front end | 34.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 10.90 | 10.80 | 12.67 | 12.67 | 27.00 | 10.80 | 10.70 | 27.00 | 27.00 | 27.00 | 10.80 | 12.67 |
| cycles | 10.90 | 16.97 | 12.67 | 12.67 | 27.00 | 10.80 | 10.70 | 27.00 | 27.00 | 27.00 | 10.80 | 12.67 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 34.00 |
| Dispatch | 27.00 |
| Overall L1 | 34.00 |
| all | 2% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 20% |
| all | 11% |
| load | 0% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 3% |
| load | 0% |
| store | 2% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| all | 10% |
| load | 6% |
| store | 11% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 22% |
| load | 12% |
| store | 41% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 9% |
| store | 13% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| SUB $0x280,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0xa0(%RBP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x98(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| SUB %R14D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOVL $0,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| JS 4271df <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x12f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOVL $0,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV %EAX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOVL $0x1,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| LEA 0x50(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA 0x54(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA 0x24(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA 0x20(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV $0x53a3d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| CALL 404850 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV 0x1c(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOV 0x18(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| SUB %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %EAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| JAE 427200 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x150> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVSD 0xd3c01(%RIP),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVSD %XMM13,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV $0x53a3f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x38(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
| CALL 404070 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| MOV 0x60(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV $0x593220,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| LEA 0x90(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV $0x53a410,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x4270a0,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| CALL 4045b0 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| JNE 4271df <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x12f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSD 0x88(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOV $0x593220,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x53a430,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| CALL 404170 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| MOV 0x60(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOV $0x53a450,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| CALL 4047c0 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 | N/A |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0xa8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOVSXD (%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV (%RCX),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| SUB %EDI,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| ADD %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| LEA -0x2(%R15),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| MOV %RAX,0x198(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %RCX,0x1a8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x1(%RCX),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| CMP $0x2,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| MOV $0x1,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %EAX,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| CMOVGE %EAX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| AND $0x7ffffff0,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| MOV %RAX,0x190(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %RCX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVQ %RCX,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | scal (12.5%) |
| VMOVAPD %ZMM0,0x200(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 | vect (100.0%) |
| MOVSXD %EBX,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOV %RDI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (,%RDI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA -0x2(%RDX),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RDI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| SUB %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x3,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| SUB %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %RDI,0x188(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV $0x18,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x10,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| SUB %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| SUB %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %RDX,0x180(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| ADD $-0x2,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x50(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x38(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x30(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x28(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x20(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x18(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA 0x18(%R12,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x18(%RCX,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x18(%R15,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%RDX,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%R10,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%R11,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%RBX,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%R14,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%R9,%RAX,1),%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %RAX,0x1b8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R12,%RDI,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%RCX,%RDI,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| ADD %R15,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %RDI,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%RDX,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R10,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R11,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%RBX,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R14,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| ADD %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %R8,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD 0xd398c(%RIP),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVDDUP 0xd1004(%RIP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VBROADCASTSD 0xced72(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RSI,0x1a0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %ESI,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JMP 4274ed <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x43d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2
| Source file and lines | calc_dt_kernel.f90:89-133 |
| Module | exec |
| nb instructions | 198 |
| nb uops | 204 |
| loop length | 1107 |
| used x86 registers | 16 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 2 |
| nb stack references | 58 |
| micro-operation queue | 34.00 cycles |
| front end | 34.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 10.90 | 10.80 | 12.67 | 12.67 | 27.00 | 10.80 | 10.70 | 27.00 | 27.00 | 27.00 | 10.80 | 12.67 |
| cycles | 10.90 | 16.97 | 12.67 | 12.67 | 27.00 | 10.80 | 10.70 | 27.00 | 27.00 | 27.00 | 10.80 | 12.67 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 34.00 |
| Dispatch | 27.00 |
| Overall L1 | 34.00 |
| all | 2% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 20% |
| all | 11% |
| load | 0% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 3% |
| load | 0% |
| store | 2% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| all | 10% |
| load | 6% |
| store | 11% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 22% |
| load | 12% |
| store | 41% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 9% |
| store | 13% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| SUB $0x280,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0xa0(%RBP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x98(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| SUB %R14D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOVL $0,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| JS 4271df <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x12f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOVL $0,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV %EAX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOVL $0x1,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| LEA 0x50(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA 0x54(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA 0x24(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA 0x20(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV $0x53a3d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| CALL 404850 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV 0x1c(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOV 0x18(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| SUB %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %EAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| JAE 427200 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x150> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVSD 0xd3c01(%RIP),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVSD %XMM13,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV $0x53a3f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x38(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
| CALL 404070 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| MOV 0x60(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV $0x593220,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| LEA 0x90(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV $0x53a410,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x4270a0,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
| CALL 4045b0 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| JNE 4271df <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x12f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSD 0x88(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOV $0x593220,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x53a430,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| CALL 404170 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| MOV 0x60(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOV $0x53a450,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| CALL 4047c0 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
| LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
| RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 | N/A |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0xa8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOVSXD (%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV (%RCX),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| SUB %EDI,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| ADD %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| LEA -0x2(%R15),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| MOV %RAX,0x198(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %RCX,0x1a8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x1(%RCX),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| CMP $0x2,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| MOV $0x1,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %EAX,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| CMOVGE %EAX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| AND $0x7ffffff0,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| MOV %RAX,0x190(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %RCX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVQ %RCX,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | scal (12.5%) |
| VMOVAPD %ZMM0,0x200(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 | vect (100.0%) |
| MOVSXD %EBX,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOV %RDI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (,%RDI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA -0x2(%RDX),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RDI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| SUB %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x3,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| SUB %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %RDI,0x188(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV $0x18,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x10,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| SUB %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| SUB %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %RDX,0x180(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| ADD $-0x2,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x50(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x38(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x30(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x28(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x20(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x18(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA 0x18(%R12,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x18(%RCX,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x18(%R15,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%RDX,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%R10,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%R11,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%RBX,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%R14,%RAX,1),%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %R13,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA 0x10(%R9,%RAX,1),%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %RAX,0x1b8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R12,%RDI,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%RCX,%RDI,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| ADD %R15,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %RDI,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%RDX,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R10,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R11,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%RBX,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R14,%R8,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RAX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| ADD %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV %R8,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD 0xd398c(%RIP),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVDDUP 0xd1004(%RIP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VBROADCASTSD 0xced72(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV %RSI,0x1a0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %ESI,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JMP 4274ed <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x43d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2– | 3.32 | 1.22 |
| ▼Loop 159 - calc_dt_kernel.f90:92-129 - exec– | 0.00 | 0.01 |
| ○Loop 161 - calc_dt_kernel.f90:92-129 - exec | 3.31 | 1.22 |
| ○Loop 160 - calc_dt_kernel.f90:94-129 - exec | 0.00 | 0.00 |
