OV - exec - Function revert_kernel_module_mp_revert_kernel

	Function: revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2	Module: exec	Source: revert_kernel.f90:41-51	Coverage (incl. loops): 2.64% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90: 41 - 51

--------------------------------------------------------------------------------

41:     !$OMP PARALLEL

42:

43:     !$OMP DO

44:     DO k=y_min,y_max

45:     !$OMP SIMD

46:       DO j=x_min,x_max

47:         density1(j,k)=density0(j,k)

48:         energy1(j,k)=energy0(j,k)

49:       ENDDO

50:     ENDDO

51:   !$OMP END DO

0x436970 PUSH	%RBP

0x436971 MOV	%RSP,%RBP

0x436974 PUSH	%R15

0x436976 PUSH	%R14

0x436978 PUSH	%R13

0x43697a PUSH	%R12

0x43697c PUSH	%RBX

0x43697d SUB	$0xb8,%RSP

0x436984 MOV	0x68(%RBP),%RAX

0x436988 MOV	%RAX,-0xd8(%RBP)

0x43698f MOV	0x60(%RBP),%RAX

0x436993 MOV	%RAX,-0xd0(%RBP)

0x43699a MOV	0x58(%RBP),%RAX

0x43699e MOV	%RAX,-0xc8(%RBP)

0x4369a5 MOV	0x50(%RBP),%RAX

0x4369a9 MOV	%RAX,-0xc0(%RBP)

0x4369b0 MOV	0x48(%RBP),%R12

0x4369b4 MOV	0x40(%RBP),%R15

0x4369b8 MOV	0x28(%RBP),%RAX

0x4369bc MOV	%RAX,-0x60(%RBP)

0x4369c0 MOV	0x20(%RBP),%RAX

0x4369c4 MOV	%RAX,-0x58(%RBP)

0x4369c8 MOV	0x38(%RBP),%R13D

0x4369cc MOV	0x30(%RBP),%EAX

0x4369cf SUB	%R13D,%EAX

0x4369d2 MOV	0x18(%RBP),%RDX

0x4369d6 MOV	%RDX,-0x50(%RBP)

0x4369da MOV	0x10(%RBP),%RDX

0x4369de MOV	%RDX,-0x48(%RBP)

0x4369e2 MOVL	$0,-0x3c(%RBP)

0x4369e9 JS	436a55

0x4369eb MOV	%RCX,%R14

0x4369ee MOV	%R9,%RBX

0x4369f1 MOV	%RDI,-0x70(%RBP)

0x4369f5 MOV	(%RDI),%ESI

0x4369f7 MOVL	$0,-0x30(%RBP)

0x4369fe MOV	%EAX,-0x2c(%RBP)

0x436a01 MOVL	$0x1,-0x38(%RBP)

0x436a08 SUB	$0x8,%RSP

0x436a0c LEA	-0x38(%RBP),%RAX

0x436a10 LEA	-0x3c(%RBP),%RCX

0x436a14 LEA	-0x30(%RBP),%R8

0x436a18 LEA	-0x2c(%RBP),%R9

0x436a1c MOV	$0x53c090,%EDI

0x436a21 MOV	%ESI,-0x34(%RBP)

0x436a24 MOV	$0x22,%EDX

0x436a29 PUSH	$0x1

0x436a2b PUSH	$0x1

0x436a2d PUSH	%RAX

0x436a2e CALL	404850 <__kmpc_for_static_init_4@plt>

0x436a33 ADD	$0x20,%RSP

0x436a37 MOV	-0x30(%RBP),%EAX

0x436a3a MOV	-0x2c(%RBP),%ECX

0x436a3d SUB	%EAX,%ECX

0x436a3f JAE	436a80

0x436a41 MOV	$0x53c0b0,%EDI

0x436a46 MOV	-0x34(%RBP),%ESI

0x436a49 VZEROUPPER

0x436a4c CALL	404070 <__kmpc_for_static_fini@plt>

0x436a51 MOV	-0x70(%RBP),%RDI

0x436a55 MOV	(%RDI),%ESI

0x436a57 MOV	$0x53c0d0,%EDI

0x436a5c ADD	$0xb8,%RSP

0x436a63 POP	%RBX

0x436a64 POP	%R12

0x436a66 POP	%R13

0x436a68 POP	%R14

0x436a6a POP	%R15

0x436a6c POP	%RBP

0x436a6d JMP	4047c0

0x436a72 NOPW	%CS:(%RAX,%RAX,1)

0x436a80 MOV	%RAX,%RDI

0x436a83 MOVSXD	(%R12),%RDX

0x436a87 MOV	(%R15),%ESI

0x436a8a ADD	%R13D,%EDI

0x436a8d SUB	%EDX,%ESI

0x436a8f LEA	0x1(%RSI),%EAX

0x436a92 CMP	$0x2,%EAX

0x436a95 MOV	$0x1,%R9D

0x436a9b CMOVGE	%EAX,%R9D

0x436a9f MOV	%R9D,%R8D

0x436aa2 AND	$0x7ffffff8,%R8D

0x436aa9 MOVSXD	%R14D,%R10

0x436aac MOVSXD	%EBX,%RAX

0x436aaf MOV	%R9,-0xa0(%RBP)

0x436ab6 VPBROADCASTQ	%R9,%ZMM0

0x436abc MOV	%RDX,-0xb0(%RBP)

0x436ac3 LEA	(,%RDX,8),%RDX

0x436acb LEA	-0x2(%RAX),%R9

0x436acf MOV	%R9,-0xa8(%RBP)

0x436ad6 SAL	$0x3,%RAX

0x436ada SUB	%RAX,%RDX

0x436add MOV	-0x48(%RBP),%RAX

0x436ae1 LEA	0x10(%RAX,%RDX,1),%RAX

0x436ae6 MOV	%RAX,-0x98(%RBP)

0x436aed MOV	$0x2,%EAX

0x436af2 SUB	%R10,%RAX

0x436af5 MOV	%RAX,-0x90(%RBP)

0x436afc ADD	$-0x2,%R10

0x436b00 MOV	%R10,-0x68(%RBP)

0x436b04 MOV	-0x50(%RBP),%RAX

0x436b08 LEA	0x10(%RAX,%RDX,1),%RAX

0x436b0d MOV	%RAX,-0x88(%RBP)

0x436b14 MOV	-0x58(%RBP),%RAX

0x436b18 LEA	0x10(%RAX,%RDX,1),%RAX

0x436b1d MOV	%RAX,-0x80(%RBP)

0x436b21 MOV	-0x60(%RBP),%RAX

0x436b25 LEA	0x10(%RAX,%RDX,1),%RAX

0x436b2a MOV	%RAX,-0x78(%RBP)

0x436b2e XOR	%EDX,%EDX

0x436b30 VPMOVSXBQ	0xbf47a(%RIP),%ZMM1

0x436b3a MOV	%RDI,-0xb8(%RBP)

0x436b41 MOV	%EDI,%R11D

0x436b44 JMP	436c00

0x436b49 NOPW	%CS:(%RAX,%RAX,1)

0x436b58 NOPW	%CS:(%RAX,%RAX,1)

0x436b67 NOPW	%CS:(%RAX,%RAX,1)

0x436b76 NOPW	%CS:(%RAX,%RAX,1)

(297) 0x436b80 SUB	-0x68(%RBP),%R10

(297) 0x436b84 IMUL	%R10,%RAX

(297) 0x436b88 IMUL	%R10,%RDI

(297) 0x436b8c IMUL	%R10,%RBX

(297) 0x436b90 IMUL	%R14,%R10

(297) 0x436b94 MOV	%RBX,%R13

(297) 0x436b97 MOV	%RDI,%R12

(297) 0x436b9a MOV	%RAX,%R15

(297) 0x436b9d XOR	%EAX,%EAX

(297) 0x436b9f VPBROADCASTQ	%RAX,%ZMM2

(297) 0x436ba5 VPSUBQ	%ZMM2,%ZMM0,%ZMM2

(297) 0x436bab VPCMPNLEUQ	%ZMM1,%ZMM2,%K1

(297) 0x436bb2 ADD	-0x60(%RBP),%R15

(297) 0x436bb6 ADD	-0xb0(%RBP),%RAX

(297) 0x436bbd SUB	-0xa8(%RBP),%RAX

(297) 0x436bc4 VMOVUPD	(%R15,%RAX,8),%ZMM2{%K1}{z}

(297) 0x436bcb ADD	-0x58(%RBP),%R12

(297) 0x436bcf VMOVUPD	%ZMM2,(%R12,%RAX,8){%K1}

(297) 0x436bd6 ADD	-0x50(%RBP),%R13

(297) 0x436bda VMOVUPD	(%R13,%RAX,8),%ZMM2{%K1}{z}

(297) 0x436be2 ADD	-0x48(%RBP),%R10

(297) 0x436be6 VMOVUPD	%ZMM2,(%R10,%RAX,8){%K1}

(297) 0x436bed JMP	436bf0

0x436bef NOP

(297) 0x436bf0 LEA	0x1(%RDX),%EAX

(297) 0x436bf3 INC	%R11D

(297) 0x436bf6 CMP	%ECX,%EDX

(297) 0x436bf8 MOV	%EAX,%EDX

(297) 0x436bfa JE	436a41

(297) 0x436c00 TEST	%ESI,%ESI

(297) 0x436c02 JS	436bf0

(297) 0x436c04 MOV	-0xb8(%RBP),%RAX

(297) 0x436c0b LEA	(%RAX,%RDX,1),%R9D

(297) 0x436c0f MOV	-0xc0(%RBP),%RAX

(297) 0x436c16 MOV	(%RAX),%RAX

(297) 0x436c19 MOV	-0xc8(%RBP),%RDI

(297) 0x436c20 MOV	(%RDI),%RDI

(297) 0x436c23 MOV	-0xd0(%RBP),%R10

(297) 0x436c2a MOV	(%R10),%RBX

(297) 0x436c2d MOV	-0xd8(%RBP),%R10

(297) 0x436c34 MOV	(%R10),%R14

(297) 0x436c37 MOVSXD	%R9D,%R10

(297) 0x436c3a TEST	%R8,%R8

(297) 0x436c3d JE	436b80

(297) 0x436c43 MOVSXD	%R11D,%R9

(297) 0x436c46 ADD	-0x90(%RBP),%R9

(297) 0x436c4d SUB	-0x68(%RBP),%R10

(297) 0x436c51 MOV	%RAX,%R15

(297) 0x436c54 IMUL	%R10,%R15

(297) 0x436c58 MOV	%RDI,%R12

(297) 0x436c5b IMUL	%R10,%R12

(297) 0x436c5f MOV	%RBX,%R13

(297) 0x436c62 IMUL	%R10,%R13

(297) 0x436c66 IMUL	%R14,%R10

(297) 0x436c6a IMUL	%R9,%R14

(297) 0x436c6e ADD	-0x98(%RBP),%R14

(297) 0x436c75 IMUL	%R9,%RBX

(297) 0x436c79 ADD	-0x88(%RBP),%RBX

(297) 0x436c80 IMUL	%R9,%RDI

(297) 0x436c84 ADD	-0x80(%RBP),%RDI

(297) 0x436c88 IMUL	%RAX,%R9

(297) 0x436c8c ADD	-0x78(%RBP),%R9

(297) 0x436c90 XOR	%EAX,%EAX

(297) 0x436c92 NOPW	%CS:(%RAX,%RAX,1)

  (298) 0x436ca0 VMOVUPS	(%R9,%RAX,8),%ZMM2

  (298) 0x436ca7 VMOVUPS	%ZMM2,(%RDI,%RAX,8)

  (298) 0x436cae VMOVUPD	(%RBX,%RAX,8),%ZMM2

  (298) 0x436cb5 VMOVUPD	%ZMM2,(%R14,%RAX,8)

  (298) 0x436cbc ADD	$0x8,%RAX

  (298) 0x436cc0 CMP	%R8,%RAX

  (298) 0x436cc3 JB	436ca0

(297) 0x436cc5 MOV	%R8,%RAX

(297) 0x436cc8 CMP	-0xa0(%RBP),%R8D

(297) 0x436ccf JNE	436b9f

(297) 0x436cd5 JMP	436bf0

0x436cda NOPW	%CS:(%RAX,%RAX,1)

0x436ce4 NOPW	%CS:(%RAX,%RAX,1)

0x436cee NOPW	%CS:(%RAX,%RAX,1)

0x436cf8 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2

Source file and lines	revert_kernel.f90:41-51
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:41-51.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.17 to 2.00 cycles (10.58x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 21.17 to 1.69 cycles (12.54x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:51
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:45

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:47
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:51

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:47

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 164 bytes. The binary function is storing 172 bytes.

General properties

nb instructions	123
nb uops	127
loop length	567
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	2
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.17 cycles
front end	21.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.80	5.80	10.33	10.33	17.50	5.80	5.80	17.50	17.50	17.50	5.80	10.33
cycles	5.80	8.07	10.33	10.33	17.50	5.80	5.80	17.50	17.50	17.50	5.80	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.17
Dispatch	17.50
Overall L1	21.17

Vectorization ratios

all	4%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	10%
load	8%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.17 cycles. At this rate:

4% of peak load performance is reached (7.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.17 to 17.50 cycles (1.21x speedup).

ASM code

In the binary file, the address of the function is: 436970

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 436a55 <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0xe5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x53c090,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x2c(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 436a80 <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0x110>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x53c0b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53c0d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4047c0 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD (%R12),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RSI),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVGE %EAX,%R9D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %R9D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffff8,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOVSXD %R14D,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %EBX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RDX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2(%RAX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RDX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $-0x2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RDX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RDX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RDX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPMOVSXBQ 0xbf47a(%RIP),%ZMM1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
MOV %RDI,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JMP 436c00 <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0x290>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2

Source file and lines	revert_kernel.f90:41-51
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:51
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:45

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:47
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:51

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:47

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 164 bytes. The binary function is storing 172 bytes.

General properties

nb instructions	123
nb uops	127
loop length	567
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	2
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.17 cycles
front end	21.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.80	5.80	10.33	10.33	17.50	5.80	5.80	17.50	17.50	17.50	5.80	10.33
cycles	5.80	8.07	10.33	10.33	17.50	5.80	5.80	17.50	17.50	17.50	5.80	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.17
Dispatch	17.50
Overall L1	21.17

Vectorization ratios

all	4%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	10%
load	8%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.17 cycles. At this rate:

4% of peak load performance is reached (7.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 436970

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JS 436a55 <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0xe5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x53c090,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x2c(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 436a80 <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0x110>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x53c0b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404070 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x53c0d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4047c0 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD (%R12),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RSI),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVGE %EAX,%R9D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %R9D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffff8,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOVSXD %R14D,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %EBX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RDX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2(%RAX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RDX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $-0x2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RDX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RDX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x10(%RAX,%RDX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPMOVSXBQ 0xbf47a(%RIP),%ZMM1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
MOV %RDI,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JMP 436c00 <revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2+0x290>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼revert_kernel_module_mp_revert_kernel_.DIR.OMP.PARALLEL.2–	2.64	0.98
▼Loop 297 - revert_kernel.f90:44-48 - exec–	0.00	0.00
○Loop 298 - revert_kernel.f90:46-48 - exec	2.64	0.97

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