OV - exec - Function pack_kernel_module_mp_clover_pack_message_left

	Function: pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101	Module: exec	Source: pack_kernel.f90:61-69	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 61 - 69

--------------------------------------------------------------------------------

61:     !$OMP PARALLEL DO PRIVATE(index)

62:     DO k=y_min-depth,y_max+y_inc+depth

63:     !$OMP SIMD

64:       DO j=1,depth

65:         index= buffer_offset + j+(k+depth-1)*depth

66:         left_snd_buffer(index)=field(x_min+x_inc-1+j,k)

67:       ENDDO

68:     ENDDO

69:   !$OMP END PARALLEL DO

0x432350 PUSH	%RBP

0x432351 MOV	%RSP,%RBP

0x432354 PUSH	%R15

0x432356 PUSH	%R14

0x432358 PUSH	%R13

0x43235a PUSH	%R12

0x43235c PUSH	%RBX

0x43235d SUB	$0x48,%RSP

0x432361 MOV	%R8,-0x70(%RBP)

0x432365 MOV	%RCX,-0x48(%RBP)

0x432369 MOV	0x20(%RBP),%RAX

0x43236d MOV	%RAX,-0x68(%RBP)

0x432371 MOV	0x18(%RBP),%RAX

0x432375 MOV	%RAX,-0x58(%RBP)

0x432379 MOV	0x10(%RBP),%RAX

0x43237d MOV	%RAX,-0x60(%RBP)

0x432381 MOV	0x30(%RBP),%EAX

0x432384 MOVL	$0,-0x3c(%RBP)

0x43238b TEST	%EAX,%EAX

0x43238d JS	432440

0x432393 MOV	%R9,%R14

0x432396 MOV	%RDX,%RBX

0x432399 MOV	(%RDI),%ESI

0x43239b MOVL	$0,-0x30(%RBP)

0x4323a2 MOV	%EAX,-0x2c(%RBP)

0x4323a5 MOVL	$0x1,-0x38(%RBP)

0x4323ac SUB	$0x8,%RSP

0x4323b0 LEA	-0x38(%RBP),%RAX

0x4323b4 LEA	-0x3c(%RBP),%RCX

0x4323b8 LEA	-0x30(%RBP),%R8

0x4323bc LEA	-0x2c(%RBP),%R9

0x4323c0 MOV	$0x53b7f0,%EDI

0x4323c5 MOV	%ESI,-0x34(%RBP)

0x4323c8 MOV	$0x22,%EDX

0x4323cd PUSH	$0x1

0x4323cf PUSH	$0x1

0x4323d1 PUSH	%RAX

0x4323d2 CALL	404850 <__kmpc_for_static_init_4@plt>

0x4323d7 ADD	$0x20,%RSP

0x4323db MOV	-0x30(%RBP),%ECX

0x4323de MOV	-0x2c(%RBP),%R13D

0x4323e2 SUB	%ECX,%R13D

0x4323e5 JAE	432480

0x4323eb MOV	$0x53b810,%EDI

0x4323f0 MOV	-0x34(%RBP),%ESI

0x4323f3 ADD	$0x48,%RSP

0x4323f7 POP	%RBX

0x4323f8 POP	%R12

0x4323fa POP	%R13

0x4323fc POP	%R14

0x4323fe POP	%R15

0x432400 POP	%RBP

0x432401 VZEROUPPER

0x432404 JMP	404070

0x432409 NOPW	%CS:(%RAX,%RAX,1)

0x432418 NOPW	%CS:(%RAX,%RAX,1)

0x432427 NOPW	%CS:(%RAX,%RAX,1)

0x432436 NOPW	%CS:(%RAX,%RAX,1)

0x432440 ADD	$0x48,%RSP

0x432444 POP	%RBX

0x432445 POP	%R12

0x432447 POP	%R13

0x432449 POP	%R14

0x43244b POP	%R15

0x43244d POP	%RBP

0x43244e RET

0x43244f NOPW	%CS:(%RAX,%RAX,1)

0x43245e NOPW	%CS:(%RAX,%RAX,1)

0x43246d NOPW	%CS:(%RAX,%RAX,1)

0x43247c NOPL	(%RAX)

0x432480 MOV	%RCX,%RAX

0x432483 MOV	(%R14),%EDX

0x432486 ADD	%EBX,%EAX

0x432488 MOV	%EDX,%ESI

0x43248a AND	$0x7ffffff8,%ESI

0x432490 VPBROADCASTQ	%RDX,%ZMM0

0x432496 MOV	%RAX,-0x50(%RBP)

0x43249a LEA	-0x1(%RDX,%RAX,1),%EDI

0x43249e IMUL	%EDX,%EDI

0x4324a1 XOR	%R8D,%R8D

0x4324a4 VPMOVSXBQ	0xc3eb2(%RIP),%ZMM1

0x4324ae VPMOVSXBD	0xc3ea9(%RIP),%YMM2

0x4324b7 VPTERNLOGD	$-0x1,%ZMM3,%ZMM3,%ZMM3

0x4324be VPMOVSXBQ	0xc3e98(%RIP),%ZMM4

0x4324c8 JMP	4325a2

0x4324cd NOPW	%CS:(%RAX,%RAX,1)

0x4324dc NOPW	%CS:(%RAX,%RAX,1)

0x4324eb NOPW	%CS:(%RAX,%RAX,1)

0x4324fa NOPW	(%RAX,%RAX,1)

(256) 0x432500 ADD	-0x48(%RBP),%R14D

(256) 0x432504 VPBROADCASTD	%R14D,%YMM7

(256) 0x43250a LEA	0x1(%RBX),%RAX

(256) 0x43250e IMUL	%RAX,%R11

(256) 0x432512 LEA	-0x1(%RBX,%RDX,1),%EAX

(256) 0x432516 IMUL	%EDX,%EAX

(256) 0x432519 MOVSXD	%EAX,%RBX

(256) 0x43251c ADD	%R12,%RBX

(256) 0x43251f XOR	%EAX,%EAX

(256) 0x432521 VPBROADCASTQ	%RAX,%ZMM8

(256) 0x432527 VPSUBQ	%ZMM8,%ZMM0,%ZMM9

(256) 0x43252d VPCMPNLEUQ	%ZMM1,%ZMM9,%K1

(256) 0x432534 VPMOVQD	%ZMM8,%YMM8

(256) 0x43253a VPADDD	%YMM7,%YMM8,%YMM7

(256) 0x43253e VPADDD	%YMM2,%YMM7,%YMM7

(256) 0x432542 ADD	%R11,%R9

(256) 0x432545 VPMOVSXDQ	%YMM7,%ZMM7

(256) 0x43254b VPSUBQ	%ZMM3,%ZMM7,%ZMM7

(256) 0x432551 VPMULLQ	%ZMM7,%ZMM6,%ZMM6

(256) 0x432557 VPXOR	%XMM7,%XMM7,%XMM7

(256) 0x43255b KMOVQ	%K1,%K2

(256) 0x432560 VGATHERQPD	(%R9,%ZMM6,1),%ZMM7{%K2}

(256) 0x432567 ADD	%RAX,%RBX

(256) 0x43256a VPBROADCASTQ	%RBX,%ZMM6

(256) 0x432570 VPADDQ	%ZMM1,%ZMM6,%ZMM6

(256) 0x432576 VPMULLQ	%ZMM6,%ZMM5,%ZMM5

(256) 0x43257c VSCATTERQPD	%ZMM7,(%R10,%ZMM5,1){%K1}

(256) 0x432583 JMP	432590

0x432585 NOPW	%CS:(%RAX,%RAX,1)

(256) 0x432590 LEA	0x1(%R8),%EAX

(256) 0x432594 ADD	%EDX,%EDI

(256) 0x432596 CMP	%R13D,%R8D

(256) 0x432599 MOV	%EAX,%R8D

(256) 0x43259c JE	4323eb

(256) 0x4325a2 TEST	%EDX,%EDX

(256) 0x4325a4 JLE	432590

(256) 0x4325a6 MOV	-0x50(%RBP),%RAX

(256) 0x4325aa ADD	%R8D,%EAX

(256) 0x4325ad MOV	-0x70(%RBP),%RCX

(256) 0x4325b1 MOVSXD	(%RCX),%R12

(256) 0x4325b4 MOV	-0x58(%RBP),%R11

(256) 0x4325b8 MOV	(%R11),%R9

(256) 0x4325bb MOV	0x38(%R11),%R10

(256) 0x4325bf MOV	-0x68(%RBP),%RCX

(256) 0x4325c3 MOV	(%RCX),%R14D

(256) 0x4325c6 MOV	0x50(%R11),%R11

(256) 0x4325ca VPBROADCASTQ	%R10,%ZMM6

(256) 0x4325d0 MOV	-0x60(%RBP),%RCX

(256) 0x4325d4 MOV	0x38(%RCX),%R10

(256) 0x4325d8 VPBROADCASTQ	%R10,%ZMM5

(256) 0x4325de MOV	(%RCX),%R10

(256) 0x4325e1 MOVSXD	%EAX,%RBX

(256) 0x4325e4 TEST	%RSI,%RSI

(256) 0x4325e7 JE	432500

(256) 0x4325ed MOVSXD	%EDI,%RAX

(256) 0x4325f0 LEA	0x1(%RBX),%R15

(256) 0x4325f4 IMUL	%R15,%R11

(256) 0x4325f8 LEA	(%R9,%R11,1),%R15

(256) 0x4325fc LEA	-0x1(%RBX,%RDX,1),%EBX

(256) 0x432600 IMUL	%EDX,%EBX

(256) 0x432603 MOVSXD	%EBX,%RBX

(256) 0x432606 ADD	-0x48(%RBP),%R14D

(256) 0x43260a ADD	%R12,%RBX

(256) 0x43260d ADD	%R12,%RAX

(256) 0x432610 XOR	%R12D,%R12D

(256) 0x432613 NOPW	%CS:(%RAX,%RAX,1)

  (257) 0x432620 LEA	(%R14,%R12,1),%ECX

  (257) 0x432624 VPBROADCASTD	%ECX,%YMM7

  (257) 0x43262a VPADDD	%YMM2,%YMM7,%YMM7

  (257) 0x43262e VPMOVSXDQ	%YMM7,%ZMM7

  (257) 0x432634 VPSUBQ	%ZMM3,%ZMM7,%ZMM7

  (257) 0x43263a VPMULLQ	%ZMM7,%ZMM6,%ZMM7

  (257) 0x432640 VXORPD	%XMM8,%XMM8,%XMM8

  (257) 0x432645 KXNORW	%K0,%K0,%K1

  (257) 0x432649 VGATHERQPD	(%R15,%ZMM7,1),%ZMM8{%K1}

  (257) 0x432650 LEA	(%RAX,%R12,1),%RCX

  (257) 0x432654 VPBROADCASTQ	%RCX,%ZMM7

  (257) 0x43265a VPADDQ	%ZMM4,%ZMM7,%ZMM7

  (257) 0x432660 VPMULLQ	%ZMM7,%ZMM5,%ZMM7

  (257) 0x432666 KXNORW	%K0,%K0,%K1

  (257) 0x43266a VSCATTERQPD	%ZMM8,(%R10,%ZMM7,1){%K1}

  (257) 0x432671 ADD	$0x8,%R12

  (257) 0x432675 CMP	%RSI,%R12

  (257) 0x432678 JB	432620

(256) 0x43267a CMP	%EDX,%ESI

(256) 0x43267c JE	432590

(256) 0x432682 VPBROADCASTD	%R14D,%YMM7

(256) 0x432688 MOV	%RSI,%RAX

(256) 0x43268b JMP	432521

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2

Source file and lines	pack_kernel.f90:61-69
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:61-69.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.83 to 4.00 cycles (3.96x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.83 to 11.41 cycles (1.39x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:63

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
VPMOVSXBQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:69

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
VPMOVSXBQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	90
nb uops	95
loop length	443
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	4
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.30	3.20	8.33	8.33	10.50	4.00	3.30	10.50	10.50	10.50	3.20	8.33
cycles	3.30	3.40	8.33	8.33	10.50	4.00	3.30	10.50	10.50	10.50	3.20	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.83
Dispatch	10.50
Overall L1	15.83

Vectorization ratios

all	16%
load	42%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

all	12%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.83 cycles. At this rate:

2% of peak load performance is reached (4.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.83 to 10.50 cycles (1.51x speedup).

ASM code

In the binary file, the address of the function is: 432350

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x48,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 432440 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0xf0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x53b7f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %ECX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 432480 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0x130>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x53b810,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x48,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 404070 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x48,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffff8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
VPBROADCASTQ %RDX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%RDX,%RAX,1),%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPMOVSXBQ 0xc3eb2(%RIP),%ZMM1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0xc3ea9(%RIP),%YMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPTERNLOGD $-0x1,%ZMM3,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVSXBQ 0xc3e98(%RIP),%ZMM4	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
JMP 4325a2 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0x252>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2

Source file and lines	pack_kernel.f90:61-69
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:61-69.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.83 to 4.00 cycles (3.96x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:63

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
VPMOVSXBQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:69

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
VPMOVSXBQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:62
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	90
nb uops	95
loop length	443
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	4
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.30	3.20	8.33	8.33	10.50	4.00	3.30	10.50	10.50	10.50	3.20	8.33
cycles	3.30	3.40	8.33	8.33	10.50	4.00	3.30	10.50	10.50	10.50	3.20	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.83
Dispatch	10.50
Overall L1	15.83

Vectorization ratios

all	16%
load	42%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

all	12%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.83 cycles. At this rate:

2% of peak load performance is reached (4.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 432350

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x48,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 432440 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0xf0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x53b7f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 404850 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %ECX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 432480 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0x130>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x53b810,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x48,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 404070 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x48,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffff8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
VPBROADCASTQ %RDX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%RDX,%RAX,1),%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPMOVSXBQ 0xc3eb2(%RIP),%ZMM1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0xc3ea9(%RIP),%YMM2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPTERNLOGD $-0x1,%ZMM3,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVSXBQ 0xc3e98(%RIP),%ZMM4	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
JMP 4325a2 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101+0x252>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split101–	0.02	0.01
▼Loop 256 - pack_kernel.f90:62-66 - exec–	0.02	0.01
○Loop 257 - pack_kernel.f90:64-66 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code