OV - exec - Loop 82

	Loop Id: 82	Module: exec	Source: advec_cell_kernel.f90:182-183	Coverage: 1.52%

0x41b1b0 VMOVUPD	(%RDX,%RAX,1),%ZMM7    [5]

0x41b1b7 VMOVUPD	(%R9,%RAX,1),%ZMM10    [2]

0x41b1be VADDPD	(%R8,%RAX,1),%ZMM7,%ZMM8    [1]

0x41b1c5 VADDPD	(%RCX,%RAX,1),%ZMM10,%ZMM11    [4]

0x41b1cc VADDPD	(%R11,%RAX,1),%ZMM8,%ZMM9    [6]

0x41b1d3 VSUBPD	%ZMM11,%ZMM9,%ZMM12

0x41b1d9 VMOVUPD	%ZMM12,(%RDI,%RAX,1)    [7]

0x41b1e0 VMOVUPD	(%RCX,%RAX,1),%ZMM13    [4]

0x41b1e7 VSUBPD	(%RDX,%RAX,1),%ZMM13,%ZMM14    [5]

0x41b1ee VADDPD	%ZMM12,%ZMM14,%ZMM15

0x41b1f4 VMOVUPD	%ZMM15,(%RSI,%RAX,1)    [3]

0x41b1fb VMOVUPD	0x40(%RDX,%RAX,1),%ZMM0    [5]

0x41b203 VMOVUPD	0x40(%R9,%RAX,1),%ZMM1    [2]

0x41b20b VADDPD	0x40(%R8,%RAX,1),%ZMM0,%ZMM2    [1]

0x41b213 VADDPD	0x40(%RCX,%RAX,1),%ZMM1,%ZMM4    [4]

0x41b21b VADDPD	0x40(%R11,%RAX,1),%ZMM2,%ZMM3    [6]

0x41b223 VSUBPD	%ZMM4,%ZMM3,%ZMM5

0x41b229 VMOVUPD	%ZMM5,0x40(%RDI,%RAX,1)    [7]

0x41b231 VMOVUPD	0x40(%RCX,%RAX,1),%ZMM6    [4]

0x41b239 VSUBPD	0x40(%RDX,%RAX,1),%ZMM6,%ZMM7    [5]

0x41b241 VADDPD	%ZMM5,%ZMM7,%ZMM8

0x41b247 VMOVUPD	%ZMM8,0x40(%RSI,%RAX,1)    [3]

0x41b24f VMOVUPD	0x80(%RDX,%RAX,1),%ZMM9    [5]

0x41b257 VMOVUPD	0x80(%R9,%RAX,1),%ZMM12    [2]

0x41b25f VADDPD	0x80(%R8,%RAX,1),%ZMM9,%ZMM10    [1]

0x41b267 VADDPD	0x80(%RCX,%RAX,1),%ZMM12,%ZMM13    [4]

0x41b26f VADDPD	0x80(%R11,%RAX,1),%ZMM10,%ZMM11    [6]

0x41b277 VSUBPD	%ZMM13,%ZMM11,%ZMM14

0x41b27d VMOVUPD	%ZMM14,0x80(%RDI,%RAX,1)    [7]

0x41b285 VMOVUPD	0x80(%RCX,%RAX,1),%ZMM15    [4]

0x41b28d VSUBPD	0x80(%RDX,%RAX,1),%ZMM15,%ZMM0    [5]

0x41b295 VADDPD	%ZMM14,%ZMM0,%ZMM2

0x41b29b VMOVUPD	%ZMM2,0x80(%RSI,%RAX,1)    [3]

0x41b2a3 VMOVUPD	0xc0(%RDX,%RAX,1),%ZMM3    [5]

0x41b2ab VMOVUPD	0xc0(%R9,%RAX,1),%ZMM5    [2]

0x41b2b3 VADDPD	0xc0(%R8,%RAX,1),%ZMM3,%ZMM1    [1]

0x41b2bb VADDPD	0xc0(%RCX,%RAX,1),%ZMM5,%ZMM6    [4]

0x41b2c3 VADDPD	0xc0(%R11,%RAX,1),%ZMM1,%ZMM4    [6]

0x41b2cb VSUBPD	%ZMM6,%ZMM4,%ZMM7

0x41b2d1 VMOVUPD	%ZMM7,0xc0(%RDI,%RAX,1)    [7]

0x41b2d9 VMOVUPD	0xc0(%RCX,%RAX,1),%ZMM8    [4]

0x41b2e1 VSUBPD	0xc0(%RDX,%RAX,1),%ZMM8,%ZMM9    [5]

0x41b2e9 VADDPD	%ZMM7,%ZMM9,%ZMM10

0x41b2ef VMOVUPD	%ZMM10,0xc0(%RSI,%RAX,1)    [3]

0x41b2f7 ADD	$0x100,%RAX

0x41b2fd CMP	%RAX,%R10

0x41b300 JNE	41b1b0

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 182 - 183

--------------------------------------------------------------------------------

182:             pre_vol(j,k)=volume(j,k)+(vol_flux_y(j  ,k+1)-vol_flux_y(j,k)+vol_flux_x(j+1,k  )-vol_flux_x(j,k))

183:             post_vol(j,k)=pre_vol(j,k)-(vol_flux_y(j  ,k+1)-vol_flux_y(j,k))

Coverage (%)	Name	Source Location	Module
○97.55	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.45	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks	P0, P1, P5,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:182-183
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	10.33
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	9.33
P3 cycles	9.33
P4 cycles	4.00
P5 cycles	12.00
P6 cycles	1.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.40
P11 cycles	9.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	46.00
Nb loads	28.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	16.00
Nb FLOP add-sub	192.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	192.00
Bytes prefetched	0.00
Bytes loaded	1792.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks	P0, P1, P5,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:182-183
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	10.33
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	9.33
P3 cycles	9.33
P4 cycles	4.00
P5 cycles	12.00
P6 cycles	1.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.40
P11 cycles	9.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	46.00
Nb loads	28.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	16.00
Nb FLOP add-sub	192.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	192.00
Bytes prefetched	0.00
Bytes loaded	1792.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:182-183
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:182-183.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.33 cycles (1.16x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

192: addition or subtraction

The binary loop is loading 1792 bytes (224 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	47
nb uops	46
loop length	342
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.33 cycles
front end	10.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.00	0.60	9.33	9.33	4.00	12.00	1.00	4.00	4.00	4.00	0.40	9.33
cycles	12.00	12.00	9.33	9.33	4.00	12.00	1.00	4.00	4.00	4.00	0.40	9.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.33
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

77% of peak load performance is reached (149.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (42.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41b1b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RDX,%RAX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%R8,%RAX,1),%ZMM7,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R11,%RAX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD %ZMM11,%ZMM9,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM12,(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%RCX,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%RDX,%RAX,1),%ZMM13,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM12,%ZMM14,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM15,(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RDX,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R9,%RAX,1),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0x40(%R8,%RAX,1),%ZMM0,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%RCX,%RAX,1),%ZMM1,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%R11,%RAX,1),%ZMM2,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD %ZMM4,%ZMM3,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM5,0x40(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RCX,%RAX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD 0x40(%RDX,%RAX,1),%ZMM6,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM5,%ZMM7,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM8,0x40(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%RDX,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x80(%R9,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0x80(%R8,%RAX,1),%ZMM9,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x80(%RCX,%RAX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x80(%R11,%RAX,1),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD %ZMM13,%ZMM11,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM14,0x80(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%RCX,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD 0x80(%RDX,%RAX,1),%ZMM15,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM14,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x80(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%RDX,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0xc0(%R9,%RAX,1),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0xc0(%R8,%RAX,1),%ZMM3,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0xc0(%RCX,%RAX,1),%ZMM5,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0xc0(%R11,%RAX,1),%ZMM1,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD %ZMM6,%ZMM4,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM7,0xc0(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD 0xc0(%RDX,%RAX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM7,%ZMM9,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM10,0xc0(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x100,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 41b1b0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x1fb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:182-183
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

192: addition or subtraction

The binary loop is loading 1792 bytes (224 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	47
nb uops	46
loop length	342
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.33 cycles
front end	10.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.00	0.60	9.33	9.33	4.00	12.00	1.00	4.00	4.00	4.00	0.40	9.33
cycles	12.00	12.00	9.33	9.33	4.00	12.00	1.00	4.00	4.00	4.00	0.40	9.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.33
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

77% of peak load performance is reached (149.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (42.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41b1b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RDX,%RAX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%R8,%RAX,1),%ZMM7,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R11,%RAX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD %ZMM11,%ZMM9,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM12,(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%RCX,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%RDX,%RAX,1),%ZMM13,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM12,%ZMM14,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM15,(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RDX,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R9,%RAX,1),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0x40(%R8,%RAX,1),%ZMM0,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%RCX,%RAX,1),%ZMM1,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%R11,%RAX,1),%ZMM2,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD %ZMM4,%ZMM3,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM5,0x40(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RCX,%RAX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD 0x40(%RDX,%RAX,1),%ZMM6,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM5,%ZMM7,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM8,0x40(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%RDX,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x80(%R9,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0x80(%R8,%RAX,1),%ZMM9,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x80(%RCX,%RAX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x80(%R11,%RAX,1),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD %ZMM13,%ZMM11,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM14,0x80(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%RCX,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD 0x80(%RDX,%RAX,1),%ZMM15,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM14,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x80(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%RDX,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0xc0(%R9,%RAX,1),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0xc0(%R8,%RAX,1),%ZMM3,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0xc0(%RCX,%RAX,1),%ZMM5,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0xc0(%R11,%RAX,1),%ZMM1,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD %ZMM6,%ZMM4,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM7,0xc0(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD 0xc0(%RDX,%RAX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM7,%ZMM9,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM10,0xc0(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x100,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 41b1b0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x1fb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code