OV - exec - Loop 80

	Loop Id: 80	Module: exec	Source: advec_cell_kernel.f90:202-246 [...]	Coverage: 3.72%

0x419ad8 MOV	0x128(%RSP),%RSI    [9]

0x419ae0 MOVSXD	0xd8(%RSP),%RCX    [9]

0x419ae8 MOV	0x120(%RSP),%R9    [9]

0x419af0 MOV	%RSI,%RDX

0x419af3 MOV	0x138(%RSP),%RDI    [9]

0x419afb MOV	0x100(%RSP),%R8    [9]

0x419b03 IMUL	%RDX,%RDI

0x419b07 MOV	0x130(%RSP),%R10    [9]

0x419b0f VANDPD	%XMM15,%XMM9,%XMM0

0x419b14 ADD	%R8,%RDI

0x419b17 ADD	%RAX,%RDI

0x419b1a MOV	0xe8(%RSP),%R8    [9]

0x419b22 VDIVSD	(%R10,%RDI,8),%XMM0,%XMM3    [4]

0x419b28 VMOVSD	(%R13),%XMM2    [6]

0x419b2e MOV	0xe0(%RSP),%R10    [9]

0x419b36 ADD	%R8,%RSI

0x419b39 VDIVSD	(%R10,%RSI,8),%XMM2,%XMM1    [3]

0x419b3f MOV	%R14,%RSI

0x419b42 IMUL	%RDX,%RSI

0x419b46 MOV	%R14,%R10

0x419b49 IMUL	%RCX,%R10

0x419b4d ADD	%R15,%RSI

0x419b50 ADD	%RAX,%RSI

0x419b53 VMOVSD	(%R11,%RSI,8),%XMM11    [5]

0x419b59 LEA	(%R15,%RAX,1),%R8

0x419b5d ADD	%R8,%R10

0x419b60 VSUBSD	(%R11,%R10,8),%XMM11,%XMM0    [5]

0x419b66 MOV	%R14,%R10

0x419b69 IMUL	%R9,%R10

0x419b6d VADDSD	%XMM5,%XMM3,%XMM10

0x419b71 VSUBSD	%XMM3,%XMM8,%XMM13

0x419b75 ADD	%R10,%R8

0x419b78 VMOVSD	(%R11,%R8,8),%XMM12    [5]

0x419b7e VMULSD	%XMM10,%XMM1,%XMM10

0x419b83 VSUBSD	%XMM11,%XMM12,%XMM2

0x419b88 VMULSD	%XMM0,%XMM2,%XMM12

0x419b8c VCMPSD	$0x6,%XMM4,%XMM2,%XMM14

0x419b91 VBLENDVPD	%XMM14,%XMM5,%XMM7,%XMM1

0x419b97 VCOMISD	%XMM4,%XMM12

0x419b9b JBE	419bcb

0x419b9d VANDPD	%XMM15,%XMM2,%XMM2

0x419ba2 VMULSD	%XMM13,%XMM2,%XMM12

0x419ba7 VANDPD	%XMM15,%XMM0,%XMM0

0x419bac VMINSD	%XMM2,%XMM0,%XMM14

0x419bb0 VSUBSD	%XMM3,%XMM5,%XMM3

0x419bb4 VFMADD132SD	%XMM10,%XMM12,%XMM0

0x419bb9 VMULSD	%XMM6,%XMM0,%XMM2

0x419bbd VMINSD	%XMM14,%XMM2,%XMM0

0x419bc2 VMULSD	%XMM3,%XMM0,%XMM14

0x419bc6 VFMADD231SD	%XMM1,%XMM14,%XMM11

0x419bcb VMULSD	%XMM9,%XMM11,%XMM9

0x419bd0 IMUL	%R12,%RDX

0x419bd4 IMUL	%R12,%RCX

0x419bd8 IMUL	%R12,%R9

0x419bdc MOV	0xf8(%RSP),%R10    [9]

0x419be4 MOV	0x108(%RSP),%R8    [9]

0x419bec ADD	%RAX,%R10

0x419bef VMOVSD	%XMM9,(%R8,%RAX,8)    [8]

0x419bf5 ADD	%R10,%RDX

0x419bf8 ADD	%R10,%RCX

0x419bfb ADD	%R9,%R10

0x419bfe VMOVSD	(%RBX,%RDX,8),%XMM1    [10]

0x419c03 VMOVSD	(%RBX,%R10,8),%XMM11    [10]

0x419c09 VSUBSD	(%RBX,%RCX,8),%XMM1,%XMM2    [10]

0x419c0e VSUBSD	%XMM1,%XMM11,%XMM0

0x419c12 VMULSD	%XMM2,%XMM0,%XMM14

0x419c16 VCMPSD	$0x6,%XMM4,%XMM0,%XMM12

0x419c1b VBLENDVPD	%XMM12,%XMM5,%XMM7,%XMM3

0x419c21 VCOMISD	%XMM4,%XMM14

0x419c25 JBE	419c74

0x419c27 MOV	0x130(%RSP),%RDX    [9]

0x419c2f VANDPD	%XMM15,%XMM0,%XMM0

0x419c34 VMOVSD	(%RDX,%RDI,8),%XMM11    [7]

0x419c39 VMULSD	%XMM13,%XMM0,%XMM13

0x419c3e VMULSD	(%R11,%RSI,8),%XMM11,%XMM12    [5]

0x419c44 VANDPD	%XMM15,%XMM2,%XMM2

0x419c49 VMINSD	%XMM0,%XMM2,%XMM14

0x419c4d VFMADD132SD	%XMM10,%XMM13,%XMM2

0x419c52 VANDPD	%XMM15,%XMM9,%XMM10

0x419c57 VDIVSD	%XMM12,%XMM10,%XMM11

0x419c5c VMULSD	%XMM6,%XMM2,%XMM2

0x419c60 VMINSD	%XMM14,%XMM2,%XMM14

0x419c65 VSUBSD	%XMM11,%XMM5,%XMM0

0x419c6a VMULSD	%XMM14,%XMM0,%XMM13

0x419c6f VFMADD231SD	%XMM3,%XMM13,%XMM1

0x419c74 VMULSD	%XMM9,%XMM1,%XMM9

0x419c79 MOV	0x110(%RSP),%RCX    [9]

0x419c81 VMOVSD	%XMM9,(%RCX,%RAX,8)    [1]

0x419c86 INC	%RAX

0x419c89 CMP	%EAX,0x118(%RSP)    [9]

0x419c90 JL	41b620

0x419c96 MOV	0xf0(%RSP),%RCX    [9]

0x419c9e VMOVSD	(%RCX,%RAX,8),%XMM9    [2]

0x419ca3 VCOMISD	%XMM4,%XMM9

0x419ca7 JA	419ad8

0x419cad MOV	0xc0(%RSP),%RCX    [9]

0x419cb5 MOV	0x128(%RSP),%R9    [9]

0x419cbd MOV	0x120(%RSP),%RDX    [9]

0x419cc5 MOV	%RCX,%RSI

0x419cc8 JMP	419af3

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 202 - 246

--------------------------------------------------------------------------------

202:         DO j=x_min,x_max

203:

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

Coverage (%)	Name	Source Location	Module
○97.60	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.40	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	2.65
CQA speedup if fully vectorized	3.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P0,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:216-246
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.50
CQA cycles if no scalar integer	16.17
CQA cycles if FP arith vectorized	6.98
CQA cycles if fully vectorized	6.00
Front-end cycles	18.17
P0 cycles	18.50
P1 cycles	18.17
P2 cycles	9.67
P3 cycles	9.67
P4 cycles	1.00
P5 cycles	18.33
P6 cycles	8.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	8.00
P11 cycles	9.67
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	104.00
Nb loads	29.00
Nb stores	2.00
Nb stack references	14.00
FLOP/cycle	1.68
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	4.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.97
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	47.06
Vector-efficiency ratio all	14.29
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.38

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	2.65
CQA speedup if fully vectorized	3.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P0,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:216-246
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.50
CQA cycles if no scalar integer	16.17
CQA cycles if FP arith vectorized	6.98
CQA cycles if fully vectorized	6.00
Front-end cycles	18.17
P0 cycles	18.50
P1 cycles	18.17
P2 cycles	9.67
P3 cycles	9.67
P4 cycles	1.00
P5 cycles	18.33
P6 cycles	8.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	8.00
P11 cycles	9.67
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	104.00
Nb loads	29.00
Nb stores	2.00
Nb stack references	14.00
FLOP/cycle	1.68
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	4.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.97
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	47.06
Vector-efficiency ratio all	14.29
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202-204,216-246.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.50 to 16.17 cycles (1.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 18.50 to 6.00 cycles (3.08x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:225
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:238

Type of elements and instruction set

36 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

12: addition or subtraction (4 inside FMA instructions)
16: multiply (4 inside FMA instructions)
3: divide

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	100
nb uops	104
loop length	501
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	14
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.17 cycles
front end	18.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.50	18.17	9.67	9.67	1.00	18.33	8.00	1.00	1.00	1.00	8.00	9.67
cycles	18.50	18.17	9.67	9.67	1.00	18.33	8.00	1.00	1.00	1.00	8.00	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	18.17
Dispatch	18.50
DIV/SQRT	12.00
Overall L1	18.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	47%

INT+FP

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	47%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.50 cycles. At this rate:

6% of peak load performance is reached (12.11 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 419c96

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x128(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD 0xd8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x120(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x138(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x100(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x130(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VANDPD %XMM15,%XMM9,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ADD %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xe8(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVSD (%R10,%RDI,8),%XMM0,%XMM3	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VMOVSD (%R13),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe0(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VDIVSD (%R10,%RSI,8),%XMM2,%XMM1	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%RSI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R15,%RAX,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VSUBSD (%R11,%R10,8),%XMM11,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
MOV %R14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VADDSD %XMM5,%XMM3,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM8,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
ADD %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%R8,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM10,%XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM11,%XMM12,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM2,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x6,%XMM4,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDVPD %XMM14,%XMM5,%XMM7,%XMM1	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VCOMISD %XMM4,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 419bcb <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x9cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM15,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULSD %XMM13,%XMM2,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM2,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM5,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM10,%XMM12,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM14,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM14,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM9,%XMM11,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL %R12,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %R12,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0xf8(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x108(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM9,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RBX,%RDX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RBX,%R10,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD (%RBX,%RCX,8),%XMM1,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM11,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x6,%XMM4,%XMM0,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDVPD %XMM12,%XMM5,%XMM7,%XMM3	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VCOMISD %XMM4,%XMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 419c74 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xa74>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x130(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VANDPD %XMM15,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVSD (%RDX,%RDI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM13,%XMM0,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD (%R11,%RSI,8),%XMM11,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM0,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM10,%XMM13,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VDIVSD %XMM12,%XMM10,%XMM11	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM6,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM14,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM11,%XMM5,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM0,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM3,%XMM13,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM9,%XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x110(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM9,(%RCX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,0x118(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JL 41b620 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x2420>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xf0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM4,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 419ad8 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x8d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x128(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x120(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 419af3 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x8f3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:225
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:238

Type of elements and instruction set

36 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

12: addition or subtraction (4 inside FMA instructions)
16: multiply (4 inside FMA instructions)
3: divide

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	100
nb uops	104
loop length	501
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	14
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.17 cycles
front end	18.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.50	18.17	9.67	9.67	1.00	18.33	8.00	1.00	1.00	1.00	8.00	9.67
cycles	18.50	18.17	9.67	9.67	1.00	18.33	8.00	1.00	1.00	1.00	8.00	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	18.17
Dispatch	18.50
DIV/SQRT	12.00
Overall L1	18.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	47%

INT+FP

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	47%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.50 cycles. At this rate:

6% of peak load performance is reached (12.11 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 419c96

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x128(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD 0xd8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x120(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x138(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x100(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x130(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VANDPD %XMM15,%XMM9,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ADD %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xe8(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVSD (%R10,%RDI,8),%XMM0,%XMM3	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VMOVSD (%R13),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe0(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VDIVSD (%R10,%RSI,8),%XMM2,%XMM1	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%RSI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R15,%RAX,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VSUBSD (%R11,%R10,8),%XMM11,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
MOV %R14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VADDSD %XMM5,%XMM3,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM8,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
ADD %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%R8,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM10,%XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM11,%XMM12,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM2,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x6,%XMM4,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDVPD %XMM14,%XMM5,%XMM7,%XMM1	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VCOMISD %XMM4,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 419bcb <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x9cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM15,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULSD %XMM13,%XMM2,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM2,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM5,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM10,%XMM12,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM14,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM14,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM9,%XMM11,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL %R12,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %R12,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0xf8(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x108(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM9,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RBX,%RDX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RBX,%R10,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD (%RBX,%RCX,8),%XMM1,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM11,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x6,%XMM4,%XMM0,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDVPD %XMM12,%XMM5,%XMM7,%XMM3	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VCOMISD %XMM4,%XMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 419c74 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xa74>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x130(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VANDPD %XMM15,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVSD (%RDX,%RDI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM13,%XMM0,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD (%R11,%RSI,8),%XMM11,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM0,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM10,%XMM13,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VDIVSD %XMM12,%XMM10,%XMM11	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM6,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM14,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM11,%XMM5,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM0,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM3,%XMM13,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM9,%XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x110(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM9,(%RCX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,0x118(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JL 41b620 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x2420>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xf0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM4,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 419ad8 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x8d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x128(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x120(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 419af3 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x8f3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code