OV - exec - Loop 72

	Loop Id: 72	Module: exec	Source: advec_cell_kernel.f90:110-155 [...]	Coverage: 3.78%

0x41a498 LEA	-0x1(%RAX),%RDX

0x41a49c LEA	-0x2(%RAX),%EBX

0x41a49f MOVSXD	%EBX,%RCX

0x41a4a2 MOV	%RDX,%R11

0x41a4a5 MOV	0x110(%RSP),%R12    [8]

0x41a4ad VMOVSD	(%R15,%RAX,8),%XMM1    [6]

0x41a4b3 ADD	%R12,%R11

0x41a4b6 MOV	0x128(%RSP),%RBX    [8]

0x41a4be MOV	0x108(%RSP),%R12    [8]

0x41a4c6 ADD	%RDX,%RBX

0x41a4c9 VDIVSD	(%R12,%R11,8),%XMM1,%XMM12    [2]

0x41a4cf VANDPD	%XMM15,%XMM11,%XMM10

0x41a4d4 LEA	(%R8,%RDX,1),%R11

0x41a4d8 VDIVSD	(%R14,%RBX,8),%XMM10,%XMM3    [3]

0x41a4de VMOVSD	(%RDI,%R11,8),%XMM10    [9]

0x41a4e4 LEA	(%R8,%RCX,1),%R12

0x41a4e8 VSUBSD	(%RDI,%R12,8),%XMM10,%XMM0    [9]

0x41a4ee LEA	(%R8,%RSI,1),%R12

0x41a4f2 VMOVSD	(%RDI,%R12,8),%XMM2    [9]

0x41a4f8 VADDSD	%XMM5,%XMM3,%XMM14

0x41a4fc VSUBSD	%XMM10,%XMM2,%XMM1

0x41a501 VSUBSD	%XMM3,%XMM9,%XMM13

0x41a505 VMULSD	%XMM14,%XMM12,%XMM8

0x41a50a VMULSD	%XMM0,%XMM1,%XMM14

0x41a50e VCMPSD	$0x6,%XMM4,%XMM1,%XMM12

0x41a513 VBLENDVPD	%XMM12,%XMM5,%XMM7,%XMM12

0x41a519 VCOMISD	%XMM4,%XMM14

0x41a51d JBE	41a54c

0x41a51f VANDPD	%XMM15,%XMM1,%XMM2

0x41a524 VMULSD	%XMM13,%XMM2,%XMM14

0x41a529 VANDPD	%XMM15,%XMM0,%XMM0

0x41a52e VMINSD	%XMM2,%XMM0,%XMM1

0x41a532 VSUBSD	%XMM3,%XMM5,%XMM3

0x41a536 VFMADD132SD	%XMM8,%XMM14,%XMM0

0x41a53b VMULSD	%XMM6,%XMM0,%XMM2

0x41a53f VMINSD	%XMM1,%XMM2,%XMM0

0x41a543 VMULSD	%XMM3,%XMM0,%XMM1

0x41a547 VFMADD231SD	%XMM12,%XMM1,%XMM10

0x41a54c VMULSD	%XMM11,%XMM10,%XMM10

0x41a551 MOV	0x118(%RSP),%R12    [8]

0x41a559 ADD	%R9,%RDX

0x41a55c ADD	%R9,%RSI

0x41a55f ADD	%R9,%RCX

0x41a562 VMOVSD	%XMM10,(%R12,%RAX,8)    [1]

0x41a568 VMOVSD	(%R10,%RDX,8),%XMM3    [5]

0x41a56e VMOVSD	(%R10,%RSI,8),%XMM11    [5]

0x41a574 VSUBSD	(%R10,%RCX,8),%XMM3,%XMM14    [5]

0x41a57a VSUBSD	%XMM3,%XMM11,%XMM2

0x41a57e VMULSD	%XMM14,%XMM2,%XMM0

0x41a583 VCMPSD	$0x6,%XMM4,%XMM2,%XMM12

0x41a588 VBLENDVPD	%XMM12,%XMM5,%XMM7,%XMM1

0x41a58e VCOMISD	%XMM4,%XMM0

0x41a592 JBE	41a5da

0x41a594 VANDPD	%XMM15,%XMM2,%XMM12

0x41a599 VMOVSD	(%R14,%RBX,8),%XMM11    [3]

0x41a59f VMULSD	%XMM13,%XMM12,%XMM13

0x41a5a4 VMULSD	(%RDI,%R11,8),%XMM11,%XMM0    [9]

0x41a5aa VANDPD	%XMM15,%XMM14,%XMM2

0x41a5af VMINSD	%XMM12,%XMM2,%XMM14

0x41a5b4 VFMADD132SD	%XMM8,%XMM13,%XMM2

0x41a5b9 VANDPD	%XMM15,%XMM10,%XMM8

0x41a5be VDIVSD	%XMM0,%XMM8,%XMM11

0x41a5c2 VMULSD	%XMM6,%XMM2,%XMM2

0x41a5c6 VMINSD	%XMM14,%XMM2,%XMM14

0x41a5cb VSUBSD	%XMM11,%XMM5,%XMM12

0x41a5d0 VMULSD	%XMM14,%XMM12,%XMM13

0x41a5d5 VFMADD231SD	%XMM1,%XMM13,%XMM3

0x41a5da VMULSD	%XMM10,%XMM3,%XMM10

0x41a5df MOV	0x120(%RSP),%RSI    [8]

0x41a5e7 VMOVSD	%XMM10,(%RSI,%RAX,8)    [7]

0x41a5ec INC	%RAX

0x41a5ef CMP	%EAX,%R13D

0x41a5f2 JL	41a630

0x41a5f4 MOV	0x130(%RSP),%RDX    [8]

0x41a5fc MOV	%RAX,%RSI

0x41a5ff VMOVSD	(%RDX,%RAX,8),%XMM11    [4]

0x41a604 VCOMISD	%XMM4,%XMM11

0x41a608 JA	41a498

0x41a60e LEA	0x1(%RAX),%R11D

0x41a612 CMP	%R13D,%R11D

0x41a615 CMOVG	%R13D,%R11D

0x41a619 MOV	%RAX,%RDX

0x41a61c MOVSXD	%R11D,%R11

0x41a61f MOV	%R11,%RCX

0x41a622 LEA	-0x1(%RAX),%RSI

0x41a626 JMP	41a4a5

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 110 - 155

--------------------------------------------------------------------------------

110:         DO j=x_min,x_max+2

111:

112:           IF(vol_flux_x(j,k).GT.0.0)THEN

113:             upwind   =j-2

114:             donor    =j-1

115:             downwind =j

116:             dif      =donor

117:           ELSE

118:             upwind   =MIN(j+1,x_max+2)

[...]

124:           sigmat=ABS(vol_flux_x(j,k))/pre_vol(donor,k)

125:           sigma3=(1.0_8+sigmat)*(vertexdx(j)/vertexdx(dif))

126:           sigma4=2.0_8-sigmat

127:

128:           sigma=sigmat

129:           sigmav=sigmat

130:

131:           diffuw=density1(donor,k)-density1(upwind,k)

132:           diffdw=density1(downwind,k)-density1(donor,k)

133:           wind=1.0_8

134:           IF(diffdw.LE.0.0) wind=-1.0_8

135:           IF(diffuw*diffdw.GT.0.0)THEN

136:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

137:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

138:           ELSE

139:             limiter=0.0

140:           ENDIF

141:           mass_flux_x(j,k)=vol_flux_x(j,k)*(density1(donor,k)+limiter)

142:

143:           sigmam=ABS(mass_flux_x(j,k))/(density1(donor,k)*pre_vol(donor,k))

144:           diffuw=energy1(donor,k)-energy1(upwind,k)

145:           diffdw=energy1(downwind,k)-energy1(donor,k)

146:           wind=1.0_8

147:           IF(diffdw.LE.0.0) wind=-1.0_8

148:           IF(diffuw*diffdw.GT.0.0)THEN

149:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

150:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

151:           ELSE

152:             limiter=0.0

153:           ENDIF

154:

155:           ener_flux(j,k)=mass_flux_x(j,k)*(energy1(donor,k)+limiter)

Coverage (%)	Name	Source Location	Module
○97.61	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.48
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P0, P1, P5,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:110-118,advec_cell_kernel.f90:124-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	6.46
CQA cycles if fully vectorized	6.00
Front-end cycles	15.83
P0 cycles	16.00
P1 cycles	16.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	1.00
P5 cycles	16.00
P6 cycles	8.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	8.00
P11 cycles	6.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	86.00
Nb uops	90.00
Nb loads	18.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	1.94
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	4.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.81
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	44.44
Vector-efficiency ratio all	14.24
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.71

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.48
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P0, P1, P5,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:110-118,advec_cell_kernel.f90:124-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	6.46
CQA cycles if fully vectorized	6.00
Front-end cycles	15.83
P0 cycles	16.00
P1 cycles	16.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	1.00
P5 cycles	16.00
P6 cycles	8.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	8.00
P11 cycles	6.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	86.00
Nb uops	90.00
Nb loads	18.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	1.94
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	4.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.81
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	44.44
Vector-efficiency ratio all	14.24
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.71

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:110-155
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110-118,124-155.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 16.00 to 6.00 cycles (2.67x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:133
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:146

Type of elements and instruction set

36 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

12: addition or subtraction (4 inside FMA instructions)
16: multiply (4 inside FMA instructions)
3: divide

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	86
nb uops	90
loop length	403
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.00	16.00	6.00	6.00	1.00	16.00	8.00	1.00	1.00	1.00	8.00	6.00
cycles	16.00	16.00	6.00	6.00	1.00	16.00	8.00	1.00	1.00	1.00	8.00	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.83
Dispatch	16.00
DIV/SQRT	12.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	47%

INT+FP

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	44%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

4% of peak load performance is reached (9.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a5f4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA -0x1(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2(%RAX),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EBX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x110(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R15,%RAX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R12,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x128(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x108(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VDIVSD (%R12,%R11,8),%XMM1,%XMM12	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VANDPD %XMM15,%XMM11,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
LEA (%R8,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VDIVSD (%R14,%RBX,8),%XMM10,%XMM3	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VMOVSD (%RDI,%R11,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R8,%RCX,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VSUBSD (%RDI,%R12,8),%XMM10,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
LEA (%R8,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%RDI,%R12,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM5,%XMM3,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM10,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM9,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM12,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM1,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x6,%XMM4,%XMM1,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDVPD %XMM12,%XMM5,%XMM7,%XMM12	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VCOMISD %XMM4,%XMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 41a54c <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x134c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM15,%XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULSD %XMM13,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM2,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM5,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM8,%XMM14,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM1,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM11,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x118(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM10,(%R12,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10,%RDX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R10,%RSI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD (%R10,%RCX,8),%XMM3,%XMM14	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM11,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x6,%XMM4,%XMM2,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDVPD %XMM12,%XMM5,%XMM7,%XMM1	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VCOMISD %XMM4,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 41a5da <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x13da>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM15,%XMM2,%XMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVSD (%R14,%RBX,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM13,%XMM12,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD (%RDI,%R11,8),%XMM11,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM14,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM12,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM8,%XMM13,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM10,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VDIVSD %XMM0,%XMM8,%XMM11	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM6,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM14,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM11,%XMM5,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM12,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM13,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM10,%XMM3,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x120(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM10,(%RSI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 41a630 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x1430>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x130(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX,%RAX,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM4,%XMM11	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 41a498 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x1298>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RAX),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R13D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVG %R13D,%R11D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R11D,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41a4a5 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x12a5>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:110-155
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:133
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:146

Type of elements and instruction set

36 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

12: addition or subtraction (4 inside FMA instructions)
16: multiply (4 inside FMA instructions)
3: divide

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	86
nb uops	90
loop length	403
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.00	16.00	6.00	6.00	1.00	16.00	8.00	1.00	1.00	1.00	8.00	6.00
cycles	16.00	16.00	6.00	6.00	1.00	16.00	8.00	1.00	1.00	1.00	8.00	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.83
Dispatch	16.00
DIV/SQRT	12.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	47%

INT+FP

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	44%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

4% of peak load performance is reached (9.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a5f4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA -0x1(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2(%RAX),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EBX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x110(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R15,%RAX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R12,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x128(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x108(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VDIVSD (%R12,%R11,8),%XMM1,%XMM12	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VANDPD %XMM15,%XMM11,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
LEA (%R8,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VDIVSD (%R14,%RBX,8),%XMM10,%XMM3	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VMOVSD (%RDI,%R11,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R8,%RCX,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VSUBSD (%RDI,%R12,8),%XMM10,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
LEA (%R8,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%RDI,%R12,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM5,%XMM3,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM10,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM9,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM12,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM1,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x6,%XMM4,%XMM1,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDVPD %XMM12,%XMM5,%XMM7,%XMM12	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VCOMISD %XMM4,%XMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 41a54c <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x134c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM15,%XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULSD %XMM13,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM2,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM5,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM8,%XMM14,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM1,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM11,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x118(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM10,(%R12,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10,%RDX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R10,%RSI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD (%R10,%RCX,8),%XMM3,%XMM14	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM11,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x6,%XMM4,%XMM2,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDVPD %XMM12,%XMM5,%XMM7,%XMM1	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VCOMISD %XMM4,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 41a5da <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x13da>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM15,%XMM2,%XMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVSD (%R14,%RBX,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM13,%XMM12,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD (%RDI,%R11,8),%XMM11,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM14,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM12,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM8,%XMM13,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM15,%XMM10,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VDIVSD %XMM0,%XMM8,%XMM11	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM6,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM14,%XMM2,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM11,%XMM5,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM12,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM13,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM10,%XMM3,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x120(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM10,(%RSI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 41a630 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x1430>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x130(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX,%RAX,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM4,%XMM11	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 41a498 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x1298>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RAX),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R13D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVG %R13D,%R11D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R11D,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41a4a5 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x12a5>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

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Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code