OV - exec - Loop 70

	Loop Id: 70	Module: exec	Source: advec_cell_kernel.f90:165-170	Coverage: 3.74%

0x41a99a VMOVUPD	(%RBX,%RAX,1),%ZMM11    [9]

0x41a9a1 VMOVUPD	(%R10,%RAX,1),%ZMM13    [5]

0x41a9a8 VMULPD	(%RCX,%RAX,1),%ZMM11,%ZMM12    [4]

0x41a9af VSUBPD	(%RDI,%RAX,1),%ZMM13,%ZMM10    [3]

0x41a9b6 VADDPD	(%R9,%RAX,1),%ZMM11,%ZMM15    [7]

0x41a9bd VSUBPD	(%R8,%RAX,1),%ZMM12,%ZMM2    [10]

0x41a9c4 VFMADD132PD	(%RDX,%RAX,1),%ZMM10,%ZMM12    [1]

0x41a9cb VSUBPD	(%RSI,%RAX,1),%ZMM15,%ZMM5    [2]

0x41a9d2 VADDPD	(%R11,%RAX,1),%ZMM2,%ZMM14    [6]

0x41a9d9 VDIVPD	%ZMM14,%ZMM12,%ZMM6

0x41a9df VDIVPD	%ZMM5,%ZMM14,%ZMM4

0x41a9e5 VMOVUPD	%ZMM4,(%RCX,%RAX,1)    [4]

0x41a9ec VMOVUPD	%ZMM6,(%RDX,%RAX,1)    [1]

0x41a9f3 VMOVUPD	0x40(%RBX,%RAX,1),%ZMM9    [9]

0x41a9fb VMOVUPD	0x40(%R10,%RAX,1),%ZMM8    [5]

0x41aa03 VMULPD	0x40(%RCX,%RAX,1),%ZMM9,%ZMM7    [4]

0x41aa0b VSUBPD	0x40(%RDI,%RAX,1),%ZMM8,%ZMM0    [3]

0x41aa13 VADDPD	0x40(%R9,%RAX,1),%ZMM9,%ZMM11    [7]

0x41aa1b VSUBPD	0x40(%R8,%RAX,1),%ZMM7,%ZMM3    [10]

0x41aa23 VFMADD132PD	0x40(%RDX,%RAX,1),%ZMM0,%ZMM7    [1]

0x41aa2b VSUBPD	0x40(%RSI,%RAX,1),%ZMM11,%ZMM12    [2]

0x41aa33 VADDPD	0x40(%R11,%RAX,1),%ZMM3,%ZMM1    [6]

0x41aa3b VDIVPD	%ZMM12,%ZMM1,%ZMM2

0x41aa41 VDIVPD	%ZMM1,%ZMM7,%ZMM14

0x41aa47 VMOVUPD	%ZMM2,0x40(%RCX,%RAX,1)    [4]

0x41aa4f VMOVUPD	%ZMM14,0x40(%RDX,%RAX,1)    [1]

0x41aa57 SUB	$-0x80,%RAX

0x41aa5b CMP	%RAX,0x128(%RSP)    [8]

0x41aa63 JNE	41a99a

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 165 - 170

--------------------------------------------------------------------------------

165:           pre_mass_s=density1(j,k)*pre_vol(j,k)

166:           post_mass_s=pre_mass_s+mass_flux_x(j,k)-mass_flux_x(j+1,k)

167:           post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j+1,k))/post_mass_s

168:           advec_vol_s=pre_vol(j,k)+vol_flux_x(j,k)-vol_flux_x(j+1,k)

169:           density1(j,k)=post_mass_s/advec_vol_s

170:           energy1(j,k)=post_ener_s

Coverage (%)	Name	Source Location	Module
○97.61	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.92
Bottlenecks	P0,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:165-170
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	64.00
CQA cycles if no scalar integer	64.00
CQA cycles if FP arith vectorized	64.00
CQA cycles if fully vectorized	64.00
Front-end cycles	8.33
P0 cycles	13.00
P1 cycles	7.00
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	2.00
P5 cycles	13.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	6.33
DIV/SQRT cycles	64.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	36.00
Nb loads	19.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	2.50
Nb FLOP add-sub	80.00
Nb FLOP mul	16.00
Nb FLOP fma	16.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.13
Bytes prefetched	0.00
Bytes loaded	1160.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.92
Bottlenecks	P0,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:165-170
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	64.00
CQA cycles if no scalar integer	64.00
CQA cycles if FP arith vectorized	64.00
CQA cycles if fully vectorized	64.00
Front-end cycles	8.33
P0 cycles	13.00
P1 cycles	7.00
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	2.00
P5 cycles	13.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	6.33
DIV/SQRT cycles	64.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	36.00
Nb loads	19.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	2.50
Nb FLOP add-sub	80.00
Nb FLOP mul	16.00
Nb FLOP fma	16.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.13
Bytes prefetched	0.00
Bytes loaded	1160.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:165-170
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:165-170.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 64.00 to 13.00 cycles (4.92x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 64.00 to 9.00 cycles (7.11x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:167
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:169
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:169
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:167

Type of elements and instruction set

18 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 160 FP arithmetical operations:

96: addition or subtraction (16 inside FMA instructions)
32: multiply (16 inside FMA instructions)
32: divide

The binary loop is loading 1160 bytes (145 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	29
nb uops	36
loop length	207
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	1
ADD-SUB / MUL ratio	5.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.00	0.00	6.33	6.33	2.00	13.00	1.00	2.00	2.00	2.00	0.00	6.33
cycles	13.00	7.00	6.33	6.33	2.00	13.00	1.00	2.00	2.00	2.00	0.00	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	64.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.33
Dispatch	13.00
DIV/SQRT	64.00
Data deps.	1.00
Overall L1	64.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 64.00 cycles. At this rate:

9% of peak load performance is reached (18.13 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a99a

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RBX,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R10,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD (%RCX,%RAX,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD (%RDI,%RAX,1),%ZMM13,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R9,%RAX,1),%ZMM11,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%R8,%RAX,1),%ZMM12,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VFMADD132PD (%RDX,%RAX,1),%ZMM10,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD (%RSI,%RAX,1),%ZMM15,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R11,%RAX,1),%ZMM2,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD %ZMM14,%ZMM12,%ZMM6	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM5,%ZMM14,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD %ZMM4,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM6,(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RBX,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R10,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD 0x40(%RCX,%RAX,1),%ZMM9,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD 0x40(%RDI,%RAX,1),%ZMM8,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%R9,%RAX,1),%ZMM9,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x40(%R8,%RAX,1),%ZMM7,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VFMADD132PD 0x40(%RDX,%RAX,1),%ZMM0,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD 0x40(%RSI,%RAX,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%R11,%RAX,1),%ZMM3,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD %ZMM12,%ZMM1,%ZMM2	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM1,%ZMM7,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD %ZMM2,0x40(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM14,0x40(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
SUB $-0x80,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,0x128(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 41a99a <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x179a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:165-170
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 64.00 to 9.00 cycles (7.11x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:167
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:169
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:169
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:167

Type of elements and instruction set

18 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 160 FP arithmetical operations:

96: addition or subtraction (16 inside FMA instructions)
32: multiply (16 inside FMA instructions)
32: divide

The binary loop is loading 1160 bytes (145 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	29
nb uops	36
loop length	207
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	1
ADD-SUB / MUL ratio	5.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.00	0.00	6.33	6.33	2.00	13.00	1.00	2.00	2.00	2.00	0.00	6.33
cycles	13.00	7.00	6.33	6.33	2.00	13.00	1.00	2.00	2.00	2.00	0.00	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	64.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.33
Dispatch	13.00
DIV/SQRT	64.00
Data deps.	1.00
Overall L1	64.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 64.00 cycles. At this rate:

9% of peak load performance is reached (18.13 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a99a

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RBX,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R10,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD (%RCX,%RAX,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD (%RDI,%RAX,1),%ZMM13,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R9,%RAX,1),%ZMM11,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%R8,%RAX,1),%ZMM12,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VFMADD132PD (%RDX,%RAX,1),%ZMM10,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD (%RSI,%RAX,1),%ZMM15,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R11,%RAX,1),%ZMM2,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD %ZMM14,%ZMM12,%ZMM6	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM5,%ZMM14,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD %ZMM4,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM6,(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RBX,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R10,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD 0x40(%RCX,%RAX,1),%ZMM9,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD 0x40(%RDI,%RAX,1),%ZMM8,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%R9,%RAX,1),%ZMM9,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x40(%R8,%RAX,1),%ZMM7,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VFMADD132PD 0x40(%RDX,%RAX,1),%ZMM0,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD 0x40(%RSI,%RAX,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%R11,%RAX,1),%ZMM3,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD %ZMM12,%ZMM1,%ZMM2	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM1,%ZMM7,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD %ZMM2,0x40(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM14,0x40(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
SUB $-0x80,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,0x128(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 41a99a <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x179a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code