OV - exec - Loop 65

	Loop Id: 65	Module: exec	Source: accelerate_kernel.f90:67-76	Coverage: 5.63%

0x417c70 MOV	0x2f0(%RSP),%RCX    [19]

0x417c78 MOV	0x2f8(%RSP),%RDX    [19]

0x417c80 VMOVUPD	(%RCX,%RAX,1),%ZMM0    [15]

0x417c87 MOV	0x300(%RSP),%RCX    [19]

0x417c8f VMULPD	(%RDX,%RAX,1),%ZMM0,%ZMM9    [25]

0x417c96 MOV	0x308(%RSP),%RDX    [19]

0x417c9e VMOVUPD	(%R13,%RAX,1),%ZMM15    [1]

0x417ca6 VMOVUPD	(%RDX,%RAX,1),%ZMM2    [24]

0x417cad MOV	0x2e0(%RSP),%RDX    [19]

0x417cb5 VFMADD231PD	(%RCX,%RAX,1),%ZMM2,%ZMM9    [14]

0x417cbc VMOVUPD	(%RDX,%RAX,1),%ZMM8    [23]

0x417cc3 MOV	0x318(%RSP),%RCX    [19]

0x417ccb MOV	0x2e8(%RSP),%RDX    [19]

0x417cd3 VMULPD	(%RCX,%RAX,1),%ZMM8,%ZMM10    [13]

0x417cda MOV	0x310(%RSP),%RCX    [19]

0x417ce2 VSUBPD	(%R12,%RAX,1),%ZMM15,%ZMM0    [16]

0x417ce9 VMOVUPD	(%RCX,%RAX,1),%ZMM11    [7]

0x417cf0 MOV	0x320(%RSP),%RCX    [19]

0x417cf8 VFMADD231PD	(%RDX,%RAX,1),%ZMM11,%ZMM10    [22]

0x417cff MOV	0x328(%RSP),%RDX    [19]

0x417d07 VADDPD	%ZMM10,%ZMM9,%ZMM12

0x417d0d VMOVUPD	(%R11,%RAX,1),%ZMM9    [12]

0x417d14 VSUBPD	(%R10,%RAX,1),%ZMM9,%ZMM2    [11]

0x417d1b VMULPD	%ZMM3,%ZMM12,%ZMM13

0x417d21 VMULPD	(%R14,%RAX,1),%ZMM2,%ZMM8    [17]

0x417d28 VDIVPD	%ZMM13,%ZMM4,%ZMM14

0x417d2e VFMADD231PD	(%RDX,%RAX,1),%ZMM0,%ZMM8    [21]

0x417d35 VFNMADD213PD	(%RCX,%RAX,1),%ZMM14,%ZMM8    [6]

0x417d3c VMOVUPD	%ZMM8,(%R15,%RAX,1)    [18]

0x417d43 VMOVUPD	(%R12,%RAX,1),%ZMM12    [16]

0x417d4a VMOVUPD	(%R13,%RAX,1),%ZMM10    [1]

0x417d52 VSUBPD	(%R10,%RAX,1),%ZMM12,%ZMM13    [11]

0x417d59 VSUBPD	(%R11,%RAX,1),%ZMM10,%ZMM11    [12]

0x417d60 VMULPD	(%R8,%RAX,1),%ZMM13,%ZMM15    [8]

0x417d67 VFMADD231PD	(%R9,%RAX,1),%ZMM11,%ZMM15    [9]

0x417d6e MOV	0x330(%RSP),%RCX    [19]

0x417d76 VFNMADD213PD	(%RCX,%RAX,1),%ZMM14,%ZMM15    [5]

0x417d7d MOV	0x338(%RSP),%RCX    [19]

0x417d85 VMOVUPD	%ZMM15,(%RBX,%RAX,1)    [26]

0x417d8c VMOVUPD	(%RCX,%RAX,1),%ZMM2    [4]

0x417d93 MOV	0x2d8(%RSP),%RCX    [19]

0x417d9b VMOVUPD	(%RDI,%RAX,1),%ZMM0    [2]

0x417da2 VSUBPD	(%RCX,%RAX,1),%ZMM2,%ZMM8    [3]

0x417da9 VSUBPD	(%RSI,%RAX,1),%ZMM0,%ZMM9    [10]

0x417db0 VMULPD	(%R14,%RAX,1),%ZMM8,%ZMM10    [17]

0x417db7 VFMADD231PD	(%RDX,%RAX,1),%ZMM9,%ZMM10    [21]

0x417dbe MOV	0x338(%RSP),%RDX    [19]

0x417dc6 VFNMADD213PD	(%R15,%RAX,1),%ZMM14,%ZMM10    [18]

0x417dcd VMOVUPD	%ZMM10,(%R15,%RAX,1)    [18]

0x417dd4 VMOVUPD	(%RSI,%RAX,1),%ZMM13    [10]

0x417ddb VMOVUPD	(%RDI,%RAX,1),%ZMM11    [2]

0x417de2 VSUBPD	(%RCX,%RAX,1),%ZMM13,%ZMM15    [3]

0x417de9 VSUBPD	(%RDX,%RAX,1),%ZMM11,%ZMM12    [20]

0x417df0 VMULPD	(%R8,%RAX,1),%ZMM15,%ZMM0    [8]

0x417df7 VFMADD231PD	(%R9,%RAX,1),%ZMM12,%ZMM0    [9]

0x417dfe VFNMADD213PD	(%RBX,%RAX,1),%ZMM0,%ZMM14    [26]

0x417e05 VMOVUPD	%ZMM14,(%RBX,%RAX,1)    [26]

0x417e0c ADD	$0x40,%RAX

0x417e10 CMP	%RAX,0x2d0(%RSP)    [19]

0x417e18 JNE	417c70

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 67 - 76

--------------------------------------------------------------------------------

67:           *0.25_8)

68:

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

Coverage (%)	Name	Source Location	Module
○97.60	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.40	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P2, P3, P11,
Function	__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:67-76
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	17.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	14.17
P0 cycles	14.50
P1 cycles	13.00
P2 cycles	17.00
P3 cycles	17.00
P4 cycles	2.00
P5 cycles	14.50
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	17.00
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	61.00
Nb loads	51.00
Nb stores	4.00
Nb stack references	14.00
FLOP/cycle	17.41
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	80.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	157.65
Bytes prefetched	0.00
Bytes loaded	2424.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	25.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P2, P3, P11,
Function	__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:67-76
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	17.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	14.17
P0 cycles	14.50
P1 cycles	13.00
P2 cycles	17.00
P3 cycles	17.00
P4 cycles	2.00
P5 cycles	14.50
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	17.00
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	61.00
Nb loads	51.00
Nb stores	4.00
Nb stack references	14.00
FLOP/cycle	17.41
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	80.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	157.65
Bytes prefetched	0.00
Bytes loaded	2424.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	25.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:67-76
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67-76.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 16.00 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 80 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67

Type of elements and instruction set

27 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 296 FP arithmetical operations:

152: addition or subtraction (80 inside FMA instructions)
136: multiply (80 inside FMA instructions)
8: divide

The binary loop is loading 2424 bytes (303 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	61
loop length	430
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	14
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.17 cycles
front end	14.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.50	0.00	17.00	17.00	2.00	14.50	1.00	2.00	2.00	2.00	0.00	17.00
cycles	14.50	13.00	17.00	17.00	2.00	14.50	1.00	2.00	2.00	2.00	0.00	17.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.17
Dispatch	17.00
DIV/SQRT	16.00
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

74% of peak load performance is reached (142.59 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (15.06 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 417c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x2f0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2f8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RCX,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x300(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPD (%RDX,%RAX,1),%ZMM0,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x308(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R13,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RDX,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x2e0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD231PD (%RCX,%RAX,1),%ZMM2,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD (%RDX,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x318(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2e8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPD (%RCX,%RAX,1),%ZMM8,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x310(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBPD (%R12,%RAX,1),%ZMM15,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD (%RCX,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x320(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD231PD (%RDX,%RAX,1),%ZMM11,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x328(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD %ZMM10,%ZMM9,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R11,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%R10,%RAX,1),%ZMM9,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM3,%ZMM12,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD (%R14,%RAX,1),%ZMM2,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VDIVPD %ZMM13,%ZMM4,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VFMADD231PD (%RDX,%RAX,1),%ZMM0,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFNMADD213PD (%RCX,%RAX,1),%ZMM14,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM8,(%R15,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R13,%RAX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%R10,%RAX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%R11,%RAX,1),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R8,%RAX,1),%ZMM13,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFMADD231PD (%R9,%RAX,1),%ZMM11,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x330(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFNMADD213PD (%RCX,%RAX,1),%ZMM14,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x338(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM15,(%RBX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%RCX,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x2d8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RDI,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%RCX,%RAX,1),%ZMM2,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%RSI,%RAX,1),%ZMM0,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R14,%RAX,1),%ZMM8,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFMADD231PD (%RDX,%RAX,1),%ZMM9,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x338(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFNMADD213PD (%R15,%RAX,1),%ZMM14,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM10,(%R15,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%RSI,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RDI,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%RCX,%RAX,1),%ZMM13,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%RDX,%RAX,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R8,%RAX,1),%ZMM15,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFMADD231PD (%R9,%RAX,1),%ZMM12,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFNMADD213PD (%RBX,%RAX,1),%ZMM0,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%RBX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,0x2d0(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 417c70 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x7b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:67-76
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 80 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67

Type of elements and instruction set

27 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 296 FP arithmetical operations:

152: addition or subtraction (80 inside FMA instructions)
136: multiply (80 inside FMA instructions)
8: divide

The binary loop is loading 2424 bytes (303 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	61
loop length	430
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	14
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.17 cycles
front end	14.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.50	0.00	17.00	17.00	2.00	14.50	1.00	2.00	2.00	2.00	0.00	17.00
cycles	14.50	13.00	17.00	17.00	2.00	14.50	1.00	2.00	2.00	2.00	0.00	17.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.17
Dispatch	17.00
DIV/SQRT	16.00
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

74% of peak load performance is reached (142.59 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (15.06 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 417c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x2f0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2f8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RCX,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x300(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPD (%RDX,%RAX,1),%ZMM0,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x308(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R13,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RDX,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x2e0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD231PD (%RCX,%RAX,1),%ZMM2,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD (%RDX,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x318(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2e8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPD (%RCX,%RAX,1),%ZMM8,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x310(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBPD (%R12,%RAX,1),%ZMM15,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD (%RCX,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x320(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD231PD (%RDX,%RAX,1),%ZMM11,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x328(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD %ZMM10,%ZMM9,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R11,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%R10,%RAX,1),%ZMM9,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD %ZMM3,%ZMM12,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD (%R14,%RAX,1),%ZMM2,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VDIVPD %ZMM13,%ZMM4,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VFMADD231PD (%RDX,%RAX,1),%ZMM0,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFNMADD213PD (%RCX,%RAX,1),%ZMM14,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM8,(%R15,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R13,%RAX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%R10,%RAX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%R11,%RAX,1),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R8,%RAX,1),%ZMM13,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFMADD231PD (%R9,%RAX,1),%ZMM11,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x330(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFNMADD213PD (%RCX,%RAX,1),%ZMM14,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x338(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM15,(%RBX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%RCX,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x2d8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RDI,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%RCX,%RAX,1),%ZMM2,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%RSI,%RAX,1),%ZMM0,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R14,%RAX,1),%ZMM8,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFMADD231PD (%RDX,%RAX,1),%ZMM9,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x338(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFNMADD213PD (%R15,%RAX,1),%ZMM14,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM10,(%R15,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%RSI,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RDI,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD (%RCX,%RAX,1),%ZMM13,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%RDX,%RAX,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMULPD (%R8,%RAX,1),%ZMM15,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFMADD231PD (%R9,%RAX,1),%ZMM12,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VFNMADD213PD (%RBX,%RAX,1),%ZMM0,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%RBX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,0x2d0(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 417c70 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x7b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code