OV - exec - Loop 55

	Loop Id: 55	Module: exec	Source: PdV_kernel.f90:114-135 [...]	Coverage: 6.47%

0x414bd8 VMOVUPD	(%R15,%RAX,1),%ZMM1    [17]

0x414bdf MOV	0x3e8(%RSP),%RDX    [29]

0x414be7 VMOVUPD	(%R14,%RAX,1),%ZMM0    [18]

0x414bee VADDPD	(%RDX,%RAX,1),%ZMM1,%ZMM2    [10]

0x414bf5 MOV	0x3e0(%RSP),%RDX    [29]

0x414bfd VMOVUPD	(%R11,%RAX,1),%ZMM8    [19]

0x414c04 VADDPD	(%RDX,%RAX,1),%ZMM0,%ZMM3    [9]

0x414c0b MOV	0x3c0(%RSP),%RDX    [29]

0x414c13 VMOVUPD	(%R9,%RAX,1),%ZMM12    [15]

0x414c1a VADDPD	(%RDX,%RAX,1),%ZMM8,%ZMM11    [8]

0x414c21 MOV	0x3b8(%RSP),%RDX    [29]

0x414c29 VMOVUPD	(%R13,%RAX,1),%ZMM1    [20]

0x414c31 VADDPD	(%RDX,%RAX,1),%ZMM12,%ZMM13    [7]

0x414c38 MOV	0x418(%RSP),%RDX    [29]

0x414c40 VMOVUPD	(%RSI,%RAX,1),%ZMM0    [1]

0x414c47 VADDPD	%ZMM13,%ZMM11,%ZMM14

0x414c4d VADDPD	%ZMM3,%ZMM2,%ZMM10

0x414c53 VMOVUPD	(%RCX,%RAX,1),%ZMM8    [21]

0x414c5a VMULPD	(%RDX,%RAX,1),%ZMM14,%ZMM15    [6]

0x414c61 MOV	0x3d0(%RSP),%RDX    [29]

0x414c69 VADDPD	(%R8,%RAX,1),%ZMM8,%ZMM12    [14]

0x414c70 VADDPD	(%RDX,%RAX,1),%ZMM1,%ZMM2    [5]

0x414c77 MOV	0x3c8(%RSP),%RDX    [29]

0x414c7f VADDPD	(%RDX,%RAX,1),%ZMM0,%ZMM3    [4]

0x414c86 MOV	0x3b0(%RSP),%RDX    [29]

0x414c8e VMOVUPD	(%RDX,%RAX,1),%ZMM13    [3]

0x414c95 MOV	0x420(%RSP),%RDX    [29]

0x414c9d VADDPD	(%RDI,%RAX,1),%ZMM13,%ZMM14    [11]

0x414ca4 VADDPD	%ZMM3,%ZMM2,%ZMM11

0x414caa VADDPD	%ZMM14,%ZMM12,%ZMM1

0x414cb0 VMULPD	(%RDX,%RAX,1),%ZMM1,%ZMM2    [2]

0x414cb7 MOV	0x3d8(%RSP),%RDX    [29]

0x414cbf VFMADD132PD	(%RDX,%RAX,1),%ZMM2,%ZMM11    [28]

0x414cc6 MOV	0x3f0(%RSP),%RDX    [29]

0x414cce VFMADD132PD	(%RDX,%RAX,1),%ZMM15,%ZMM10    [27]

0x414cd5 MOV	0x430(%RSP),%RDX    [29]

0x414cdd VMULSD	(%RDX),%XMM4,%XMM15    [26]

0x414ce1 VMOVUPD	(%RBX,%RAX,1),%ZMM13    [12]

0x414ce8 MOV	0x410(%RSP),%RDX    [29]

0x414cf0 VSUBPD	%ZMM10,%ZMM11,%ZMM10

0x414cf6 VADDPD	(%RDX,%RAX,1),%ZMM13,%ZMM14    [25]

0x414cfd VMOVUPD	(%R10,%RAX,1),%ZMM3    [13]

0x414d04 VBROADCASTSD	%XMM15,%ZMM0

0x414d0a VDIVPD	(%R12,%RAX,1),%ZMM14,%ZMM1    [16]

0x414d11 VMULPD	%ZMM0,%ZMM10,%ZMM11

0x414d17 VDIVPD	%ZMM3,%ZMM5,%ZMM2

0x414d1d VMULPD	%ZMM2,%ZMM1,%ZMM15

0x414d23 MOV	0x408(%RSP),%RDX    [29]

0x414d2b VADDPD	%ZMM3,%ZMM11,%ZMM8

0x414d31 VFNMADD213PD	(%RDX,%RAX,1),%ZMM15,%ZMM11    [24]

0x414d38 MOV	0x400(%RSP),%RDX    [29]

0x414d40 VDIVPD	%ZMM8,%ZMM3,%ZMM12

0x414d46 VMOVUPD	%ZMM11,(%RDX,%RAX,1)    [23]

0x414d4d VMULPD	(%R12,%RAX,1),%ZMM12,%ZMM10    [16]

0x414d54 MOV	0x3f8(%RSP),%RDX    [29]

0x414d5c VMOVUPD	%ZMM10,(%RDX,%RAX,1)    [22]

0x414d63 MOV	0x3a8(%RSP),%RDX    [29]

0x414d6b ADD	$0x40,%RAX

0x414d6f CMP	%RDX,%RAX

0x414d72 JNE	414bd8

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 114 - 135

--------------------------------------------------------------------------------

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
○97.59	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.41	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.91
Bottlenecks	P0,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	48.00
CQA cycles if no scalar integer	48.00
CQA cycles if FP arith vectorized	48.00
CQA cycles if fully vectorized	48.00
Front-end cycles	13.50
P0 cycles	16.50
P1 cycles	12.00
P2 cycles	14.67
P3 cycles	14.67
P4 cycles	1.00
P5 cycles	16.50
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	14.67
DIV/SQRT cycles	48.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	66.00
Nb loads	44.00
Nb stores	2.00
Nb stack references	17.00
FLOP/cycle	4.85
Nb FLOP add-sub	120.00
Nb FLOP mul	41.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	40.33
Bytes prefetched	0.00
Bytes loaded	1808.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	27.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	95.00
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	83.33
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	95.63
Vector-efficiency ratio load	96.76
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	85.42
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.91
Bottlenecks	P0,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	48.00
CQA cycles if no scalar integer	48.00
CQA cycles if FP arith vectorized	48.00
CQA cycles if fully vectorized	48.00
Front-end cycles	13.50
P0 cycles	16.50
P1 cycles	12.00
P2 cycles	14.67
P3 cycles	14.67
P4 cycles	1.00
P5 cycles	16.50
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	14.67
DIV/SQRT cycles	48.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	66.00
Nb loads	44.00
Nb stores	2.00
Nb stack references	17.00
FLOP/cycle	4.85
Nb FLOP add-sub	120.00
Nb FLOP mul	41.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	40.33
Bytes prefetched	0.00
Bytes loaded	1808.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	27.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	95.00
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	83.33
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	95.63
Vector-efficiency ratio load	96.76
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	85.42
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:114-123,129-135.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

96% of SSE/AVX loads are used in vector version.
83% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 48.00 to 16.50 cycles (2.91x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 14.33 cycles (3.35x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:129
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:123

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 26 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 233 FP arithmetical operations:

144: addition or subtraction (24 inside FMA instructions)
65: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1808 bytes (226 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	66
loop length	416
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	12
nb stack references	17
ADD-SUB / MUL ratio	2.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.50	1.00	14.67	14.67	1.00	16.50	1.00	1.00	1.00	1.00	0.00	14.67
cycles	16.50	12.00	14.67	14.67	1.00	16.50	1.00	1.00	1.00	1.00	0.00	14.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	48.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.50
Dispatch	16.50
DIV/SQRT	48.00
Data deps.	1.00
Overall L1	48.00

Vectorization ratios

all	95%
load	96%
store	100%
mul	83%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

all	95%
load	96%
store	100%
mul	85%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.00 cycles. At this rate:

19% of peak load performance is reached (37.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 414bd8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R15,%RAX,1),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x3e8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R14,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM1,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3e0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R11,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM0,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3c0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R9,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM8,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3b8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R13,%RAX,1),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x418(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RSI,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM11,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM2,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD (%RDX,%RAX,1),%ZMM14,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x3d0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD (%R8,%RAX,1),%ZMM8,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM1,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3c8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD (%RDX,%RAX,1),%ZMM0,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3b0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RDX,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x420(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD (%RDI,%RAX,1),%ZMM13,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM3,%ZMM2,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM12,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD (%RDX,%RAX,1),%ZMM1,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x3d8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD132PD (%RDX,%RAX,1),%ZMM2,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x3f0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD132PD (%RDX,%RAX,1),%ZMM15,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x430(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%RDX),%XMM4,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD (%RBX,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x410(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBPD %ZMM10,%ZMM11,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM13,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD (%R10,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VBROADCASTSD %XMM15,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VDIVPD (%R12,%RAX,1),%ZMM14,%ZMM1	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMULPD %ZMM0,%ZMM10,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM3,%ZMM5,%ZMM2	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM2,%ZMM1,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x408(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD %ZMM3,%ZMM11,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD213PD (%RDX,%RAX,1),%ZMM15,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x400(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVPD %ZMM8,%ZMM3,%ZMM12	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD %ZMM11,(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD (%R12,%RAX,1),%ZMM12,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x3f8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM10,(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV 0x3a8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x40,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 414bd8 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x1d88>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

96% of SSE/AVX loads are used in vector version.
83% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 14.33 cycles (3.35x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:131
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:129
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:123

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 233 FP arithmetical operations:

144: addition or subtraction (24 inside FMA instructions)
65: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1808 bytes (226 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	66
loop length	416
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	12
nb stack references	17
ADD-SUB / MUL ratio	2.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.50	1.00	14.67	14.67	1.00	16.50	1.00	1.00	1.00	1.00	0.00	14.67
cycles	16.50	12.00	14.67	14.67	1.00	16.50	1.00	1.00	1.00	1.00	0.00	14.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	48.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.50
Dispatch	16.50
DIV/SQRT	48.00
Data deps.	1.00
Overall L1	48.00

Vectorization ratios

all	95%
load	96%
store	100%
mul	83%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

all	95%
load	96%
store	100%
mul	85%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.00 cycles. At this rate:

19% of peak load performance is reached (37.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 414bd8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R15,%RAX,1),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x3e8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R14,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM1,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3e0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R11,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM0,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3c0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R9,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM8,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3b8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R13,%RAX,1),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x418(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RSI,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM11,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM2,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD (%RDX,%RAX,1),%ZMM14,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x3d0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD (%R8,%RAX,1),%ZMM8,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM1,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3c8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD (%RDX,%RAX,1),%ZMM0,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x3b0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RDX,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x420(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD (%RDI,%RAX,1),%ZMM13,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM3,%ZMM2,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM12,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD (%RDX,%RAX,1),%ZMM1,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x3d8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD132PD (%RDX,%RAX,1),%ZMM2,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x3f0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD132PD (%RDX,%RAX,1),%ZMM15,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x430(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%RDX),%XMM4,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD (%RBX,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x410(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBPD %ZMM10,%ZMM11,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RDX,%RAX,1),%ZMM13,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD (%R10,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VBROADCASTSD %XMM15,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VDIVPD (%R12,%RAX,1),%ZMM14,%ZMM1	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMULPD %ZMM0,%ZMM10,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM3,%ZMM5,%ZMM2	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM2,%ZMM1,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x408(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD %ZMM3,%ZMM11,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD213PD (%RDX,%RAX,1),%ZMM15,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x400(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVPD %ZMM8,%ZMM3,%ZMM12	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD %ZMM11,(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD (%R12,%RAX,1),%ZMM12,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x3f8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM10,(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV 0x3a8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x40,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 414bd8 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x1d88>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code