OV - exec - Loop 311

	Loop Id: 311	Module: exec	Source: revert_kernel.f90:47-48	Coverage: 2.31%

0x43d401 VMOVUPD	(%R13,%RAX,1),%ZMM14    [3]

0x43d409 VMOVUPD	%ZMM14,(%R12,%RAX,1)    [2]

0x43d410 VMOVUPD	(%RBX,%RAX,1),%ZMM15    [4]

0x43d417 VMOVUPD	%ZMM15,(%RCX,%RAX,1)    [1]

0x43d41e VMOVUPD	0x40(%R13,%RAX,1),%ZMM0    [3]

0x43d426 VMOVUPD	%ZMM0,0x40(%R12,%RAX,1)    [2]

0x43d42e VMOVUPD	0x40(%RBX,%RAX,1),%ZMM1    [4]

0x43d436 VMOVUPD	%ZMM1,0x40(%RCX,%RAX,1)    [1]

0x43d43e VMOVUPD	0x80(%R13,%RAX,1),%ZMM2    [3]

0x43d446 VMOVUPD	%ZMM2,0x80(%R12,%RAX,1)    [2]

0x43d44e VMOVUPD	0x80(%RBX,%RAX,1),%ZMM3    [4]

0x43d456 VMOVUPD	%ZMM3,0x80(%RCX,%RAX,1)    [1]

0x43d45e VMOVUPD	0xc0(%R13,%RAX,1),%ZMM4    [3]

0x43d466 VMOVUPD	%ZMM4,0xc0(%R12,%RAX,1)    [2]

0x43d46e VMOVUPD	0xc0(%RBX,%RAX,1),%ZMM5    [4]

0x43d476 VMOVUPD	%ZMM5,0xc0(%RCX,%RAX,1)    [1]

0x43d47e VMOVUPD	0x100(%R13,%RAX,1),%ZMM6    [3]

0x43d486 VMOVUPD	%ZMM6,0x100(%R12,%RAX,1)    [2]

0x43d48e VMOVUPD	0x100(%RBX,%RAX,1),%ZMM7    [4]

0x43d496 VMOVUPD	%ZMM7,0x100(%RCX,%RAX,1)    [1]

0x43d49e VMOVUPD	0x140(%R13,%RAX,1),%ZMM8    [3]

0x43d4a6 VMOVUPD	%ZMM8,0x140(%R12,%RAX,1)    [2]

0x43d4ae VMOVUPD	0x140(%RBX,%RAX,1),%ZMM9    [4]

0x43d4b6 VMOVUPD	%ZMM9,0x140(%RCX,%RAX,1)    [1]

0x43d4be VMOVUPD	0x180(%R13,%RAX,1),%ZMM10    [3]

0x43d4c6 VMOVUPD	%ZMM10,0x180(%R12,%RAX,1)    [2]

0x43d4ce VMOVUPD	0x180(%RBX,%RAX,1),%ZMM11    [4]

0x43d4d6 VMOVUPD	%ZMM11,0x180(%RCX,%RAX,1)    [1]

0x43d4de VMOVUPD	0x1c0(%R13,%RAX,1),%ZMM12    [3]

0x43d4e6 VMOVUPD	%ZMM12,0x1c0(%R12,%RAX,1)    [2]

0x43d4ee VMOVUPD	0x1c0(%RBX,%RAX,1),%ZMM13    [4]

0x43d4f6 VMOVUPD	%ZMM13,0x1c0(%RCX,%RAX,1)    [1]

0x43d4fe ADD	$0x200,%RAX

0x43d504 CMP	%RAX,0x68(%RSP)    [5]

0x43d509 JNE	43d401

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90: 47 - 48

--------------------------------------------------------------------------------

47:         density1(j,k)=density0(j,k)

48:         energy1(j,k)=energy0(j,k)

Coverage (%)	Name	Source Location	Module
○97.61	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P4, P7, P8, P9,
Function	__revert_kernel_module_MOD_revert_kernel._omp_fn.0
Source	revert_kernel.f90:47-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	5.67
P0 cycles	0.50
P1 cycles	0.40
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	8.00
P5 cycles	0.40
P6 cycles	0.50
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.20
P11 cycles	5.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	17.00
Nb stores	16.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	257.00
Bytes prefetched	0.00
Bytes loaded	1032.00
Bytes stored	1024.00
Stride 0	1.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P4, P7, P8, P9,
Function	__revert_kernel_module_MOD_revert_kernel._omp_fn.0
Source	revert_kernel.f90:47-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	5.67
P0 cycles	0.50
P1 cycles	0.40
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	8.00
P5 cycles	0.40
P6 cycles	0.50
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.20
P11 cycles	5.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	17.00
Nb stores	16.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	257.00
Bytes prefetched	0.00
Bytes loaded	1032.00
Bytes stored	1024.00
Stride 0	1.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__revert_kernel_module_MOD_revert_kernel._omp_fn.0
Source file and lines	revert_kernel.f90:47-48
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:47-48.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 1032 bytes. The binary loop is storing 1024 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	35
nb uops	34
loop length	270
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.40	5.67	5.67	8.00	0.40	0.50	8.00	8.00	8.00	0.20	5.67
cycles	0.50	0.40	5.67	5.67	8.00	0.40	0.50	8.00	8.00	8.00	0.20	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

67% of peak load performance is reached (129.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
100% of peak store performance is reached (128.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43d401

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R13,%RAX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%RBX,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM15,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%R13,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM0,0x40(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RBX,%RAX,1),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%R13,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x80(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%RBX,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM3,0x80(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%R13,%RAX,1),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM4,0xc0(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM5,0xc0(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x100(%R13,%RAX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM6,0x100(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x100(%RBX,%RAX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM7,0x100(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x140(%R13,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM8,0x140(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x140(%RBX,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM9,0x140(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x180(%R13,%RAX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM10,0x180(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x180(%RBX,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x180(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x1c0(%R13,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM12,0x1c0(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x1c0(%RBX,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM13,0x1c0(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x200,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,0x68(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 43d401 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x2b1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	__revert_kernel_module_MOD_revert_kernel._omp_fn.0
Source file and lines	revert_kernel.f90:47-48
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 1032 bytes. The binary loop is storing 1024 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	35
nb uops	34
loop length	270
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.40	5.67	5.67	8.00	0.40	0.50	8.00	8.00	8.00	0.20	5.67
cycles	0.50	0.40	5.67	5.67	8.00	0.40	0.50	8.00	8.00	8.00	0.20	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

67% of peak load performance is reached (129.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
100% of peak store performance is reached (128.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43d401

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R13,%RAX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%RBX,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM15,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%R13,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM0,0x40(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RBX,%RAX,1),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%R13,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x80(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%RBX,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM3,0x80(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%R13,%RAX,1),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM4,0xc0(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM5,0xc0(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x100(%R13,%RAX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM6,0x100(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x100(%RBX,%RAX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM7,0x100(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x140(%R13,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM8,0x140(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x140(%RBX,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM9,0x140(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x180(%R13,%RAX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM10,0x180(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x180(%RBX,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x180(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x1c0(%R13,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM12,0x1c0(%R12,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x1c0(%RBX,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM13,0x1c0(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x200,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,0x68(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 43d401 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x2b1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code