OV - exec - Loop 269

	Loop Id: 269	Module: exec	Source: pack_kernel.f90:61-66	Coverage: 0.02%

  (268) 0x4379fd MOV	-0x70(%RBP),%RAX

  (268) 0x437a01 MOVSXD	-0x38(%RBP),%RDX

  (268) 0x437a05 MOV	-0x40(%RBP),%R9

  (268) 0x437a09 MOV	-0x68(%RBP),%R12

  (268) 0x437a0d MOV	-0x58(%RBP),%RCX

  (268) 0x437a11 ADD	%RAX,%RDX

  (268) 0x437a14 ADD	%R9,%R12

  (268) 0x437a17 IMUL	%RDI,%RDX

  (268) 0x437a1b LEA	(%RCX,%R12,8),%RSI

  (268) 0x437a1f MOV	-0x50(%RBP),%R12

  (268) 0x437a23 MOV	-0x60(%RBP),%R9

  (268) 0x437a27 ADD	%R12,%RDX

  (268) 0x437a2a LEA	(%R9,%RDX,8),%RCX

  (268) 0x437a2e MOV	-0xa0(%RBP),%RAX

  (268) 0x437a35 MOV	-0xa8(%RBP),%RDX

  (268) 0x437a3c MOV	%RSI,-0x80(%RBP)

  (268) 0x437a40 MOV	%RCX,-0x88(%RBP)

  (268) 0x437a47 LEA	(%RSI,%RDX,1),%RDX

  (268) 0x437a4b ADD	%RCX,%RAX

  (268) 0x437a4e XOR	%R12D,%R12D

  (268) 0x437a51 TESTB	$0x1,-0x34(%RBP)

  (268) 0x437a55 JE	437ae0

  (268) 0x437a5b MOV	-0x80(%RBP),%R12

  (268) 0x437a5f MOV	-0x78(%RBP),%R9

  (268) 0x437a63 VMOVSD	(%R12),%XMM7

  (268) 0x437a69 VMOVSD	(%R12,%R8,8),%XMM6

  (268) 0x437a6f VMOVSD	(%R12,%R11,1),%XMM5

  (268) 0x437a75 VMOVSD	(%R12,%R9,1),%XMM4

  (268) 0x437a7b VMOVSD	(%RDX),%XMM3

  (268) 0x437a7f VMOVSD	(%RDX,%R8,8),%XMM2

  (268) 0x437a85 VMOVSD	(%RDX,%R11,1),%XMM1

  (268) 0x437a8b VMOVSD	(%RDX,%R9,1),%XMM0

  (268) 0x437a91 MOV	-0x88(%RBP),%R12

  (268) 0x437a98 ADD	%R15,%RSI

  (268) 0x437a9b VMOVSD	%XMM7,(%R12)

  (268) 0x437aa1 ADD	%R13,%RCX

  (268) 0x437aa4 VMOVSD	%XMM6,(%R12,%RDI,8)

  (268) 0x437aaa ADD	%R15,%RDX

  (268) 0x437aad VMOVSD	%XMM5,(%R12,%RBX,1)

  (268) 0x437ab3 VMOVSD	%XMM4,(%R12,%R10,1)

  (268) 0x437ab9 VMOVSD	%XMM3,(%RAX)

  (268) 0x437abd VMOVSD	%XMM2,(%RAX,%RDI,8)

  (268) 0x437ac2 VMOVSD	%XMM1,(%RAX,%RBX,1)

  (268) 0x437ac7 VMOVSD	%XMM0,(%RAX,%R10,1)

  (268) 0x437acd ADD	%R13,%RAX

  (268) 0x437ad0 CMPL	$0x1,-0x34(%RBP)

  (268) 0x437ad4 MOV	$0x1,%R12D

  (268) 0x437ada JE	437bb6

  (268) 0x437ae0 MOV	-0x78(%RBP),%R9

    (267) 0x437ae4 VMOVSD	(%RSI),%XMM8

    (267) 0x437ae8 VMOVSD	(%RSI,%R8,8),%XMM9

    (267) 0x437aee VMOVSD	(%RSI,%R11,1),%XMM10

    (267) 0x437af4 VMOVSD	(%RSI,%R9,1),%XMM11

    (267) 0x437afa VMOVSD	(%RDX),%XMM12

    (267) 0x437afe VMOVSD	(%RDX,%R8,8),%XMM13

    (267) 0x437b04 VMOVSD	(%RDX,%R11,1),%XMM14

    (267) 0x437b0a VMOVSD	(%RDX,%R9,1),%XMM15

    (267) 0x437b10 ADD	%R15,%RSI

    (267) 0x437b13 VMOVSD	%XMM8,(%RCX)

    (267) 0x437b17 ADD	%R15,%RDX

    (267) 0x437b1a VMOVSD	%XMM9,(%RCX,%RDI,8)

    (267) 0x437b1f VMOVSD	%XMM10,(%RCX,%RBX,1)

    (267) 0x437b24 VMOVSD	%XMM11,(%RCX,%R10,1)

    (267) 0x437b2a VMOVSD	%XMM12,(%RAX)

    (267) 0x437b2e VMOVSD	%XMM13,(%RAX,%RDI,8)

    (267) 0x437b33 VMOVSD	%XMM14,(%RAX,%RBX,1)

    (267) 0x437b38 VMOVSD	%XMM15,(%RAX,%R10,1)

    (267) 0x437b3e VMOVSD	(%RSI),%XMM7

    (267) 0x437b42 VMOVSD	(%RSI,%R8,8),%XMM6

    (267) 0x437b48 VMOVSD	(%RSI,%R11,1),%XMM5

    (267) 0x437b4e VMOVSD	(%RSI,%R9,1),%XMM4

    (267) 0x437b54 VMOVSD	(%RDX),%XMM3

    (267) 0x437b58 VMOVSD	(%RDX,%R8,8),%XMM2

    (267) 0x437b5e VMOVSD	(%RDX,%R11,1),%XMM1

    (267) 0x437b64 VMOVSD	(%RDX,%R9,1),%XMM0

    (267) 0x437b6a ADD	%R13,%RCX

    (267) 0x437b6d ADD	%R13,%RAX

    (267) 0x437b70 ADD	$0x2,%R12D

    (267) 0x437b74 VMOVSD	%XMM7,(%RCX)

    (267) 0x437b78 ADD	%R15,%RSI

    (267) 0x437b7b VMOVSD	%XMM6,(%RCX,%RDI,8)

    (267) 0x437b80 ADD	%R15,%RDX

    (267) 0x437b83 VMOVSD	%XMM5,(%RCX,%RBX,1)

    (267) 0x437b88 VMOVSD	%XMM4,(%RCX,%R10,1)

    (267) 0x437b8e VMOVSD	%XMM3,(%RAX)

    (267) 0x437b92 ADD	%R13,%RCX

    (267) 0x437b95 VMOVSD	%XMM2,(%RAX,%RDI,8)

    (267) 0x437b9a VMOVSD	%XMM1,(%RAX,%RBX,1)

    (267) 0x437b9f VMOVSD	%XMM0,(%RAX,%R10,1)

    (267) 0x437ba5 ADD	%R13,%RAX

    (267) 0x437ba8 CMP	%R12D,-0x34(%RBP)

    (267) 0x437bac JNE	437ae4

  (268) 0x437bb2 MOV	%R9,-0x78(%RBP)

  (268) 0x437bb6 MOV	-0xac(%RBP),%ECX

  (268) 0x437bbc MOV	%ECX,%ESI

  (268) 0x437bbe LEA	0x1(%RCX),%EAX

  (268) 0x437bc1 CMP	%R14D,%ECX

  (268) 0x437bc4 JE	437d33

0x437bca MOV	%R14D,%R12D

0x437bcd SUB	%ESI,%R12D

0x437bd0 LEA	-0x1(%R12),%EDX

0x437bd5 CMP	$0x2,%EDX

0x437bd8 JBE	437c6f

0x437bde MOV	%R8,%RCX

0x437be1 IMUL	%RSI,%RCX

0x437be5 MOV	-0x68(%RBP),%R9

0x437be9 MOV	-0x40(%RBP),%RDX

0x437bed IMUL	%RDI,%RSI

0x437bf1 ADD	%R9,%RDX

0x437bf4 MOV	-0x58(%RBP),%R9

0x437bf8 ADD	%RCX,%RDX

0x437bfb LEA	(%R9,%RDX,8),%RCX

0x437bff MOV	-0x70(%RBP),%R9

0x437c03 MOVSXD	-0x38(%RBP),%RDX

0x437c07 VMOVSD	(%RCX),%XMM8

0x437c0b ADD	%R9,%RDX

0x437c0e IMUL	%RDI,%RDX

0x437c12 MOV	-0x50(%RBP),%R9

0x437c16 ADD	%R9,%RDX

0x437c19 MOV	-0xb8(%RBP),%R9

0x437c20 ADD	%RSI,%RDX

0x437c23 ADD	%R9,%RCX

0x437c26 VMOVSD	(%RCX),%XMM9

0x437c2a MOV	-0x60(%RBP),%RSI

0x437c2e ADD	%R9,%RCX

0x437c31 VMOVSD	(%RCX),%XMM10

0x437c35 VMOVSD	(%RCX,%R9,1),%XMM11

0x437c3b MOV	-0xc0(%RBP),%RCX

0x437c42 LEA	(%RSI,%RDX,8),%RDX

0x437c46 MOV	%R12D,%ESI

0x437c49 VMOVSD	%XMM8,(%RDX)

0x437c4d AND	$-0x4,%ESI

0x437c50 ADD	%RCX,%RDX

0x437c53 VMOVSD	%XMM9,(%RDX)

0x437c57 ADD	%ESI,%EAX

0x437c59 ADD	%RCX,%RDX

0x437c5c AND	$0x3,%R12D

0x437c60 VMOVSD	%XMM10,(%RDX)

0x437c64 VMOVSD	%XMM11,(%RDX,%RCX,1)

0x437c69 JE	437d33

0x437c6f MOV	-0xb0(%RBP),%ESI

0x437c75 MOV	-0x58(%RBP),%R9

0x437c79 LEA	(%RSI,%RAX,1),%R12D

0x437c7d MOVSXD	%R12D,%RDX

0x437c80 IMUL	%R8,%RDX

0x437c84 MOV	-0x40(%RBP),%R12

0x437c88 MOV	-0x48(%RBP),%ECX

0x437c8b ADD	%R12,%RDX

0x437c8e VMOVSD	(%R9,%RDX,8),%XMM12

0x437c94 MOV	-0x38(%RBP),%EDX

0x437c97 ADD	%EAX,%ECX

0x437c99 ADD	%EDX,%ECX

0x437c9b MOVSXD	%ECX,%R9

0x437c9e IMUL	%RDI,%R9

0x437ca2 MOV	-0x50(%RBP),%RCX

0x437ca6 MOV	-0x60(%RBP),%RDX

0x437caa ADD	%RCX,%R9

0x437cad VMOVSD	%XMM12,(%RDX,%R9,8)

0x437cb3 LEA	0x1(%RAX),%EDX

0x437cb6 CMP	%EDX,%R14D

0x437cb9 JL	437d33

0x437cbb LEA	(%RSI,%RDX,1),%R9D

0x437cbf MOVSXD	%R9D,%RCX

0x437cc2 IMUL	%R8,%RCX

0x437cc6 MOV	-0x58(%RBP),%R9

0x437cca ADD	$0x2,%EAX

0x437ccd ADD	%R12,%RCX

0x437cd0 VMOVSD	(%R9,%RCX,8),%XMM13

0x437cd6 MOV	-0x48(%RBP),%ECX

0x437cd9 MOV	-0x38(%RBP),%R9D

0x437cdd ADD	%ECX,%EDX

0x437cdf ADD	%R9D,%EDX

0x437ce2 MOVSXD	%EDX,%RDX

0x437ce5 IMUL	%RDI,%RDX

0x437ce9 MOV	-0x50(%RBP),%R9

0x437ced ADD	%R9,%RDX

0x437cf0 MOV	-0x60(%RBP),%R9

0x437cf4 VMOVSD	%XMM13,(%R9,%RDX,8)

0x437cfa CMP	%EAX,%R14D

0x437cfd JL	437d33

0x437cff LEA	(%RSI,%RAX,1),%ESI

0x437d02 MOVSXD	%ESI,%RDX

0x437d05 ADD	%ECX,%EAX

0x437d07 MOV	-0x38(%RBP),%ECX

0x437d0a IMUL	%R8,%RDX

0x437d0e ADD	%ECX,%EAX

0x437d10 CLTQ

0x437d12 ADD	%R12,%RDX

0x437d15 IMUL	%RDI,%RAX

0x437d19 MOV	-0x58(%RBP),%R12

0x437d1d MOV	-0x50(%RBP),%R9

0x437d21 VMOVSD	(%R12,%RDX,8),%XMM14

0x437d27 MOV	-0x60(%RBP),%RSI

0x437d2b ADD	%R9,%RAX

0x437d2e VMOVSD	%XMM14,(%RSI,%RAX,8)

  (268) 0x437d33 INCL	-0x44(%RBP)

  (268) 0x437d36 MOV	-0x90(%RBP),%RDX

  (268) 0x437d3d ADD	%R14D,-0x38(%RBP)

  (268) 0x437d41 ADD	%RDX,-0x40(%RBP)

  (268) 0x437d45 MOV	-0x44(%RBP),%EAX

  (268) 0x437d48 TEST	%R14D,%R14D

  (268) 0x437d4b JNS	437d90

  (268) 0x437d90 CMP	%EAX,-0x94(%RBP)

  (268) 0x437d96 JLE	437dcd

  (268) 0x437d98 MOV	-0xcc(%RBP),%ESI

  (268) 0x437d9e CMPL	$0x6,-0x98(%RBP)

  (268) 0x437da5 MOV	%ESI,-0xc8(%RBP)

  (268) 0x437dab MOVB	$0x1,-0xc1(%RBP)

  (268) 0x437db2 JA	4379fd

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 61 - 66

--------------------------------------------------------------------------------

61:     !$OMP PARALLEL DO PRIVATE(index)

62:     DO k=y_min-depth,y_max+y_inc+depth

63:     !$OMP SIMD

64:       DO j=1,depth

65:         index= buffer_offset + j+(k+depth-1)*depth

66:         left_snd_buffer(index)=field(x_min+x_inc-1+j,k)

Coverage (%)	Name	Source Location	Module
○96.40	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○3.60	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	2.84
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P1,
Function	__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0
Source	pack_kernel.f90:65-66
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.97
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	17.97
CQA cycles if fully vectorized	1.17
Front-end cycles	16.17
P0 cycles	10.60
P1 cycles	17.97
P2 cycles	10.67
P3 cycles	10.67
P4 cycles	3.50
P5 cycles	10.60
P6 cycles	10.60
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	10.60
P11 cycles	10.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	97.00
Nb uops	97.00
Nb loads	32.00
Nb stores	7.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.81
Bytes prefetched	0.00
Bytes loaded	228.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.46
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.81

Metric	Value
CQA speedup if no scalar integer	2.84
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P1,
Function	__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0
Source	pack_kernel.f90:65-66
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.97
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	17.97
CQA cycles if fully vectorized	1.17
Front-end cycles	16.17
P0 cycles	10.60
P1 cycles	17.97
P2 cycles	10.67
P3 cycles	10.67
P4 cycles	3.50
P5 cycles	10.60
P6 cycles	10.60
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	10.60
P11 cycles	10.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	97.00
Nb uops	97.00
Nb loads	32.00
Nb stores	7.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.81
Bytes prefetched	0.00
Bytes loaded	228.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.46
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.81

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0
Source file and lines	pack_kernel.f90:61-66
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:61-66.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:65-66.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.97 to 6.33 cycles (2.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 17.97 to 1.17 cycles (15.40x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 228 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	97
nb uops	97
loop length	361
used x86 registers	10
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.17 cycles
front end	16.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.60	10.60	10.67	10.67	3.50	10.60	10.60	3.50	3.50	3.50	10.60	10.67
cycles	10.60	17.97	10.67	10.67	3.50	10.60	10.60	3.50	3.50	3.50	10.60	10.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.17
Dispatch	17.97
Overall L1	17.97

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.97 cycles. At this rate:

6% of peak load performance is reached (12.69 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 437bca

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%R12),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 437c6f <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x63f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%RDX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RDI,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xb8(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RCX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RCX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RCX,%R9,1),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xc0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM8,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x4,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM9,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM10,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM11,(%RDX,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 437d33 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x703>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RAX,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R12D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RDX,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %ECX,%R9	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RDI,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM12,(%RDX,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RAX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %EDX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 437d33 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x703>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RSI,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R9D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RCX,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RDI,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x60(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM13,(%R9,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %EAX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 437d33 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x703>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RSI,%RAX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %ESI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R12,%RDX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM14,(%RSI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)

Function	__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0
Source file and lines	pack_kernel.f90:61-66
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.97 to 6.33 cycles (2.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:66

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 228 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	97
nb uops	97
loop length	361
used x86 registers	10
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.17 cycles
front end	16.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.60	10.60	10.67	10.67	3.50	10.60	10.60	3.50	3.50	3.50	10.60	10.67
cycles	10.60	17.97	10.67	10.67	3.50	10.60	10.60	3.50	3.50	3.50	10.60	10.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.17
Dispatch	17.97
Overall L1	17.97

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.97 cycles. At this rate:

6% of peak load performance is reached (12.69 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 437bca

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%R12),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 437c6f <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x63f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%RDX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RDI,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xb8(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RCX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RCX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RCX,%R9,1),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xc0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM8,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x4,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM9,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM10,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM11,(%RDX,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 437d33 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x703>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RAX,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R12D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RDX,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %ECX,%R9	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RDI,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM12,(%RDX,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RAX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %EDX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 437d33 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x703>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RSI,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R9D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RCX,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RDI,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x60(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM13,(%R9,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %EAX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 437d33 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x703>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RSI,%RAX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %ESI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R12,%RDX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM14,(%RSI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code