OV - exec - Loop 257

	Loop Id: 257	Module: exec	Source: pack_kernel.f90:155-160	Coverage: 0.02%

  (256) 0x4369dd MOV	-0x78(%RBP),%RAX

  (256) 0x4369e1 MOVSXD	-0x38(%RBP),%R12

  (256) 0x4369e5 MOV	-0x48(%RBP),%RDX

  (256) 0x4369e9 MOV	-0x70(%RBP),%R14

  (256) 0x4369ed MOV	-0x60(%RBP),%RCX

  (256) 0x4369f1 ADD	%RAX,%R12

  (256) 0x4369f4 ADD	%RDX,%R14

  (256) 0x4369f7 IMUL	%RDI,%R12

  (256) 0x4369fb LEA	(%RCX,%R14,8),%RSI

  (256) 0x4369ff MOV	-0x58(%RBP),%R14

  (256) 0x436a03 MOV	-0x68(%RBP),%RDX

  (256) 0x436a07 ADD	%R14,%R12

  (256) 0x436a0a LEA	(%RDX,%R12,8),%RCX

  (256) 0x436a0e MOV	-0xa8(%RBP),%RAX

  (256) 0x436a15 MOV	-0xb0(%RBP),%R12

  (256) 0x436a1c MOV	%RSI,-0x88(%RBP)

  (256) 0x436a23 LEA	(%RSI,%R12,1),%RDX

  (256) 0x436a27 MOV	%RCX,-0x90(%RBP)

  (256) 0x436a2e ADD	%RCX,%RAX

  (256) 0x436a31 XOR	%R12D,%R12D

  (256) 0x436a34 TESTB	$0x1,-0x40(%RBP)

  (256) 0x436a38 JE	436ac7

  (256) 0x436a3e MOV	-0x88(%RBP),%R12

  (256) 0x436a45 MOV	-0x80(%RBP),%R14

  (256) 0x436a49 VMOVSD	(%R12),%XMM7

  (256) 0x436a4f VMOVSD	(%R12,%R8,1),%XMM6

  (256) 0x436a55 VMOVSD	(%R12,%R10,1),%XMM5

  (256) 0x436a5b VMOVSD	(%RDX,%R15,1),%XMM4

  (256) 0x436a61 VMOVSD	(%R12,%R14,1),%XMM3

  (256) 0x436a67 VMOVSD	(%RDX),%XMM2

  (256) 0x436a6b VMOVSD	(%RDX,%R8,1),%XMM1

  (256) 0x436a71 VMOVSD	(%RDX,%R10,1),%XMM0

  (256) 0x436a77 MOV	-0x90(%RBP),%R12

  (256) 0x436a7e ADD	%RBX,%RSI

  (256) 0x436a81 VMOVSD	%XMM7,(%R12)

  (256) 0x436a87 ADD	%R13,%RCX

  (256) 0x436a8a VMOVSD	%XMM6,(%R12,%RDI,8)

  (256) 0x436a90 ADD	%RBX,%RDX

  (256) 0x436a93 VMOVSD	%XMM5,(%R12,%R11,1)

  (256) 0x436a99 VMOVSD	%XMM4,(%R12,%R9,1)

  (256) 0x436a9f VMOVSD	%XMM3,(%RAX)

  (256) 0x436aa3 VMOVSD	%XMM2,(%RAX,%RDI,8)

  (256) 0x436aa8 VMOVSD	%XMM1,(%RAX,%R11,1)

  (256) 0x436aae VMOVSD	%XMM0,(%RAX,%R9,1)

  (256) 0x436ab4 ADD	%R13,%RAX

  (256) 0x436ab7 CMPL	$0x1,-0x40(%RBP)

  (256) 0x436abb MOV	$0x1,%R12D

  (256) 0x436ac1 JE	436ba1

  (256) 0x436ac7 MOV	-0x80(%RBP),%R14

    (255) 0x436acb VMOVSD	(%RSI),%XMM8

    (255) 0x436acf VMOVSD	(%RSI,%R8,1),%XMM9

    (255) 0x436ad5 VMOVSD	(%RSI,%R10,1),%XMM10

    (255) 0x436adb VMOVSD	(%RDX,%R15,1),%XMM11

    (255) 0x436ae1 VMOVSD	(%RSI,%R14,1),%XMM12

    (255) 0x436ae7 VMOVSD	(%RDX),%XMM13

    (255) 0x436aeb VMOVSD	(%RDX,%R8,1),%XMM14

    (255) 0x436af1 VMOVSD	(%RDX,%R10,1),%XMM15

    (255) 0x436af7 ADD	%RBX,%RSI

    (255) 0x436afa VMOVSD	%XMM8,(%RCX)

    (255) 0x436afe ADD	%RBX,%RDX

    (255) 0x436b01 VMOVSD	%XMM9,(%RCX,%RDI,8)

    (255) 0x436b06 VMOVSD	%XMM10,(%RCX,%R11,1)

    (255) 0x436b0c VMOVSD	%XMM11,(%RCX,%R9,1)

    (255) 0x436b12 VMOVSD	%XMM12,(%RAX)

    (255) 0x436b16 VMOVSD	%XMM13,(%RAX,%RDI,8)

    (255) 0x436b1b VMOVSD	%XMM14,(%RAX,%R11,1)

    (255) 0x436b21 VMOVSD	%XMM15,(%RAX,%R9,1)

    (255) 0x436b27 VMOVSD	(%RSI),%XMM7

    (255) 0x436b2b VMOVSD	(%RSI,%R8,1),%XMM6

    (255) 0x436b31 VMOVSD	(%RSI,%R10,1),%XMM5

    (255) 0x436b37 VMOVSD	(%RDX,%R15,1),%XMM4

    (255) 0x436b3d VMOVSD	(%RSI,%R14,1),%XMM3

    (255) 0x436b43 VMOVSD	(%RDX),%XMM2

    (255) 0x436b47 VMOVSD	(%RDX,%R8,1),%XMM1

    (255) 0x436b4d VMOVSD	(%RDX,%R10,1),%XMM0

    (255) 0x436b53 ADD	%R13,%RCX

    (255) 0x436b56 ADD	%R13,%RAX

    (255) 0x436b59 ADD	$0x2,%R12D

    (255) 0x436b5d VMOVSD	%XMM7,(%RCX)

    (255) 0x436b61 ADD	%RBX,%RSI

    (255) 0x436b64 VMOVSD	%XMM6,(%RCX,%RDI,8)

    (255) 0x436b69 ADD	%RBX,%RDX

    (255) 0x436b6c VMOVSD	%XMM5,(%RCX,%R11,1)

    (255) 0x436b72 VMOVSD	%XMM4,(%RCX,%R9,1)

    (255) 0x436b78 VMOVSD	%XMM3,(%RAX)

    (255) 0x436b7c ADD	%R13,%RCX

    (255) 0x436b7f VMOVSD	%XMM2,(%RAX,%RDI,8)

    (255) 0x436b84 VMOVSD	%XMM1,(%RAX,%R11,1)

    (255) 0x436b8a VMOVSD	%XMM0,(%RAX,%R9,1)

    (255) 0x436b90 ADD	%R13,%RAX

    (255) 0x436b93 CMP	%R12D,-0x40(%RBP)

    (255) 0x436b97 JNE	436acb

  (256) 0x436b9d MOV	%R14,-0x80(%RBP)

  (256) 0x436ba1 MOV	-0xb4(%RBP),%ECX

  (256) 0x436ba7 MOV	-0x34(%RBP),%EDX

  (256) 0x436baa MOV	%ECX,%ESI

  (256) 0x436bac LEA	0x1(%RCX),%EAX

  (256) 0x436baf CMP	%EDX,%ECX

  (256) 0x436bb1 JE	436d3c

0x436bb7 MOV	-0x34(%RBP),%R12D

0x436bbb SUB	%ESI,%R12D

0x436bbe LEA	-0x1(%R12),%R14D

0x436bc3 CMP	$0x2,%R14D

0x436bc7 JBE	436c59

0x436bcd MOV	%R8,%R14

0x436bd0 IMUL	%RSI,%R14

0x436bd4 MOV	-0x48(%RBP),%RDX

0x436bd8 MOV	-0x70(%RBP),%RCX

0x436bdc IMUL	%RDI,%RSI

0x436be0 ADD	%RDX,%RCX

0x436be3 LEA	(%R14,%RCX,8),%RDX

0x436be7 MOV	-0x60(%RBP),%RCX

0x436beb MOV	-0x78(%RBP),%R14

0x436bef ADD	%RCX,%RDX

0x436bf2 MOVSXD	-0x38(%RBP),%RCX

0x436bf6 VMOVSD	(%RDX),%XMM8

0x436bfa ADD	%R14,%RCX

0x436bfd IMUL	%RDI,%RCX

0x436c01 MOV	-0x58(%RBP),%R14

0x436c05 ADD	%R8,%RDX

0x436c08 ADD	%R14,%RCX

0x436c0b VMOVSD	(%RDX),%XMM9

0x436c0f ADD	%RSI,%RCX

0x436c12 ADD	%R8,%RDX

0x436c15 MOV	-0x68(%RBP),%RSI

0x436c19 VMOVSD	(%RDX),%XMM10

0x436c1d VMOVSD	(%RDX,%R8,1),%XMM11

0x436c23 MOV	-0xc8(%RBP),%RDX

0x436c2a LEA	(%RSI,%RCX,8),%RCX

0x436c2e MOV	%R12D,%R14D

0x436c31 VMOVSD	%XMM8,(%RCX)

0x436c35 AND	$-0x4,%R14D

0x436c39 ADD	%RDX,%RCX

0x436c3c VMOVSD	%XMM9,(%RCX)

0x436c40 ADD	%R14D,%EAX

0x436c43 ADD	%RDX,%RCX

0x436c46 AND	$0x3,%R12D

0x436c4a VMOVSD	%XMM10,(%RCX)

0x436c4e VMOVSD	%XMM11,(%RCX,%RDX,1)

0x436c53 JE	436d3c

0x436c59 MOV	-0xb8(%RBP),%ESI

0x436c5f MOV	-0x48(%RBP),%RCX

0x436c63 MOV	%ESI,%R12D

0x436c66 SUB	%EAX,%R12D

0x436c69 MOVSXD	%R12D,%RDX

0x436c6c MOV	-0xc0(%RBP),%R12

0x436c73 MOV	-0x60(%RBP),%R14

0x436c77 IMUL	%R12,%RDX

0x436c7b ADD	%RCX,%RDX

0x436c7e VMOVSD	(%R14,%RDX,8),%XMM12

0x436c84 MOV	-0x9c(%RBP),%EDX

0x436c8a MOV	-0x38(%RBP),%ECX

0x436c8d ADD	%EAX,%EDX

0x436c8f ADD	%ECX,%EDX

0x436c91 MOVSXD	%EDX,%R14

0x436c94 IMUL	%RDI,%R14

0x436c98 MOV	-0x58(%RBP),%RDX

0x436c9c MOV	-0x68(%RBP),%RCX

0x436ca0 ADD	%RDX,%R14

0x436ca3 LEA	0x1(%RAX),%EDX

0x436ca6 VMOVSD	%XMM12,(%RCX,%R14,8)

0x436cac CMP	%EDX,-0x34(%RBP)

0x436caf JL	436d3c

0x436cb5 MOV	-0xd0(%RBP),%R14D

0x436cbc SUB	%EAX,%R14D

0x436cbf MOVSXD	%R14D,%RCX

0x436cc2 IMUL	%R12,%RCX

0x436cc6 MOV	-0x48(%RBP),%R14

0x436cca ADD	$0x2,%EAX

0x436ccd ADD	%R14,%RCX

0x436cd0 MOV	-0x60(%RBP),%R14

0x436cd4 VMOVSD	(%R14,%RCX,8),%XMM13

0x436cda MOV	-0x9c(%RBP),%ECX

0x436ce0 MOV	-0x38(%RBP),%R14D

0x436ce4 ADD	%ECX,%EDX

0x436ce6 ADD	%R14D,%EDX

0x436ce9 MOVSXD	%EDX,%RDX

0x436cec IMUL	%RDI,%RDX

0x436cf0 MOV	-0x58(%RBP),%R14

0x436cf4 ADD	%R14,%RDX

0x436cf7 MOV	-0x68(%RBP),%R14

0x436cfb VMOVSD	%XMM13,(%R14,%RDX,8)

0x436d01 CMP	%EAX,-0x34(%RBP)

0x436d04 JL	436d3c

0x436d06 SUB	%EAX,%ESI

0x436d08 ADD	%ECX,%EAX

0x436d0a MOV	-0x38(%RBP),%ECX

0x436d0d MOVSXD	%ESI,%RSI

0x436d10 IMUL	%R12,%RSI

0x436d14 ADD	%ECX,%EAX

0x436d16 MOV	-0x48(%RBP),%R12

0x436d1a CLTQ

0x436d1c IMUL	%RDI,%RAX

0x436d20 MOV	-0x60(%RBP),%RDX

0x436d24 ADD	%R12,%RSI

0x436d27 MOV	-0x58(%RBP),%R14

0x436d2b VMOVSD	(%RDX,%RSI,8),%XMM14

0x436d30 MOV	-0x68(%RBP),%RSI

0x436d34 ADD	%R14,%RAX

0x436d37 VMOVSD	%XMM14,(%RSI,%RAX,8)

  (256) 0x436d3c MOV	-0x34(%RBP),%EAX

  (256) 0x436d3f TEST	%EAX,%EAX

  (256) 0x436d41 JNS	436d98

  (256) 0x436d98 INCL	-0x4c(%RBP)

  (256) 0x436d9b MOV	-0x98(%RBP),%RSI

  (256) 0x436da2 MOV	-0x34(%RBP),%EAX

  (256) 0x436da5 ADD	%RSI,-0x48(%RBP)

  (256) 0x436da9 MOV	-0x4c(%RBP),%R14D

  (256) 0x436dad ADD	%EAX,-0x38(%RBP)

  (256) 0x436db0 CMP	%R14D,-0x50(%RBP)

  (256) 0x436db4 JLE	436deb

  (256) 0x436db6 MOV	-0xd8(%RBP),%EDX

  (256) 0x436dbc CMPL	$0x6,-0xa0(%RBP)

  (256) 0x436dc3 MOV	%EDX,-0xd4(%RBP)

  (256) 0x436dc9 MOVB	$0x1,-0xc9(%RBP)

  (256) 0x436dd0 JA	4369dd

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 155 - 160

--------------------------------------------------------------------------------

155:     !$OMP PARALLEL DO PRIVATE(index)

156:     DO k=y_min-depth,y_max+y_inc+depth

157:     !$OMP SIMD

158:       DO j=1,depth

159:         index= buffer_offset + j+(k+depth-1)*depth

160:         right_snd_buffer(index)=field(x_max+1-j,k)

Coverage (%)	Name	Source Location	Module
○97.09	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.91	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	2.84
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P1,
Function	__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0
Source	pack_kernel.f90:159-160
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.97
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	17.97
CQA cycles if fully vectorized	1.21
Front-end cycles	16.83
P0 cycles	10.60
P1 cycles	17.97
P2 cycles	12.67
P3 cycles	12.67
P4 cycles	3.50
P5 cycles	10.60
P6 cycles	10.60
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	10.60
P11 cycles	12.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	101.00
Nb uops	101.00
Nb loads	38.00
Nb stores	7.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.59
Bytes prefetched	0.00
Bytes loaded	260.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.46
Vector-efficiency ratio load	11.11
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.81

Metric	Value
CQA speedup if no scalar integer	2.84
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P1,
Function	__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0
Source	pack_kernel.f90:159-160
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.97
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	17.97
CQA cycles if fully vectorized	1.21
Front-end cycles	16.83
P0 cycles	10.60
P1 cycles	17.97
P2 cycles	12.67
P3 cycles	12.67
P4 cycles	3.50
P5 cycles	10.60
P6 cycles	10.60
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	10.60
P11 cycles	12.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	101.00
Nb uops	101.00
Nb loads	38.00
Nb stores	7.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.59
Bytes prefetched	0.00
Bytes loaded	260.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.46
Vector-efficiency ratio load	11.11
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.81

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0
Source file and lines	pack_kernel.f90:155-160
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:155-160.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:159-160.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.97 to 6.33 cycles (2.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 17.97 to 1.21 cycles (14.87x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 260 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	101
nb uops	101
loop length	389
used x86 registers	9
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.60	10.60	12.67	12.67	3.50	10.60	10.60	3.50	3.50	3.50	10.60	12.67
cycles	10.60	17.97	12.67	12.67	3.50	10.60	10.60	3.50	3.50	3.50	10.60	12.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	17.97
Overall L1	17.97

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.97 cycles. At this rate:

7% of peak load performance is reached (14.47 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 436bb7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x34(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ESI,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%R12),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 436c59 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x679>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R14,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R14,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R14,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x68(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDX,%R8,1),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xc8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM8,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x4,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM9,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM10,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM11,(%RCX,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 436d3c <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x75c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb8(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ESI,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EAX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R12D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV -0xc0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R12,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R14,%RDX,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x9c(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EDX,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RDI,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM12,(%RCX,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %EDX,-0x34(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JL 436d3c <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x75c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xd0(%RBP),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R14D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R12,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R14,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x60(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R14,%RCX,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x9c(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RDI,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x68(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM13,(%R14,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %EAX,-0x34(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JL 436d3c <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x75c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %EAX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R12,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x48(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX,%RSI,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM14,(%RSI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)

Function	__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0
Source file and lines	pack_kernel.f90:155-160
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.97 to 6.33 cycles (2.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:160

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 260 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	101
nb uops	101
loop length	389
used x86 registers	9
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.60	10.60	12.67	12.67	3.50	10.60	10.60	3.50	3.50	3.50	10.60	12.67
cycles	10.60	17.97	12.67	12.67	3.50	10.60	10.60	3.50	3.50	3.50	10.60	12.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	17.97
Overall L1	17.97

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.97 cycles. At this rate:

7% of peak load performance is reached (14.47 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 436bb7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x34(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ESI,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%R12),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 436c59 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x679>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R14,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R14,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R14,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x68(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDX,%R8,1),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xc8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM8,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x4,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM9,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM10,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM11,(%RCX,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 436d3c <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x75c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb8(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ESI,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EAX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R12D,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV -0xc0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R12,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R14,%RDX,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x9c(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EDX,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RDI,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM12,(%RCX,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %EDX,-0x34(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JL 436d3c <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x75c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xd0(%RBP),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R14D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R12,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R14,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x60(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R14,%RCX,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x9c(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RDI,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x68(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM13,(%R14,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %EAX,-0x34(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JL 436d3c <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x75c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %EAX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R12,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x48(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX,%RSI,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM14,(%RSI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code