OV - exec - Loop 168

	Loop Id: 168	Module: exec	Source: flux_calc_kernel.f90:58-60	Coverage: 4.02%

0x42b9a2 VMULSD	(%RAX),%XMM2,%XMM6    [1]

0x42b9a6 VMOVUPD	(%R12,%RDX,1),%ZMM7    [7]

0x42b9ad VMOVUPD	(%R10,%RDX,1),%ZMM9    [5]

0x42b9b4 VADDPD	(%R11,%RDX,1),%ZMM7,%ZMM8    [12]

0x42b9bb VADDPD	(%R9,%RDX,1),%ZMM9,%ZMM10    [14]

0x42b9c2 VBROADCASTSD	%XMM6,%ZMM12

0x42b9c8 VMULPD	(%RBX,%RDX,1),%ZMM12,%ZMM13    [16]

0x42b9cf VADDPD	%ZMM10,%ZMM8,%ZMM11

0x42b9d5 MOV	0x208(%RSP),%RCX    [15]

0x42b9dd VMULPD	%ZMM13,%ZMM11,%ZMM14

0x42b9e3 VMOVUPD	%ZMM14,(%R14,%RDX,1)    [10]

0x42b9ea VMULSD	(%RAX),%XMM2,%XMM15    [1]

0x42b9ee VMOVUPD	(%R8,%RDX,1),%ZMM0    [13]

0x42b9f5 VMOVUPD	(%RSI,%RDX,1),%ZMM3    [9]

0x42b9fc VADDPD	(%RDI,%RDX,1),%ZMM0,%ZMM1    [4]

0x42ba03 VADDPD	(%RCX,%RDX,1),%ZMM3,%ZMM4    [6]

0x42ba0a VBROADCASTSD	%XMM15,%ZMM7

0x42ba10 VMULPD	(%R13,%RDX,1),%ZMM7,%ZMM8    [8]

0x42ba18 VADDPD	%ZMM4,%ZMM1,%ZMM6

0x42ba1e VMULPD	%ZMM8,%ZMM6,%ZMM9

0x42ba24 VMOVUPD	%ZMM9,(%R15,%RDX,1)    [11]

0x42ba2b VMULSD	(%RAX),%XMM2,%XMM10    [1]

0x42ba2f VMOVUPD	0x40(%RDX,%R12,1),%ZMM11    [3]

0x42ba37 VMOVUPD	0x40(%R10,%RDX,1),%ZMM13    [5]

0x42ba3f VADDPD	0x40(%RDX,%R11,1),%ZMM11,%ZMM12    [3]

0x42ba47 VADDPD	0x40(%R9,%RDX,1),%ZMM13,%ZMM14    [14]

0x42ba4f VBROADCASTSD	%XMM10,%ZMM0

0x42ba55 VMULPD	0x40(%RDX,%RBX,1),%ZMM0,%ZMM1    [3]

0x42ba5d VADDPD	%ZMM14,%ZMM12,%ZMM15

0x42ba63 VMULPD	%ZMM1,%ZMM15,%ZMM3

0x42ba69 VMOVUPD	%ZMM3,0x40(%RDX,%R14,1)    [3]

0x42ba71 VMULSD	(%RAX),%XMM2,%XMM4    [1]

0x42ba75 VMOVUPD	0x40(%R8,%RDX,1),%ZMM6    [13]

0x42ba7d VMOVUPD	0x40(%RSI,%RDX,1),%ZMM8    [9]

0x42ba85 VADDPD	0x40(%RDI,%RDX,1),%ZMM6,%ZMM7    [4]

0x42ba8d VADDPD	0x40(%RCX,%RDX,1),%ZMM8,%ZMM9    [6]

0x42ba95 VBROADCASTSD	%XMM4,%ZMM11

0x42ba9b VMULPD	0x40(%RDX,%R13,1),%ZMM11,%ZMM12    [3]

0x42baa3 VADDPD	%ZMM9,%ZMM7,%ZMM10

0x42baa9 MOV	0x220(%RSP),%RCX    [15]

0x42bab1 SUB	$-0x80,%RDX

0x42bab5 VMULPD	%ZMM12,%ZMM10,%ZMM13

0x42babb VMOVUPD	%ZMM13,-0x40(%RDX,%R15,1)    [2]

0x42bac3 CMP	%RCX,%RDX

0x42bac6 JNE	42b9a2

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 58 - 60

--------------------------------------------------------------------------------

58:           *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1))

59:         vol_flux_y(j,k)=0.25_8*dt*yarea(j,k)                  &

60:           *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k))

Coverage (%)	Name	Source Location	Module
○97.67	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.33	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0,
Function	__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0
Source	flux_calc_kernel.f90:58-60
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.06
CQA cycles if fully vectorized	10.50
Front-end cycles	9.33
P0 cycles	12.50
P1 cycles	12.00
P2 cycles	8.67
P3 cycles	8.67
P4 cycles	2.00
P5 cycles	12.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	8.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	44.00
Nb loads	26.00
Nb stores	4.00
Nb stack references	2.00
FLOP/cycle	13.12
Nb FLOP add-sub	96.00
Nb FLOP mul	68.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	126.72
Bytes prefetched	0.00
Bytes loaded	1328.00
Bytes stored	256.00
Stride 0	2.00
Stride 1	6.00
Stride n	8.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	80.00
Vectorization ratio load	83.33
Vectorization ratio store	100.00
Vectorization ratio mul	66.67
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	82.50
Vector-efficiency ratio load	85.42
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	70.83
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0,
Function	__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0
Source	flux_calc_kernel.f90:58-60
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.06
CQA cycles if fully vectorized	10.50
Front-end cycles	9.33
P0 cycles	12.50
P1 cycles	12.00
P2 cycles	8.67
P3 cycles	8.67
P4 cycles	2.00
P5 cycles	12.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	8.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	44.00
Nb loads	26.00
Nb stores	4.00
Nb stack references	2.00
FLOP/cycle	13.12
Nb FLOP add-sub	96.00
Nb FLOP mul	68.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	126.72
Bytes prefetched	0.00
Bytes loaded	1328.00
Bytes stored	256.00
Stride 0	2.00
Stride 1	6.00
Stride n	8.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	80.00
Vectorization ratio load	83.33
Vectorization ratio store	100.00
Vectorization ratio mul	66.67
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	82.50
Vector-efficiency ratio load	85.42
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	70.83
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0
Source file and lines	flux_calc_kernel.f90:58-60
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:58-60.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 82% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.50 to 10.50 cycles (1.19x speedup).

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

83% of SSE/AVX loads are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Use vector aligned instructions:
1. The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
2. Use another compiler or locally use C code (for instance via libraries)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 20 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

96: addition or subtraction
68: multiply

The binary loop is loading 1328 bytes (166 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	45
nb uops	44
loop length	298
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	14
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.50	3.50	8.67	8.67	2.00	12.00	1.00	2.00	2.00	2.00	0.00	8.67
cycles	12.50	12.00	8.67	8.67	2.00	12.00	1.00	2.00	2.00	2.00	0.00	8.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.33
Dispatch	12.50
Data deps.	1.00
Overall L1	12.50

Vectorization ratios

all	80%
load	83%
store	100%
mul	66%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	82%
load	85%
store	100%
mul	70%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

55% of peak load performance is reached (106.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (20.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42b9a2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMULSD (%RAX),%XMM2,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD (%R12,%RDX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R10,%RDX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%R11,%RDX,1),%ZMM7,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R9,%RDX,1),%ZMM9,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VBROADCASTSD %XMM6,%ZMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULPD (%RBX,%RDX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM10,%ZMM8,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x208(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPD %ZMM13,%ZMM11,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%R14,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULSD (%RAX),%XMM2,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD (%R8,%RDX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RSI,%RDX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RDX,1),%ZMM0,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%RCX,%RDX,1),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VBROADCASTSD %XMM15,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULPD (%R13,%RDX,1),%ZMM7,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM1,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM6,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM9,(%R15,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULSD (%RAX),%XMM2,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD 0x40(%RDX,%R12,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R10,%RDX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0x40(%RDX,%R11,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%R9,%RDX,1),%ZMM13,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VBROADCASTSD %XMM10,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULPD 0x40(%RDX,%RBX,1),%ZMM0,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM12,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM15,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,0x40(%RDX,%R14,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULSD (%RAX),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD 0x40(%R8,%RDX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%RSI,%RDX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0x40(%RDI,%RDX,1),%ZMM6,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%RCX,%RDX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VBROADCASTSD %XMM4,%ZMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULPD 0x40(%RDX,%R13,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM7,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x220(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB $-0x80,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD %ZMM12,%ZMM10,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM13,-0x40(%RDX,%R15,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 42b9a2 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x612>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0
Source file and lines	flux_calc_kernel.f90:58-60
Module	exec

gain
potential
hint
expert

Vectorization

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

83% of SSE/AVX loads are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Use vector aligned instructions:
1. The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
2. Use another compiler or locally use C code (for instance via libraries)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

96: addition or subtraction
68: multiply

The binary loop is loading 1328 bytes (166 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	45
nb uops	44
loop length	298
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	14
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.50	3.50	8.67	8.67	2.00	12.00	1.00	2.00	2.00	2.00	0.00	8.67
cycles	12.50	12.00	8.67	8.67	2.00	12.00	1.00	2.00	2.00	2.00	0.00	8.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.33
Dispatch	12.50
Data deps.	1.00
Overall L1	12.50

Vectorization ratios

all	80%
load	83%
store	100%
mul	66%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	82%
load	85%
store	100%
mul	70%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

55% of peak load performance is reached (106.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (20.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42b9a2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMULSD (%RAX),%XMM2,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD (%R12,%RDX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R10,%RDX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%R11,%RDX,1),%ZMM7,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%R9,%RDX,1),%ZMM9,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VBROADCASTSD %XMM6,%ZMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULPD (%RBX,%RDX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM10,%ZMM8,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x208(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPD %ZMM13,%ZMM11,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%R14,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULSD (%RAX),%XMM2,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD (%R8,%RDX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%RSI,%RDX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RDX,1),%ZMM0,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD (%RCX,%RDX,1),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VBROADCASTSD %XMM15,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULPD (%R13,%RDX,1),%ZMM7,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM1,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM6,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM9,(%R15,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULSD (%RAX),%XMM2,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD 0x40(%RDX,%R12,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R10,%RDX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0x40(%RDX,%R11,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%R9,%RDX,1),%ZMM13,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VBROADCASTSD %XMM10,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULPD 0x40(%RDX,%RBX,1),%ZMM0,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM12,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM15,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,0x40(%RDX,%R14,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULSD (%RAX),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVUPD 0x40(%R8,%RDX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%RSI,%RDX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD 0x40(%RDI,%RDX,1),%ZMM6,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD 0x40(%RCX,%RDX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VBROADCASTSD %XMM4,%ZMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULPD 0x40(%RDX,%R13,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM7,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x220(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB $-0x80,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD %ZMM12,%ZMM10,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM13,-0x40(%RDX,%R15,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 42b9a2 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x612>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code