OV - exec - Loop 155

	Loop Id: 155	Module: exec	Source: calc_dt_kernel.f90:99-129	Coverage: 3.43%

0x429398 MOV	-0x40(%RBP),%RDX    [9]

0x42939c VMOVSD	(%RDX),%XMM29    [7]

0x4293a2 VMINSD	%XMM21,%XMM29,%XMM30

0x4293a8 LEA	0x1(%RAX),%RDX

0x4293ac VMINSD	%XMM3,%XMM30,%XMM31

0x4293b2 VMINSD	%XMM31,%XMM9,%XMM9

0x4293b8 CMP	%RAX,-0x38(%RBP)    [9]

0x4293bc JE	4294d0

0x4293c2 MOV	%RDX,%RAX

0x4293c5 VMOVSD	(%R13,%RAX,8),%XMM1    [10]

0x4293cc VMOVSD	(%RBX,%RAX,8),%XMM18    [15]

0x4293d3 VADDSD	%XMM1,%XMM1,%XMM3

0x4293d7 VMOVAPD	%XMM4,%XMM1

0x4293db VMOVSD	0x8(%R8,%RAX,8),%XMM4    [14]

0x4293e2 VDIVSD	(%R12,%RAX,8),%XMM3,%XMM0    [4]

0x4293e8 VADDSD	0x8(%R9,%RAX,8),%XMM4,%XMM3    [2]

0x4293ef VMULSD	%XMM18,%XMM8,%XMM20

0x4293f5 VMOVSD	(%R14,%RAX,8),%XMM2    [12]

0x4293fb VMULSD	0x8(%RDI,%RAX,8),%XMM3,%XMM4    [5]

0x429401 VFMADD132SD	%XMM2,%XMM0,%XMM2

0x429406 VANDPD	%XMM5,%XMM1,%XMM0

0x42940a VMAXSD	%XMM20,%XMM0,%XMM0

0x429410 VMULSD	%XMM18,%XMM11,%XMM17

0x429416 VANDPD	%XMM5,%XMM4,%XMM3

0x42941a VMAXSD	%XMM3,%XMM0,%XMM0

0x42941e VMOVAPD	%XMM6,%XMM3

0x429422 VMOVSD	0x8(%RSI,%RAX,8),%XMM6    [6]

0x429428 VDIVSD	%XMM0,%XMM17,%XMM21

0x42942e VADDSD	%XMM6,%XMM3,%XMM0

0x429432 VMOVAPD	%XMM7,%XMM3

0x429436 VMOVSD	0x8(%RCX,%RAX,8),%XMM7    [3]

0x42943c VMULSD	(%R11,%RAX,8),%XMM0,%XMM0    [8]

0x429442 VADDSD	%XMM7,%XMM3,%XMM3

0x429446 VMINSD	(%R15,%RAX,8),%XMM14,%XMM23    [13]

0x42944d VSQRTSD	%XMM2,%XMM2,%XMM2

0x429451 VMULSD	(%R10,%RAX,8),%XMM3,%XMM3    [1]

0x429457 VSUBSD	%XMM0,%XMM4,%XMM19

0x42945d VANDPD	%XMM5,%XMM0,%XMM0

0x429461 VADDSD	%XMM18,%XMM18,%XMM25

0x429467 VMULSD	%XMM18,%XMM10,%XMM22

0x42946d VSUBSD	%XMM1,%XMM3,%XMM1

0x429471 VANDPD	%XMM5,%XMM3,%XMM3

0x429475 VMAXSD	%XMM0,%XMM3,%XMM3

0x429479 VADDSD	%XMM19,%XMM1,%XMM1

0x42947f VMULSD	%XMM13,%XMM23,%XMM24

0x429485 VMAXSD	%XMM20,%XMM3,%XMM0

0x42948b VMAXSD	%XMM2,%XMM8,%XMM2

0x42948f VDIVSD	%XMM25,%XMM1,%XMM26

0x429495 VDIVSD	%XMM0,%XMM22,%XMM3

0x42949b VCOMISD	%XMM26,%XMM12

0x4294a1 VDIVSD	%XMM2,%XMM24,%XMM0

0x4294a7 VMINSD	%XMM0,%XMM3,%XMM3

0x4294ab JBE	429398

0x4294b1 VDIVSD	%XMM26,%XMM16,%XMM27

0x4294b7 MOV	-0x48(%RBP),%RDX    [9]

0x4294bb VXORPD	%XMM15,%XMM27,%XMM28

0x4294c1 VMULSD	(%RDX),%XMM28,%XMM29    [11]

0x4294c7 JMP	4293a2

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 99 - 129

--------------------------------------------------------------------------------

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

Coverage (%)	Name	Source Location	Module
○97.61	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.04
Bottlenecks
Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source	calc_dt_kernel.f90:99-129
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	26.50
CQA cycles if no scalar integer	26.50
CQA cycles if FP arith vectorized	13.25
CQA cycles if fully vectorized	13.25
Front-end cycles	10.08
P0 cycles	13.00
P1 cycles	13.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	0.00
P5 cycles	12.50
P6 cycles	2.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	5.00
DIV/SQRT cycles	26.50
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.50
Nb uops	54.50
Nb loads	15.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.91
Nb FLOP add-sub	8.00
Nb FLOP mul	7.50
Nb FLOP fma	1.00
Nb FLOP div	5.50
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.55
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	13.00
Stride indirect	0.00
Vectorization ratio all	15.61
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	40.50
Vector-efficiency ratio all	14.45
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.56

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.11
Bottlenecks	P0,
Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source	calc_dt_kernel.f90:99-129
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	14.25
CQA cycles if fully vectorized	14.25
Front-end cycles	10.33
P0 cycles	13.50
P1 cycles	13.50
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	0.00
P5 cycles	13.00
P6 cycles	2.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	5.00
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	56.00
Nb loads	15.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.88
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	1.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.21
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	13.00
Stride indirect	0.00
Vectorization ratio all	16.33
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	42.11
Vector-efficiency ratio all	14.54
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.76

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.96
Bottlenecks	P0,
Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source	calc_dt_kernel.f90:99-129
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.50
CQA cycles if no scalar integer	24.50
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	12.25
Front-end cycles	9.83
P0 cycles	12.50
P1 cycles	12.50
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	0.00
P5 cycles	12.00
P6 cycles	2.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	5.00
DIV/SQRT cycles	24.50
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	53.00
Nb loads	15.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.94
Nb FLOP add-sub	8.00
Nb FLOP mul	7.00
Nb FLOP fma	1.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.90
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	13.00
Stride indirect	0.00
Vectorization ratio all	14.89
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	38.89
Vector-efficiency ratio all	14.36
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.36

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source file and lines	calc_dt_kernel.f90:99-129
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:99-129.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 26.50 to 13.25 cycles (2.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 26.50 to 12.92 cycles (2.05x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

34 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

9: addition or subtraction (1 inside FMA instructions)
8.50: multiply (1 inside FMA instructions)
5.50: divide
1: square root

The binary loop is loading 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	54.50
nb uops	54.50
loop length	289.50
used x86 registers	15
used mmx registers	0
used xmm registers	30
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.07

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	10.08 cycles
front end	10.08 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.00	13.00	5.00	5.00	0.00	12.50	2.00	0.00	0.00	0.00	1.00	5.00
cycles	13.00	13.00	5.00	5.00	0.00	12.50	2.00	0.00	0.00	0.00	1.00	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	26.50
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	10.08
Dispatch	13.00
DIV/SQRT	26.50
Data deps.	4.00
Overall L1	26.50

Vectorization ratios

all	15%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	40%

Vector efficiency ratios

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 26.50 cycles. At this rate:

2% of peak load performance is reached (4.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source file and lines	calc_dt_kernel.f90:99-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 28.50 to 13.50 cycles (2.11x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.50 to 13.33 cycles (2.14x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

35 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

9: addition or subtraction (1 inside FMA instructions)
9: multiply (1 inside FMA instructions)
6: divide
1: square root

The binary loop is loading 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	56
nb uops	56
loop length	298
used x86 registers	15
used mmx registers	0
used xmm registers	32
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.33 cycles
front end	10.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.50	13.50	5.00	5.00	0.00	13.00	2.00	0.00	0.00	0.00	1.00	5.00
cycles	13.50	13.50	5.00	5.00	0.00	13.00	2.00	0.00	0.00	0.00	1.00	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	10.33
Dispatch	13.50
DIV/SQRT	28.50
Data deps.	4.00
Overall L1	28.50

Vectorization ratios

all	16%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	42%

Vector efficiency ratios

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

2% of peak load performance is reached (4.21 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4293c5

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMINSD %XMM21,%XMM29,%XMM30	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x1(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMINSD %XMM3,%XMM30,%XMM31	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM31,%XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RAX,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JE 4294d0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x4e0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R13,%RAX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RBX,%RAX,8),%XMM18	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM1,%XMM1,%XMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVAPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD 0x8(%R8,%RAX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD (%R12,%RAX,8),%XMM3,%XMM0	1	1	0	0.33	0.33	0	0	0	0.33	13-15	4	scal (12.5%)
VADDSD 0x8(%R9,%RAX,8),%XMM4,%XMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
VMULSD %XMM18,%XMM8,%XMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD 0x8(%RDI,%RAX,8),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD132SD %XMM2,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM5,%XMM1,%XMM0	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM20,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM18,%XMM11,%XMM17	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM5,%XMM4,%XMM3	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM3,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD 0x8(%RSI,%RAX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD %XMM0,%XMM17,%XMM21	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VADDSD %XMM6,%XMM3,%XMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVAPD %XMM7,%XMM3	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD 0x8(%RCX,%RAX,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%R11,%RAX,8),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM7,%XMM3,%XMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD (%R15,%RAX,8),%XMM14,%XMM23	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VSQRTSD %XMM2,%XMM2,%XMM2	1	1	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMULSD (%R10,%RAX,8),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM4,%XMM19	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM5,%XMM0,%XMM0	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM18,%XMM18,%XMM25	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM18,%XMM10,%XMM22	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM3,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM5,%XMM3,%XMM3	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM0,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM19,%XMM1,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM13,%XMM23,%XMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMAXSD %XMM20,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMAXSD %XMM2,%XMM8,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM25,%XMM1,%XMM26	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VDIVSD %XMM0,%XMM22,%XMM3	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VCOMISD %XMM26,%XMM12	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
VDIVSD %XMM2,%XMM24,%XMM0	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMINSD %XMM0,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
JBE 429398 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x3a8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VDIVSD %XMM26,%XMM16,%XMM27	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VXORPD %XMM15,%XMM27,%XMM28	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
VMULSD (%RDX),%XMM28,%XMM29	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
JMP 4293a2 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x3b2>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source file and lines	calc_dt_kernel.f90:99-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.50 to 12.50 cycles (1.96x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

33 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 23 FP arithmetical operations:

9: addition or subtraction (1 inside FMA instructions)
8: multiply (1 inside FMA instructions)
5: divide
1: square root

The binary loop is loading 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	53
nb uops	53
loop length	281
used x86 registers	15
used mmx registers	0
used xmm registers	28
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.50	12.50	5.00	5.00	0.00	12.00	2.00	0.00	0.00	0.00	1.00	5.00
cycles	12.50	12.50	5.00	5.00	0.00	12.00	2.00	0.00	0.00	0.00	1.00	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	24.50
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	9.83
Dispatch	12.50
DIV/SQRT	24.50
Data deps.	4.00
Overall L1	24.50

Vectorization ratios

all	14%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	38%

Vector efficiency ratios

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.50 cycles. At this rate:

2% of peak load performance is reached (4.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4293c5

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x40(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX),%XMM29	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM21,%XMM29,%XMM30	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x1(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMINSD %XMM3,%XMM30,%XMM31	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM31,%XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RAX,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JE 4294d0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x4e0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R13,%RAX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RBX,%RAX,8),%XMM18	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM1,%XMM1,%XMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVAPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD 0x8(%R8,%RAX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD (%R12,%RAX,8),%XMM3,%XMM0	1	1	0	0.33	0.33	0	0	0	0.33	13-15	4	scal (12.5%)
VADDSD 0x8(%R9,%RAX,8),%XMM4,%XMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
VMULSD %XMM18,%XMM8,%XMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD 0x8(%RDI,%RAX,8),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD132SD %XMM2,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM5,%XMM1,%XMM0	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM20,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM18,%XMM11,%XMM17	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM5,%XMM4,%XMM3	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM3,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD 0x8(%RSI,%RAX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD %XMM0,%XMM17,%XMM21	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VADDSD %XMM6,%XMM3,%XMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVAPD %XMM7,%XMM3	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD 0x8(%RCX,%RAX,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%R11,%RAX,8),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM7,%XMM3,%XMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD (%R15,%RAX,8),%XMM14,%XMM23	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VSQRTSD %XMM2,%XMM2,%XMM2	1	1	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMULSD (%R10,%RAX,8),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM4,%XMM19	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM5,%XMM0,%XMM0	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM18,%XMM18,%XMM25	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM18,%XMM10,%XMM22	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM3,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM5,%XMM3,%XMM3	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM0,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM19,%XMM1,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM13,%XMM23,%XMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMAXSD %XMM20,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMAXSD %XMM2,%XMM8,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM25,%XMM1,%XMM26	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VDIVSD %XMM0,%XMM22,%XMM3	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VCOMISD %XMM26,%XMM12	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
VDIVSD %XMM2,%XMM24,%XMM0	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMINSD %XMM0,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
JBE 429398 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x3a8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code