OV - exec - Loop 122

	Loop Id: 122	Module: exec	Source: advec_mom_kernel.f90:106-107	Coverage: 2.57%

0x423476 VMOVUPD	(%R8,%RAX,1),%ZMM15    [6]

0x42347d VMOVUPD	%ZMM15,(%RDI,%RAX,1)    [3]

0x423484 VADDPD	(%RSI,%RAX,1),%ZMM15,%ZMM1    [2]

0x42348b VSUBPD	(%RCX,%RAX,1),%ZMM1,%ZMM0    [1]

0x423492 VMOVUPD	%ZMM0,(%RDX,%RAX,1)    [4]

0x423499 VMOVUPD	0x40(%R8,%RAX,1),%ZMM2    [6]

0x4234a1 VMOVUPD	%ZMM2,0x40(%RDI,%RAX,1)    [3]

0x4234a9 VADDPD	0x40(%RSI,%RAX,1),%ZMM2,%ZMM3    [2]

0x4234b1 VSUBPD	0x40(%RCX,%RAX,1),%ZMM3,%ZMM4    [1]

0x4234b9 VMOVUPD	%ZMM4,0x40(%RDX,%RAX,1)    [4]

0x4234c1 VMOVUPD	0x80(%R8,%RAX,1),%ZMM5    [6]

0x4234c9 VMOVUPD	%ZMM5,0x80(%RDI,%RAX,1)    [3]

0x4234d1 VADDPD	0x80(%RSI,%RAX,1),%ZMM5,%ZMM6    [2]

0x4234d9 VSUBPD	0x80(%RCX,%RAX,1),%ZMM6,%ZMM7    [1]

0x4234e1 VMOVUPD	%ZMM7,0x80(%RDX,%RAX,1)    [4]

0x4234e9 VMOVUPD	0xc0(%R8,%RAX,1),%ZMM8    [6]

0x4234f1 VMOVUPD	%ZMM8,0xc0(%RDI,%RAX,1)    [3]

0x4234f9 VADDPD	0xc0(%RSI,%RAX,1),%ZMM8,%ZMM9    [2]

0x423501 VSUBPD	0xc0(%RCX,%RAX,1),%ZMM9,%ZMM10    [1]

0x423509 VMOVUPD	%ZMM10,0xc0(%RDX,%RAX,1)    [4]

0x423511 VMOVUPD	0x100(%R8,%RAX,1),%ZMM11    [6]

0x423519 VMOVUPD	%ZMM11,0x100(%RDI,%RAX,1)    [3]

0x423521 VADDPD	0x100(%RSI,%RAX,1),%ZMM11,%ZMM12    [2]

0x423529 VSUBPD	0x100(%RCX,%RAX,1),%ZMM12,%ZMM13    [1]

0x423531 VMOVUPD	%ZMM13,0x100(%RDX,%RAX,1)    [4]

0x423539 VMOVUPD	0x140(%R8,%RAX,1),%ZMM14    [6]

0x423541 VMOVUPD	%ZMM14,0x140(%RDI,%RAX,1)    [3]

0x423549 VADDPD	0x140(%RSI,%RAX,1),%ZMM14,%ZMM15    [2]

0x423551 VSUBPD	0x140(%RCX,%RAX,1),%ZMM15,%ZMM1    [1]

0x423559 VMOVUPD	%ZMM1,0x140(%RDX,%RAX,1)    [4]

0x423561 VMOVUPD	0x180(%R8,%RAX,1),%ZMM0    [6]

0x423569 VMOVUPD	%ZMM0,0x180(%RDI,%RAX,1)    [3]

0x423571 VADDPD	0x180(%RSI,%RAX,1),%ZMM0,%ZMM2    [2]

0x423579 MOV	0x140(%RSP),%R9    [5]

0x423581 VSUBPD	0x180(%RCX,%RAX,1),%ZMM2,%ZMM3    [1]

0x423589 VMOVUPD	%ZMM3,0x180(%RDX,%RAX,1)    [4]

0x423591 VMOVUPD	0x1c0(%R8,%RAX,1),%ZMM4    [6]

0x423599 VMOVUPD	%ZMM4,0x1c0(%RDI,%RAX,1)    [3]

0x4235a1 VADDPD	0x1c0(%RSI,%RAX,1),%ZMM4,%ZMM5    [2]

0x4235a9 VSUBPD	0x1c0(%RCX,%RAX,1),%ZMM5,%ZMM6    [1]

0x4235b1 VMOVUPD	%ZMM6,0x1c0(%RDX,%RAX,1)    [4]

0x4235b9 ADD	$0x200,%RAX

0x4235bf CMP	%R9,%RAX

0x4235c2 JNE	423476

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 106 - 107

--------------------------------------------------------------------------------

106:           post_vol(j,k)=volume(j,k)

107:           pre_vol(j,k)=post_vol(j,k)+vol_flux_y(j  ,k+1)-vol_flux_y(j,k)

Coverage (%)	Name	Source Location	Module
○97.61	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:106-107
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.83
CQA cycles if no scalar integer	9.83
CQA cycles if FP arith vectorized	9.83
CQA cycles if fully vectorized	9.83
Front-end cycles	9.83
P0 cycles	8.00
P1 cycles	8.00
P2 cycles	8.33
P3 cycles	8.33
P4 cycles	8.00
P5 cycles	8.00
P6 cycles	1.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.40
P11 cycles	8.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	43.00
Nb loads	25.00
Nb stores	16.00
Nb stack references	1.00
FLOP/cycle	13.02
Nb FLOP add-sub	128.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	261.15
Bytes prefetched	0.00
Bytes loaded	1544.00
Bytes stored	1024.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:106-107
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.83
CQA cycles if no scalar integer	9.83
CQA cycles if FP arith vectorized	9.83
CQA cycles if fully vectorized	9.83
Front-end cycles	9.83
P0 cycles	8.00
P1 cycles	8.00
P2 cycles	8.33
P3 cycles	8.33
P4 cycles	8.00
P5 cycles	8.00
P6 cycles	1.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.40
P11 cycles	8.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	43.00
Nb loads	25.00
Nb stores	16.00
Nb stack references	1.00
FLOP/cycle	13.02
Nb FLOP add-sub	128.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	261.15
Bytes prefetched	0.00
Bytes loaded	1544.00
Bytes stored	1024.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:106-107
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106-107.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

128: addition or subtraction

The binary loop is loading 1544 bytes (193 double precision FP elements). The binary loop is storing 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	44
nb uops	43
loop length	338
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	0.60	8.33	8.33	8.00	8.00	1.00	8.00	8.00	8.00	0.40	8.33
cycles	8.00	8.00	8.33	8.33	8.00	8.00	1.00	8.00	8.00	8.00	0.40	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.83
Dispatch	8.33
Data deps.	1.00
Overall L1	9.83

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.83 cycles. At this rate:

81% of peak load performance is reached (157.02 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
81% of peak store performance is reached (104.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.83 to 8.33 cycles (1.18x speedup).

ASM code

In the binary file, the address of the loop is: 423476

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R8,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM15,(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD (%RSI,%RAX,1),%ZMM15,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%RCX,%RAX,1),%ZMM1,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM0,(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%R8,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x40(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x40(%RSI,%RAX,1),%ZMM2,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x40(%RCX,%RAX,1),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM4,0x40(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%R8,%RAX,1),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM5,0x80(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x80(%RSI,%RAX,1),%ZMM5,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x80(%RCX,%RAX,1),%ZMM6,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM7,0x80(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%R8,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM8,0xc0(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0xc0(%RSI,%RAX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0xc0(%RCX,%RAX,1),%ZMM9,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM10,0xc0(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x100(%R8,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x100(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x100(%RSI,%RAX,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x100(%RCX,%RAX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM13,0x100(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x140(%R8,%RAX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM14,0x140(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x140(%RSI,%RAX,1),%ZMM14,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x140(%RCX,%RAX,1),%ZMM15,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM1,0x140(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x180(%R8,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM0,0x180(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x180(%RSI,%RAX,1),%ZMM0,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x140(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBPD 0x180(%RCX,%RAX,1),%ZMM2,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM3,0x180(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x1c0(%R8,%RAX,1),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM4,0x1c0(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x1c0(%RSI,%RAX,1),%ZMM4,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x1c0(%RCX,%RAX,1),%ZMM5,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM6,0x1c0(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x200,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 423476 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3a76>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:106-107
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

128: addition or subtraction

The binary loop is loading 1544 bytes (193 double precision FP elements). The binary loop is storing 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	44
nb uops	43
loop length	338
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	0.60	8.33	8.33	8.00	8.00	1.00	8.00	8.00	8.00	0.40	8.33
cycles	8.00	8.00	8.33	8.33	8.00	8.00	1.00	8.00	8.00	8.00	0.40	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.83
Dispatch	8.33
Data deps.	1.00
Overall L1	9.83

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.83 cycles. At this rate:

81% of peak load performance is reached (157.02 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
81% of peak store performance is reached (104.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 423476

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R8,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM15,(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD (%RSI,%RAX,1),%ZMM15,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD (%RCX,%RAX,1),%ZMM1,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM0,(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%R8,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x40(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x40(%RSI,%RAX,1),%ZMM2,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x40(%RCX,%RAX,1),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM4,0x40(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%R8,%RAX,1),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM5,0x80(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x80(%RSI,%RAX,1),%ZMM5,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x80(%RCX,%RAX,1),%ZMM6,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM7,0x80(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%R8,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM8,0xc0(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0xc0(%RSI,%RAX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0xc0(%RCX,%RAX,1),%ZMM9,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM10,0xc0(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x100(%R8,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x100(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x100(%RSI,%RAX,1),%ZMM11,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x100(%RCX,%RAX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM13,0x100(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x140(%R8,%RAX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM14,0x140(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x140(%RSI,%RAX,1),%ZMM14,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x140(%RCX,%RAX,1),%ZMM15,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM1,0x140(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x180(%R8,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM0,0x180(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x180(%RSI,%RAX,1),%ZMM0,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x140(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBPD 0x180(%RCX,%RAX,1),%ZMM2,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM3,0x180(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x1c0(%R8,%RAX,1),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD %ZMM4,0x1c0(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VADDPD 0x1c0(%RSI,%RAX,1),%ZMM4,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VSUBPD 0x1c0(%RCX,%RAX,1),%ZMM5,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM6,0x1c0(%RDX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x200,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 423476 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3a76>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code