OV - exec - Loop 112

	Loop Id: 112	Module: exec	Source: advec_mom_kernel.f90:172-240 [...]	Coverage: 2.95%

0x421520 MOVSXD	0x140(%RSP),%R10    [7]

0x421528 MOV	0x160(%RSP),%R13    [7]

0x421530 MOV	%R10D,%EAX

0x421533 MOV	%R12,%RDI

0x421536 MOV	%RBX,%RSI

0x421539 CLTQ

0x42153b IMUL	%R13,%RSI

0x42153f IMUL	%RBX,%RAX

0x421543 IMUL	%RBX,%RDI

0x421547 MOV	0x170(%RSP),%RDX    [7]

0x42154f ADD	%RCX,%RDX

0x421552 ADD	%RDX,%RSI

0x421555 ADD	%RDX,%RAX

0x421558 ADD	%RDI,%RDX

0x42155b VMOVSD	(%R11,%RSI,8),%XMM1    [3]

0x421561 VMOVSD	(%R11,%RDX,8),%XMM4    [3]

0x421567 VSUBSD	(%R11,%RAX,8),%XMM1,%XMM15    [3]

0x42156d VSUBSD	%XMM1,%XMM4,%XMM0

0x421571 VMULSD	%XMM15,%XMM0,%XMM5

0x421576 VCOMISD	%XMM9,%XMM5

0x42157b JBE	421622

0x421581 VCOMISD	%XMM0,%XMM9

0x421585 VANDPD	%XMM10,%XMM15,%XMM2

0x42158a VANDPD	%XMM10,%XMM0,%XMM7

0x42158f JAE	423108

0x421595 VMOVAPD	%XMM11,%XMM6

0x421599 VMOVAPD	%XMM11,%XMM15

0x42159e MOV	0x178(%RSP),%RAX    [7]

0x4215a6 MOV	0x150(%RSP),%RSI    [7]

0x4215ae IMUL	%RAX,%R13

0x4215b2 ADD	%RCX,%RSI

0x4215b5 VANDPD	%XMM10,%XMM3,%XMM4

0x4215ba ADD	%R13,%RSI

0x4215bd MOV	0x130(%RSP),%R13    [7]

0x4215c5 MOV	0x158(%RSP),%RDI    [7]

0x4215cd VDIVSD	(%R13,%RSI,8),%XMM4,%XMM4    [2]

0x4215d4 VADDSD	%XMM6,%XMM4,%XMM0

0x4215d8 MOV	0x128(%RSP),%RDX    [7]

0x4215e0 ADD	%RDI,%R10

0x4215e3 VMULSD	%XMM2,%XMM0,%XMM5

0x4215e7 VMOVSD	(%R14),%XMM8    [4]

0x4215ec VMINSD	%XMM2,%XMM7,%XMM2

0x4215f0 VSUBSD	%XMM4,%XMM6,%XMM6

0x4215f4 VDIVSD	(%RDX,%R10,8),%XMM5,%XMM0    [8]

0x4215fa VSUBSD	%XMM4,%XMM13,%XMM5

0x4215fe VMULSD	%XMM7,%XMM5,%XMM5

0x421602 VDIVSD	%XMM8,%XMM5,%XMM5

0x421607 VMULSD	%XMM12,%XMM8,%XMM8

0x42160c VADDSD	%XMM5,%XMM0,%XMM0

0x421610 VMULSD	%XMM8,%XMM0,%XMM5

0x421615 VMINSD	%XMM2,%XMM5,%XMM7

0x421619 VMULSD	%XMM6,%XMM7,%XMM4

0x42161d VFMADD231SD	%XMM15,%XMM4,%XMM1

0x421622 VMULSD	%XMM3,%XMM1,%XMM3

0x421626 MOV	0x168(%RSP),%R10    [7]

0x42162e VMOVSD	%XMM3,(%R9,%RCX,8)    [1]

0x421634 MOV	%R8,%RCX

0x421637 CMP	%R10,%R8

0x42163a JE	421670

0x42163c INC	%R8

0x42163f VMOVSD	(%R15,%RCX,8),%XMM3    [6]

0x421645 VCOMISD	%XMM3,%XMM9

0x421649 JBE	421520

0x42164f MOV	0x108(%RSP),%EAX    [7]

0x421656 MOV	0x160(%RSP),%RDI    [7]

0x42165e MOVSXD	0x110(%RSP),%R10    [7]

0x421666 INC	%EAX

0x421668 MOV	%R12,%R13

0x42166b JMP	421536

0x423108 VMOVSD	0x7e370(%RIP),%XMM6    [5]

0x423110 VMOVAPD	%XMM14,%XMM15

0x423115 JMP	42159e

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 172 - 240

--------------------------------------------------------------------------------

172:             IF(vdiffdw.LE.0.0) wind=-1.0_8

[...]

214:         DO j=x_min,x_max+1

215:           IF(node_flux(j,k).LT.0.0)THEN

216:             upwind=k+2

217:             donor=k+1

218:             downwind=k

219:             dif=donor

220:           ELSE

221:             upwind=k-1

[...]

227:           sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor))

228:           width=celldy(k)

229:           vdiffuw=vel1(j,donor)-vel1(j,upwind)

230:           vdiffdw=vel1(j,downwind)-vel1(j,donor)

231:           limiter=0.0

232:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

233:             auw=ABS(vdiffuw)

234:             adw=ABS(vdiffdw)

235:             wind=1.0_8

236:             IF(vdiffdw.LE.0.0) wind=-1.0_8

237:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw)

238:           ENDIF

239:           advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter

240:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

Coverage (%)	Name	Source Location	Module
○97.66	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.34	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.04
CQA speedup if FP arith vectorized	2.08
CQA speedup if fully vectorized	2.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:172-172,advec_mom_kernel.f90:214-221,advec_mom_kernel.f90:227-240
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	12.50
P0 cycles	10.00
P1 cycles	10.00
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	0.50
P5 cycles	10.00
P6 cycles	6.60
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	6.40
P11 cycles	6.67
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	20.00
Nb stores	1.00
Nb stack references	11.00
FLOP/cycle	1.44
Nb FLOP add-sub	6.00
Nb FLOP mul	7.00
Nb FLOP fma	1.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.48
Bytes prefetched	0.00
Bytes loaded	148.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.63
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	14.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.86

Metric	Value
CQA speedup if no scalar integer	1.04
CQA speedup if FP arith vectorized	2.08
CQA speedup if fully vectorized	2.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:172-172,advec_mom_kernel.f90:214-221,advec_mom_kernel.f90:227-240
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	12.50
P0 cycles	10.00
P1 cycles	10.00
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	0.50
P5 cycles	10.00
P6 cycles	6.60
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	6.40
P11 cycles	6.67
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	20.00
Nb stores	1.00
Nb stack references	11.00
FLOP/cycle	1.44
Nb FLOP add-sub	6.00
Nb FLOP mul	7.00
Nb FLOP fma	1.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.48
Bytes prefetched	0.00
Bytes loaded	148.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.63
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	14.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.86

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:172-240
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:172,214-221,227-240.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 6 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.50 to 6.00 cycles (2.08x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

22 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

7: addition or subtraction (1 inside FMA instructions)
8: multiply (1 inside FMA instructions)
3: divide

The binary loop is loading 148 bytes (18 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	72
nb uops	72
loop length	354
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	0.86

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	10.00	6.67	6.67	0.50	10.00	6.60	0.50	0.50	0.50	6.40	6.67
cycles	10.00	10.00	6.67	6.67	0.50	10.00	6.60	0.50	0.50	0.50	6.40	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.50
Dispatch	10.00
DIV/SQRT	12.00
Overall L1	12.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	17%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	54%

INT+FP

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	42%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	19%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

6% of peak load performance is reached (11.84 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 42163f

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD 0x140(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x160(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
IMUL %R13,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RBX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RBX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x170(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%RSI,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R11,%RDX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD (%R11,%RAX,8),%XMM1,%XMM15	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM4,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM15,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM9,%XMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 421622 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1c22>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM0,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VANDPD %XMM10,%XMM15,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VANDPD %XMM10,%XMM0,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
JAE 423108 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3708>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPD %XMM11,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV 0x178(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x150(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VANDPD %XMM10,%XMM3,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ADD %R13,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x130(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x158(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD (%R13,%RSI,8),%XMM4,%XMM4	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VADDSD %XMM6,%XMM4,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x128(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM2,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R14),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM2,%XMM7,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM4,%XMM6,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD (%RDX,%R10,8),%XMM5,%XMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VSUBSD %XMM4,%XMM13,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM7,%XMM5,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM5,%XMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM12,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM8,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM2,%XMM5,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM15,%XMM4,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM1,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x168(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM3,(%R9,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 421670 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1c70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD (%R15,%RCX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM3,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 421520 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1b20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x108(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x160(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD 0x110(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 421536 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1b36>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD 0x7e370(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVAPD %XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 42159e <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1b9e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:172-240
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:229

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

22 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

7: addition or subtraction (1 inside FMA instructions)
8: multiply (1 inside FMA instructions)
3: divide

The binary loop is loading 148 bytes (18 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	72
nb uops	72
loop length	354
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	0.86

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	10.00	6.67	6.67	0.50	10.00	6.60	0.50	0.50	0.50	6.40	6.67
cycles	10.00	10.00	6.67	6.67	0.50	10.00	6.60	0.50	0.50	0.50	6.40	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.50
Dispatch	10.00
DIV/SQRT	12.00
Overall L1	12.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	17%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	54%

INT+FP

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	42%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	19%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

6% of peak load performance is reached (11.84 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 42163f

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD 0x140(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x160(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
IMUL %R13,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RBX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RBX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x170(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%RSI,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R11,%RDX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD (%R11,%RAX,8),%XMM1,%XMM15	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM4,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM15,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM9,%XMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 421622 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1c22>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM0,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VANDPD %XMM10,%XMM15,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VANDPD %XMM10,%XMM0,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
JAE 423108 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3708>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPD %XMM11,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV 0x178(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x150(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VANDPD %XMM10,%XMM3,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ADD %R13,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x130(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x158(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD (%R13,%RSI,8),%XMM4,%XMM4	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VADDSD %XMM6,%XMM4,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x128(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM2,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R14),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM2,%XMM7,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM4,%XMM6,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD (%RDX,%R10,8),%XMM5,%XMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VSUBSD %XMM4,%XMM13,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM7,%XMM5,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM5,%XMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM12,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM8,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM2,%XMM5,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM15,%XMM4,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM1,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x168(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM3,(%R9,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 421670 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1c70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD (%R15,%RCX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM3,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 421520 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1b20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x108(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x160(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD 0x110(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 421536 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1b36>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD 0x7e370(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVAPD %XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 42159e <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1b9e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code